CN100580638C

CN100580638C - Method and apparatus for implementing hardware level verification

Info

Publication number: CN100580638C
Application number: CN200710119586A
Authority: CN
Inventors: 樊荣
Original assignee: BEIJING BLX IC DESIGN Co Ltd
Current assignee: BEIJING BLX IC DESIGN Co Ltd
Priority date: 2007-07-26
Filing date: 2007-07-26
Publication date: 2010-01-13
Anticipated expiration: 2027-07-26
Also published as: CN101354674A

Abstract

The invention discloses a method and a device for realizing hardware level verification. The device comprises a basic development and verification board and an extended development and verification board which are connected with each other through an AMBA bus of a high-quality microprocessor bus framework, wherein the basic development and verification board reads and writes a CPU register through an EJTAG interface of a reinforced joint test action group and executes CPU IP verification, and the basic development and verification board and the extended development and verification board execute the CPU IP verification and SOC (system on a chip) verification through the AMBA bus. The method and the device have the advantages that: firstly, structures of the basic development and verification board and the extended development and verification board not only can conveniently realize design and development and functional verification of an SOC but also can complete the development and verification work of IP and particularly CPU IP; secondly, the cost can be reduced; and thirdly, system correction and extension are easier and realization is flexible and convenient.

Description

A kind of method and device of realizing hardware level verification

Technical field

(SOC, System-on-Chip) technology are meant a kind of hardware level verification method and the device that can realize SOC checking and IP checking simultaneously especially to the present invention relates to SOC (system on a chip).

Background technology

At current integrated circuit (IC, Integrated circuit) design field, SOC is a dark horse, and develops very rapid.SOC design based on silicon intellectual property (IP) is different from traditional application-specific IC (ASIC, Application Specific Integrated Circuit) design, and its design cycle is short, more can adapt to the needs in market.And the same with ASIC design in the past, SOC also is faced with the problem of field programmable gate array (FPGA, Field Programmable GateArray) hardware level verification.Present FPGA exploitation checking mainly based on single development board, be single FPGA, the situation of a plurality of FPGA is also arranged, usually towards the SOC in a field, and adopt the development board of motherboard+daughter board structure mostly be at IP particularly CPU IP develop and verify.

The FPGA exploitation witness plate of veneer is often developed voluntarily by each SOC design corporation, in this case, general target domain at the SOC design, peripheral hardware on the FPGA exploitation witness plate can be numerous can letter, but the structure of FPGA exploitation witness plate is normally fairly simple: core is the bigger FPGA of a slice, being used to place the SOC logic, is a large amount of phy chip peripheral hardwares, as ROM, Flash, various RAM etc. and expansion interface on every side.Peripheral hardware is decided according to the needs of SOC design, and which kind of logic interfacing is promptly arranged on the SOC, just needs which kind of peripheral hardware on the corresponding FPGA exploitation witness plate.Development phase or Qualify Phase at SOC all can download to SOC among the FPGA of FPGA exploitation witness plate with respect to the physics realization of determining FPGA, and debug.In addition, also released multiple FPGA exploitation verification platform at present, in the FPGA exploitation verification platform a plurality of large-scale FPGA have been arranged, be on a grand scale, application is also wider, and its design philosophy is identical with the description of front.

This single plate structure is the main flow of present FPGA exploitation witness plate, but it has certain limitation.At first, the scale of SOC is increasing at present, and complexity improves constantly, and this just needs the great FPGA of a slice, and like this, hardware circuit board is also bigger, and overall cost is very high.Secondly, the high FPGA exploitation witness plate of price is generally used for the SOC checking like this, there is no need and be applied to CPU IP checking.Once more, the structure of single FPGA exploitation witness plate itself just has the defective that is not easy to change, when the SOC design needs to increase some interface, and do not have corresponding peripheral hardware on the FPGA exploitation witness plate, even the design direction of SOC changes the necessary whole redesign of FPGA exploitation witness plate that all might cause high price to manufacture and design to some extent.

Except single plate structure, the structure of motherboard+daughter board also has application in the IP checking.As its name suggests, the structure of motherboard+daughter board has two exploitation witness plates, on the every exploitation witness plate a slice FPGA is arranged all, and the FPGA on the daughter board is used to place the IP logic, and the FPGA on the motherboard is used to place other logics, connects by interface between son, the motherboard.This structure is relatively flexible, but this design is mainly verified towards the exploitation of IP at present, as checking CPU IP.CPU IP logic is positioned on the FPGA of daughter board, and other minimum logics (comprising ROM, RAM, interface and serial ports etc.) that can satisfy the CPU operation place on the FPGA of motherboard.After the system start-up, CPU is debugged by strengthening combined testing action group (EJTAG, Enhanced Joint Test ActionGroup) interface, serial ports etc.Corresponding cpu bus or self-defined bus are adopted in the connection of two FPGA, but not the SOC system bus as advanced microprocessor bus architecture (AMBA, Advanced Microcontroller Bus Architecture) bus, makes system running speed low.In this case, because it is different with the SOC system bus to connect the bus structure of two FPGA, therefore, can not really realize the SOC checking.

In sum, the scheme that provides of prior art can't provide effective SOC checking and IP to verify in SOC simultaneously.

Summary of the invention

In view of this, fundamental purpose of the present invention is to provide a kind of method and device of realizing hardware level verification, realizes SOC checking and IP checking simultaneously effectively.

For achieving the above object, technical scheme of the present invention is achieved in that

A kind of device of realizing hardware level verification, comprise: develop witness plate and regarded as output controlling witness plate substantially, the two links to each other by advanced microprocessor bus architecture AMBA bus, wherein, basic exploitation witness plate is carried out CPU IP checking by strengthening the combined testing action EJTAG of group interface read-write CPU register; Basic exploitation witness plate and regarded as output controlling witness plate are carried out CPU IP checking and SOC (system on a chip) SOC checking by the AMBA bus.

Wherein, described basic exploitation witness plate comprises: the main control module of the SOC when CPU IP to be verified when CPU IP, EJTAG interface and needed clock generator of CPU IP and logic analyser interface, described CPU IP are verified for CPU IP or SOC checking; Described EJTAG interface is used to provide the read-write CPU interface of register; Described clock generator can select different clock frequencies to export; Described logic analyser interface is used for the docking port signal and analyzes.

Wherein, described regarded as output controlling witness plate comprises at least: the on-site programmable gate array FPGA, external interface circuit and the clock generator that are used to realize the SOC functional module.

Wherein, the FPGA on the described regarded as output controlling witness plate further comprises: AMBA bus structure and Synchronous Dynamic Random Access Memory sdram interface.

FPGA on the described regarded as output controlling witness plate further comprises: flash interface or UART UART serial ports or above the two combination.

Wherein, described basic exploitation witness plate uses the stone of processor IP, and then described regarded as output controlling witness plate has only a slice FPGA.

Wherein, described basic exploitation witness plate does not use the stone of processor IP, and then described basic exploitation witness plate and regarded as output controlling witness plate respectively comprise a slice FPGA.

A kind of method that realizes hardware level verification comprises: develop witness plate substantially and link to each other with the regarded as output controlling witness plate by the AMBA bus; Basic exploitation witness plate is carried out CPU IP checking by EJTAG interface read-write CPU register; Basic exploitation witness plate and regarded as output controlling witness plate are carried out CPU IP checking SOC (system on a chip) SOC checking by the AMBA bus.

Wherein, described execution CPU IP checking comprises: develop the relevant AMBA bus interface signal wire access bus of the CPU of witness plate substantially by expansion interface, and fill order.

Wherein, described order is from BIOS stored among FLASH or the ROM, or from the program of moving among the RAM.

According to scheme provided by the invention, at first, the structure of developing witness plate+regarded as output controlling witness plate substantially both can realize designing and developing and functional verification of SOC easily, also can finish the particularly exploitation checking work of CPU IP of IP; In fact, develop the independent use of witness plate substantially and can realize certain IP authentication function.Secondly, can reduce cost, because it is not only linear growth that the price of FPGA increases with capacity, use two less FPGA costs well below using the large-scale FPGA of a slice, adopt CPU IP stone chip if develop witness plate substantially, substitute FPGA, can when producing in batches, further reduce cost.Once more, owing to adopt the structure of exploitation witness plate+regarded as output controlling witness plate substantially, the correction of system, expansion become easily, make that realization is flexible.For basic exploitation witness plate, the mode of placing CPU IP kernel can be the FPGA form, and also stone chip form because external interface is in full accord, need not during replacement basic exploitation witness plate is carried out big change.For the regarded as output controlling witness plate, can need at different application, make different regarded as output controlling witness plates, so long as get final product based on the SOC design of AMBA structure, all can dock with basic exploitation witness plate, substantially develop witness plate without any change this moment, and the single relatively development board structure of the change of regarded as output controlling witness plate is also obviously little.The range of application that in fact this enlarged this FPGA exploitation verification system makes it have more versatility.

Description of drawings

Fig. 1 is the SOC basic structure synoptic diagram based on the AMBA bus;

Fig. 2 is for realizing the apparatus structure synoptic diagram of SOC checking and IP checking among the present invention;

Fig. 3 is for realizing the signal relation synoptic diagram of SOC checking and IP checking among the present invention;

Fig. 4 is basic exploitation witness plate structural representation among the present invention;

Fig. 5 is regarded as output controlling witness plate structural representation among the present invention.

Embodiment

Because at present the on-chip bus that adopts of SOC designing institute is mainly the AMBA bus, so be example with SOC among the present invention, specific implementation of the present invention is elaborated based on the AMBA design.One based on the SOC basic structure of AMBA bus as shown in Figure 1, all modules are the logic on the SOC, CPUIP and part high-speed interface are carried out bus (AHB by the senior high speed of AMBA bus, AdvancedHigh-performance Bus) is connected, other low-speed interfaces are connected to the advanced peripheral bus (APB of AMBA bus, Advanced Peripheral Bus), and by the APB bridge be connected with ahb bus.

Fig. 2 is for realizing the apparatus structure synoptic diagram of SOC checking and IP checking among the present invention, as shown in Figure 2, this device adopts the structure of basic exploitation witness plate+regarded as output controlling witness plate.Wherein, develop substantially and place the CPU IP kernel shown in Fig. 1 in the witness plate, this CPU core comprises master control AHB (AHB Master) interface, and other all possible modules all realize on the regarded as output controlling witness plate.Like this, two connection signals of developing between the witness plate are fixed, and need other signals less, promptly only need one group of ahb bus interface signal interconnection.Can on the regarded as output controlling witness plate, increase function corresponding according to the complexity that realizes SOC, substantially developing witness plate then remains unchanged, and use FPGA to realize processor IP or use stone to realize that processor IP can shared identical regarded as output controlling witness plate, develop witness plate substantially and be connected constant with signal between the regarded as output controlling witness plate.Consider from the angle that reduces cost,, then only need a slice FPGA can realize other functional modules on the regarded as output controlling witness plate if develop the stone that witness plate uses processor IP substantially; If do not use the stone of processor IP, then develop witness plate substantially and the regarded as output controlling witness plate respectively needs a slice FPGA, wherein, to develop substantially and be used on the witness plate realize that the FPGA of processor IP need not very high capacity, the resource that only can hold CPU IP gets final product.

Fig. 3 is for realizing the signal relation synoptic diagram of SOC checking and IP checking among the present invention, as shown in Figure 3, CPU IP checking is mainly carried out at basic exploitation witness plate, and the checking of peripheral IP can be finished on the regarded as output controlling witness plate.Can only carry out some simple CPU IP checkings at basic exploitation witness plate, mainly be the read-write of inner general-purpose register of CPU IP and control register, and this is a basic test, prove the CPU IP normal startup that powers on.When carrying out CPU IP checking, developing witness plate substantially can be by EJTAG interface read-write CPU register, as carrying out the read-write of CPU register by signals such as TCK, TMS, TDI, TDO, TRST.Finish more function if desired, then need on the regarded as output controlling witness plate, realize AMBA bus structure and flash memory (Flash) interface, Synchronous Dynamic Random Access Memory (SDRAM, SynchronousDynamic Random Access Memory) interface and UART (UART, UniversalAsynchronous Receiver/Transmitter) logic such as serial ports, promptly having realized a minimum system that can make the cpu system operation, in fact is exactly a little SOC.Basic exploitation witness plate and regarded as output controlling witness plate are carried out CPU IP checking and SOC checking by ahb bus to the regarded as output controlling witness plate.On the basic exploitation witness plate only is the basic test of finishing CPU IP, and how deep test, checking need be finished together with the regarded as output controlling witness plate.Whether need to finish more function and will see at first which kind of physical module (except that FPGA) has on the regarded as output controlling witness plate, for example, there is the Ethernet phy chip FPGA outside, can be at the inner exploitation of FPGA ethernet mac controller; And for example, there is the SDRAM chip FPGA outside, can the inner exploitation of FPGA sdram controller to SDRAM memory access control.Here do not need to realize the repertoire of AMBA bus, for example,, therefore, just do not need the bus arbitration of AMBA bus owing to have only a main equipment of CPU (master); Owing to do not have low-speed device, therefore, need not realize the bridge joint of high-speed bus yet to low speed bus.Store the Basic Input or Output System (BIOS) (BIOS of start-up system among the Flash, Basic Input/Output System), order among the BIOS reads to ahb bus one by one, the CPU of basic exploitation witness plate is by relevant master control AHB (AHB master) the interface signal line access bus of expansion interface (EX IF), and fill order, this order may also may come program of moving among the comfortable RAM or the like from BIOS stored among the FLASH/ROM.Order can be the realization of very simple CPU initialize routine, a kind of algorithm, complicated Cache operation or the like, the promptly any program that can verify CPU.Software debugging can be finished by the EJTAG interface: the EJTAG signal is connected to host (PC), CPU IP software Integrated Development Environment (IDE) on the host can be developed the CPU register of witness plate substantially by the EJTAG read-write, or by the read-write of regarded as output controlling witness plate Flash, RAM etc.Application software is downloaded to RAM and goes up execution, and in fact BIOS itself also can be downloaded on the RAM by host, has not just needed Flash in this case.Except access register, RAM and Flash, that IDE has is graphical, the characteristics of integrated user interface, can conveniently carry out code editor, tissue, engineering management etc.; IDE also supports higher level lanquage and assembly language single step tracking, breakpoint trace debug etc., can assist the on-line debugging of basic exploitation witness plate.The realization of UART is another the optional debugging method that substitutes EJTAG.When carrying out the SOC checking, similar with process described above, only according to different SOC designs, the logic content of regarded as output controlling witness plate will enrich manyly relatively, and BIOS need load the driving of corresponding module.Debugging method is still basic exploitation witness plate hardware environment is provided, and IDE realizes CPU register access, internal storage access, the download of software and realization software debugging (single step, breaking or the like).SOC verifies that needing basic exploitation witness plate and regarded as output controlling witness plate to unite finishes, and just at different applications, the regarded as output controlling witness plate can difference.The specific implementation and the CPU IP checking of SOC checking are similar, and difference is the heavier test at CPU of CPU IP checking, and application program can be very complicated, mainly is to see that CPU IP to the program implementation situation, takies situation etc. as processing time, cpu resource; And SOC checking will be verified each the module ruuning situation that comprises CPU IP and the contact situation of intermodule on the one hand, this just requires proving program to comprise initialization to each module, CPU is to the driving of peripheral module, still will run application on the other hand, checking CPU IP is to the ruuning situation of program implementation situation, whole SOC (realizing in FPGA).

Only comprise the least resource that realizes processor IP on the basic exploitation witness plate, as shown in Figure 4, develop witness plate substantially and comprise: CPU IP, EJTAG interface and needed clock generator of CPU IP and logic analyser interface etc.The main control module of SOC when CPU IP to be verified when wherein, CPU IP verifies for CPU IP or SOC checking; The EJTAG interface is used to provide the read-write CPU interface of register; Clock generator can select different clock frequencies to export; The logic analyser interface is used for the docking port signal and analyzes.If CPU IP adopts the FPGA form to realize, then approximately be operated in the frequency of 20～50MHz according to actual conditions; If CPU IP uses the stone form to realize that then frequency can reach 100MHz even 200MHz, to look the frequency that plate level interface can bear and revise and decide, present high-speed interface can adapt to the frequency of 200MHz.Adopt multi-form CPU IP, it is constant to develop the witness plate structure substantially.Clock generator is used for carrying out frequency and selects, and can dispose the inside and outside frequency of CPU IP by clock generator, is provided to clock on the regarded as output controlling witness plate simultaneously.Clock generator can utilize the crystal oscillator of self circuit to realize, also can import from the outside, perhaps receives the clock signal from the regarded as output controlling witness plate.The look-at-me of CPU IP is connected on the regarded as output controlling witness plate, realizes interruptable controller on the regarded as output controlling witness plate.On basic exploitation witness plate, keep the EJTAG interface, utilize the EJTAG debug function of CPU IP to carry out system debug, this also makes basic exploitation witness plate independently to use, carry out certain debugging work, carry out some simple CPU IP checkings at basic exploitation witness plate, mainly be the read-write of inner general-purpose register of CPU IP and control register, this is a basic test, prove the CPU IP normal startup that powers on.Logic analyser interface (Logic Monitor IF) is used for the docking port signal and monitors, analyzes.Basic exploitation witness plate also comprise FPGA download interface, be used to store the EEPROM of data download.In the practical application, can be directly data (logic that need realize at FPGA) be downloaded to FPGA, but data are not preserved after the power down; Also data curing can be saved in EEPROM, like this, after powering on, the data among the EEPROM can import FPGA at every turn.The power supply of basic exploitation witness plate needs the regarded as output controlling witness plate to provide.Expansion interface (EX IF) is used for connecting basic exploitation witness plate and regarded as output controlling witness plate, line between the two is very simple, mainly be three kinds of signals: the ahb bus master signal about 110, promptly the AHB Master Interface of CPU IP is connected to the bus structure of the AHB on the regarded as output controlling witness plate; The interruption of CPU IP, signal such as reset, clock is connected with power supply etc.; The expansion line, such as coprocessor interface being connected to the regarded as output controlling witness plate, perhaps other user logic signals.

The regarded as output controlling witness plate has comprised all logic function circuit except that CPU IP, as shown in Figure 5, comprise: be used to realize the FPGA (comprising the bus structure that realize AHB and APB), external interface circuit, clock generator of SOC functional module etc., the user is according to the design verification needs, can design the regarded as output controlling witness plate voluntarily, increase the function that needs.AHB, APB bus structure and SOC functional module realize in FPGA.SDRAM, codec, Ethernet PHY, USB PHY, UART are the external physical module, and the logical circuit of realizing among the FPGA is used to control these external modules.A slice FPGA on the regarded as output controlling witness plate deposits AMBA system (comprising AHB and APB) and all user logic modules.The expansion interface of regarded as output controlling witness plate is a link of developing the witness plate signal substantially, inserts FPGA.Other exterior I/O of FPGA all use as user I/O, according to the realization logic among the FPGA, such as SDRAM, PCI, Audio, MAC, USB etc., have the external circuit of these logic interfacings on the regarded as output controlling witness plate.The regarded as output controlling witness plate has basic memory unit such as FLASH, Boot ROM, SRAM, SDRAM.Inner interruptable controller and the GPIO that realizes the APB system of FPGA, button interrupt source is arranged on the regarded as output controlling witness plate, be input to the interruptable controller of FPGA, the interruptable controller output signal is connected to basic exploitation witness plate by expansion interface, dial wiretap (DIP) and be used for to the GPIO input signal, LED is used for showing the GPIO signal.By stirring DIP comes set or reset by hand, the SOC system that realizes based on FPGA is resetted, also may be that some basic I/O detect, import some signal by DIP to GPIO, correspondingly, whether may observe LED shows consistent with expectation.There are clock generator and reset signal to produce on the regarded as output controlling witness plate, can pass through the signal of user I/O (User I/O) use, also can pass to basic exploitation witness plate to corresponding signal from basic exploitation witness plate.The power supply of regarded as output controlling witness plate also will be given the power supply of basic exploitation witness plate except self powers.In addition, the regarded as output controlling witness plate has the logic analyser interface too, can monitor, analyze part even all users' I/O signal as required.

The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.

Claims

1, a kind of device of realizing hardware level verification is characterized in that, this device comprises: develop witness plate and regarded as output controlling witness plate substantially, the two links to each other by advanced microprocessor bus architecture AMBA bus, wherein,

Basic exploitation witness plate is carried out CPU IP checking by strengthening the combined testing action EJTAG of group interface read-write CPU register;

Basic exploitation witness plate and regarded as output controlling witness plate are carried out CPU IP checking and SOC (system on a chip) SOC checking by the AMBA bus.

2, device according to claim 1 is characterized in that, described basic exploitation witness plate comprises: CPU IP, EJTAG interface and needed clock generator of CPU IP and logic analyser interface, wherein,

The main control module of SOC when CPU IP to be verified when described CPU IP verifies for CPU IP or SOC checking;

Described EJTAG interface is used to provide the read-write CPU interface of register;

Described clock generator can select different clock frequencies to export;

Described logic analyser interface is used for the docking port signal and analyzes.

3, device according to claim 1 is characterized in that, described regarded as output controlling witness plate comprises at least: the on-site programmable gate array FPGA, external interface circuit and the clock generator that are used to realize the SOC functional module.

4, device according to claim 3 is characterized in that, the FPGA on the described regarded as output controlling witness plate comprises: AMBA bus structure and Synchronous Dynamic Random Access Memory sdram interface.

5, device according to claim 4 is characterized in that, the FPGA on the described regarded as output controlling witness plate further comprises: flash interface or UART UART serial ports or the combination of the two.

According to the arbitrary described device of claim 1 to 5, it is characterized in that 6, described basic exploitation witness plate uses the stone of processor IP, then described regarded as output controlling witness plate has only a slice FPGA.

According to the arbitrary described device of claim 1 to 5, it is characterized in that 7, described basic exploitation witness plate does not use the stone of processor IP, then described basic exploitation witness plate and regarded as output controlling witness plate respectively comprise a slice FPGA.

8, a kind of method that realizes hardware level verification is characterized in that, this method comprises:

Basic exploitation witness plate links to each other with the regarded as output controlling witness plate by the AMBA bus;

Basic exploitation witness plate is carried out CPU IP checking by EJTAG interface read-write CPU register;

9, method according to claim 8 is characterized in that, described execution CPU IP checking comprises: develop the relevant AMBA bus interface signal wire access bus of the CPU of witness plate substantially by expansion interface, and fill order.

10, method according to claim 9 is characterized in that, described order is from BIOS stored among FLASH or the ROM, or from the program of moving among the RAM.