CN100583414C - 具有埋入衬底的栅的动态随机存取存储器晶体管及其形成方法 - Google Patents

具有埋入衬底的栅的动态随机存取存储器晶体管及其形成方法 Download PDF

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CN100583414C
CN100583414C CN200580038056A CN200580038056A CN100583414C CN 100583414 C CN100583414 C CN 100583414C CN 200580038056 A CN200580038056 A CN 200580038056A CN 200580038056 A CN200580038056 A CN 200580038056A CN 100583414 C CN100583414 C CN 100583414C
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semiconductor substrate
source
drain region
transistor
grid
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CN101057322A (zh
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S·唐
G·哈勒
K·布朗
T·E·艾伦三世
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Micron Technology Inc
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Abstract

本发明包括具有半导体衬底(12)的晶体管器件(69)，所述衬底具有上表面。一对源/漏区(41，59)在半导体衬底内形成以及沟道区(46)在半导体衬底内形成并且通常相对于半导体衬底的上表面垂直延伸。栅(54)在半导地衬底内所述的一对源/漏区(41，59)之间形成并且可围绕沟道区(46)和/或源/漏区中的一个。

Description

具有埋入衬底的栅的动态随机存取存储器晶体管及其形成方法
技术领域
本发明涉及形成半导体构造(如存储电路)的方法，具体涉及形成存储单元、DRAM和晶体管的方法。
背景技术
由于集成电路的尺寸持续缩小，因此要继续努力寻找形成集成电路结构和有关集成电路的新颖方法，所述新颖方法对目前使用的这些方法以及因此形成得到的结构加以改进。一种类型的集成电路是存储电路和阵列。这种电路已经并将继续成为集中努力减小电路尺寸、提高这种电路得以操作的速度、以及维持或增强该电路实施其存储功能能力方面的焦点。行业设计者不断地探索在未牺牲阵列性能的情况下减小存储电路尺寸的方法。
一种这样的方法是改进与存储电路结合的晶体管结构的设计。晶体管结构或器件大量用于半导体电路。例如，晶体管结构可以结合进存储电路(例如动态随机存取存储器(DRAM))和逻辑电路。DRAM电路通常包括通过分别被称为字线和数位线(位线)的若干行和列互连的存储单元的阵列。典型的DRAM存储单元包含与电荷存储器件或数据存储元件(如电容器件)相连的晶体管结构。
典型的晶体管结构包含一对源/漏区之间的沟道区和被配置成可通过沟道区使源/漏区彼此电连接的栅。在半导体构造中使用的晶体管构造将被半导体衬底所支持。半导体衬底将具有可以被认为是限定水平方向或水平表面的主要表面。基于沟道区相对于半导体衬底的主要表面的取向，可将晶体管器件分成两个大类。具体地说，具有主要平行于衬底的主要表面的沟道区的晶体管结构被称为平面晶体管结构，并且具有通常垂直于衬底的主要表面的沟道区的晶体管结构被称为垂直晶体管结构。因为晶体管器件的源和漏区之间的电流发生通过沟道区，基于电流方向以及沟道区的通常取向可将平面晶体管器件和垂直晶体管器件区分开来。具体地说，垂直晶体管器件是其中器件的源和漏区之间的电流主要基本上垂直于半导体衬底的主要表面的器件，并且平面晶体管器件是其中源和漏区之间的电流主要平行于半导体衬底的主要表面的器件。
由于其中利用垂直晶体管器件可获得相对于平面晶体管器件的压缩密度方面的优势，在可以将垂直晶体管器件结合进集成电路应用的方法的开发方面存在有持续的兴趣。在试图生产半导体应用所希望的大量垂直晶体管器件阵列同时维持器件的适当性能特征时通常会遭遇到困难。例如，所提供的用于形成垂直晶体管器件的方法包括形成或生长自半导体衬底的主要或水平表面向上延伸的外延硅柱或支柱。在垂直晶体管器件的现有设计中，外延硅柱或支柱被用作晶体管沟道。然而，该设计产生若干问题。例如，伴随潜在的单元泄漏问题，高缺陷密度产生。另外，该设计促进了晶体管沟道中的浮体效应，其复杂化并增加了控制晶体管的栅阈值电压的难度。因此，期望开发用于改进和/或至少减少或减轻这些问题的、制造垂直晶体管器件的新方法。
发明内容
在一个方面，本发明包含包括有半导体衬底的晶体管器件。该器件还包括形成的在半导体衬底内延伸的栅、在栅上方形成的栅介质、在栅的相对侧形成的一对源/漏区、以及在半导体衬底内形成的沟道区。
在另一个方面，本发明包含包括有半导体衬底的晶体管器件，所述半导体衬底具有上表面。一对源/漏区在半导体衬底内形成。沟道区在半导体衬底内形成并且通常相对于半导体衬底的上表面垂直延伸。栅在源/漏区对之间形成。
在又一个方面，本发明包含半导体构造，所述半导体构造包括自半导体衬底的上表面向上延伸的传导柱。源/漏区在半导体衬底内传导柱下面形成并且与传导柱电耦合。晶体管沟道在源/漏区的下面延伸并且栅在半导体衬底内邻近晶体管沟道形成。
在另一个方面，本发明包含形成半导体构造的方法，所述方法包括为半导体衬底提供开口。氧化膜在半导体衬底上方在开口内形成。传导栅材料在氧化膜上方提供并且填充开口。一对扩散区在半导体衬底内栅材料的相对侧上形成并且沟道区被限定为在半导体衬底内通常垂直延伸。
附图说明
下面参考附图对本发明的优选实施例进行描述。
图1是本发明示范方面的预备处理阶段时的半导体构造的顶部平面片断示意图。
图2是沿图1片断的线条2-2所作的横截面视图。
图3是图1的预备处理阶段之后的处理阶段时所示的图1片断的视图。
图4是沿图3片断的线条4-4所作的横截面视图。
图5是图3的处理阶段之后的处理阶段时所示的图3片断的视图。
图6是沿图5片断的线条6-6所作的横截面视图。
图7是旋转了90度的图5片断的视图。
图8是沿图7片断的线条8-8所作的横截面视图。
图9是图5的处理阶段之后的处理阶段时所示的图5片断的视图。
图10是沿图9片断的线条10-10所作的横截面视图。
图11是旋转了90度的图9片断的视图。
图12是沿图11片断的线条12-12所作的横截面视图。
图13是图9的处理阶段之后的处理阶段时所示的图9片断的视图。
图14是沿图13片断的线条14-14所作的横截面视图。
图15是旋转了90度的图13片断的视图。
图16是沿图15片断的线条16-16所作的横截面视图。
图17是图13的处理阶段之后的处理阶段时所示的图13片断的视图。
图18是沿图17片断的线条18-18所作的横截面视图。
图19是旋转了90度的图17片断的视图。
图20是沿图19片断的线条20-20所作的横截面视图。
图21是图17的处理阶段之后的处理阶段时所示的图17片断的视图。
图22是沿图21片断的线条22-22所作的横截面视图。
图23是旋转了90度的图21片断的视图。
图24是沿图23片断的线条24-24所作的横截面视图。
图25是图21的处理阶段之后的处理阶段时所示的图21片断的视图。
图26是沿图25片断的线条26-26所作的横截面视图。
图27是旋转了90度的图25片断的视图。
图28是沿图27片断的线条28-28所作的横截面视图。
图29是图25的处理阶段之后的处理阶段时所示的图25片断的视图。
图30是沿图29片断的线条30-30所作的横截面视图。
图31是旋转了90度的图29片断的视图。
图32是沿图31片断的线条32-32所作的横截面视图。
图33是图29的处理阶段之后的处理阶段时所示的图29片断的视图。
图34是沿图33片断的线条34-34所作的横截面视图。
图35是旋转了90度的图33片断的视图。
图36是沿图35片断的线条36-36所作的横截面视图。
图37是图33的处理阶段之后的处理阶段时所示的图33片断的视图。
图38是沿图37片断的线条38-38所作的横截面视图。
图39是旋转了90度的图37片断的视图。
图40是沿图39片断的线条40-40所作的横截面视图。
图41是图37的处理阶段之后的处理阶段时所示的图37片断的视图。
图42是沿图41片断的线条42-42所作的横截面视图。
图43是旋转了90度的图41片断的视图。
图44是沿图43片断的线条44-44所作的横截面视图。
图45是图41的处理阶段之后的处理阶段时所示的图41片断的视图。
图46是沿图45片断的线条46-46所作的横截面视图。
图47是旋转了90度的图45片断的视图。
图48是沿图47片断的线条48-48所作的横截面视图。
图49是图45-48的处理阶段之后的处理阶段时的、本发明一个示范实施例的最后处理阶段时的半导体构造的横截面片断视图。
图50是旋转了90度的图49片断的视图。
具体实施方式
本发明公开内容的提出是为了推动美国专利法“促进科学和实用技术的进步”(第八部分，第一款)的立宪目的。
关于存储集成电路，存储阵列中的每个存储单元所要求的衬底上方的面积部分地确定了该器件的容量。这个面积是每个存储单元内元件数量和每个元件尺寸的函数。对于传统存储单元来说，该面积被表示为8F2，其中F代表用于光刻限定特征的最小特征尺寸并且传统单元面积的尺度为2Fx4F。这些存储单元的尺度和面积通过参考2003年12月25日公布的美国专利申请公布No.2003/0234414 A1是很容易理解的，该专利申请的公开内容通过引用而被结合于此。美国专利申请公布No.2003/0234414 A1公开了现有技术的存储器，其中存储单元具有大约为4F2的单元面积。通过回顾美国专利申请公布No.2003/0234414 A1并且将这样的公开内容与本发明的公开内容进行比较，应当理解，本发明公开了包括为4F2量级的存储单元面积的存储电路。
现在参见图1和2(图2是图1的横截面视图)，半导体构造10包含衬底12，所述衬底12具有通常水平取向并被可选地描述为上表面的主要表面13。衬底12可包含、基本上由、或者由单晶半导体材料构成，并且在特定方面将包含、基本上由、或者由轻微掺杂有适当的本底类型的掺杂剂的单晶硅构成。例如衬底12可以是单晶硅晶片的一部分。为了有助于解释下面的权利要求，术语“半导电衬底”和“半导体衬底”被限定为指包含半导体材料的任何构造，包括但不限于如半导体晶片这样的大块半导体材料(或单独或在其上包含有其他材料的组合中)以及半导体材料层(或单独或在包含有其他材料的组合中)。术语“衬底”指任何支持结构，包括但不限于上述的半导体衬底。在一个示范实施例中，衬底12包含大块半导体衬底或大块晶片，例如单晶硅衬底或晶片。
仍然参见图1-2，隔离区14在衬底12上形成。在一个示范实施例中，隔离区14包含浅槽隔离(STI)区。隔离区14通常以平行且间隔行的方式延伸，使得衬底12的区域16位于隔离区14的各行之间。衬底12的区域16被隔离区14所限定并且被配置成平行且间隔行，其具有上表面13。
参见图3和4(图4是图3的横截面视图)，氮化层18在衬底12的上表面13和隔离区14上方沉积。氮化层18的示范厚度，也就是其中氮化层18自上表面13向上延伸的高度，在大约2000埃至大约3000埃之间变化。
参见图5-8，应当理解，所有四幅图代表相同的处理步骤。图5-6代表第一取向并且图7-8代表根据图5-6的取向被调整了90度的第二取向。氮化层18被形成图案并被蚀刻以形成向下延伸至衬底12的槽20(图8)，从而使衬底12的上表面部分22曝光。槽20还使隔离区14的隔离区部分24曝光。使得氮化层18被形成图案，成为取向垂直于隔离区14的方向、通常以间隔并平行关系延伸的氮化物行或流道(runner)18。衬底12的上表面部分22通常被隔离区14的隔离区部分24和氮化物行18所限制，并且通常被成形为正方形。在一个示范实施例中，蚀刻步骤包括范围自0至大约300埃的衬底的过蚀刻。
参见图9-12，隔离区部分24被蚀刻以使隔离区14凹进，在高度上低于衬底12的上表面部分22，从而留下隔离区14的凹面26(图10)。在一个示范实施例中，蚀刻过程包含反应离子蚀刻(R.I.E.)并且将选择性地至氮化物流道18和衬底12的曝光硅，例如上表面部分22。凹槽蚀刻使最初被隔离区14的绝缘材料覆盖的的衬底12的侧壁27曝光。使隔离区14凹进上表面部分22下面大约500至大约1500埃的范围，其中另一个示范的凹进范围为大约800至大约1500埃。在一个示范的实施例中，凹面26和上表面部分22之间的凹进距离等于大约1000埃。利用被称为湿氢氟酸(HF)蚀刻的示范的清洁蚀刻，实施清洁蚀刻以从侧壁27和衬底12的上表面部分22上移去剩余的氧化物。
参见图13-16，氮化物衬垫28被设于衬底12和在其上形成的结构上方，以保护隔离区14的曝光部分(如图9-12中说明的凹面26)。在一个示范实施例中，氮化物衬垫28的厚度在大约30至大约100埃之间变化。设置牺牲层30(比如，旋涂玻璃(SOG)层)，以填充氮化物流道18之间的槽20。牺牲层30的其他示范材料包括硼磷硅玻璃(BPSG)和/或TEOS层。实施平面蚀刻以使SOG层30平面化直至平面蚀刻在氮化物行18处停止，其中氮化物行18起到蚀刻停止的作用。示范的平面蚀刻包含CMP(化学机械抛光)处理。
参见图17-20，SOG层30被形成图案并且被选择性地蚀刻以移去SOG层30的若干部分从而形成穿过SOG层30的开口31以便使衬底12的上表面部分22上方的氮化物衬垫28曝光。氮化物衬垫28的曝光部分的示范配置是正方形。SOG层30的若干部分在氮化物流道18之间保持为自衬底12向上延伸的塔柱，其中塔柱的示范配置为矩形。氮化物衬垫28的曝光部分被移去以使衬底12的上表面部分22曝光。用来从上表面部分22上方移去氮化物衬垫28的若干部分的示范蚀刻包括选择性氮化物蚀刻。在自上表面部分22上移去氮化物衬垫28的若干部分之后，开口31延伸到上表面部分22并且被SOG层30的塔柱和氮化物行18限定或邻接。示范的选择性氮化物蚀刻将过度蚀刻氮化物(例如氮化物行18)达0至大约300埃并且优选地在硅衬底12处停止。在一个示范实施例中，衬底12的曝光的上表面部分22限定了衬底12的一般表面面积，其将用来或充当随后形成的器件和/或结构的有效面积。
参见图21-24，薄层绝缘层(例如TEOS层)在硅衬底12上方形成并填充开口31。示范的TEOS层被各向异性蚀刻以在氮化物行18和SOG层30上方形成牺牲TEOS隔片34。示范的蚀刻包括反应离子蚀刻，留下牺牲TEOS隔片34从氮化物行18和SOG层30的侧面侧向延伸达大约200至大约500埃。牺牲TEOS隔片34使开口31变窄，留下通常为圆柱形的开口32使上表面部分22的较小表面面积曝光。在一个示范实施例中，TEOS隔片34改进了可能用于设置在硅衬底12的上表面22上方或之上的随后形成的结构的临界尺寸。
参见25-28，在某些但是并非所有的实施例中，氮化物材料被设置于硅衬底12上方以填充圆柱形开口32并且接着被各向异性蚀刻从而在牺牲TEOS隔片34上方形成另一个氮化物衬垫36(第一氮化物衬垫是28)。示范的各向异性蚀刻将提供具有从大约50至大约200埃变化的厚度的氮化物衬垫36。在各向异性蚀刻以形成氮化物衬垫36之后，实施反应离子蚀刻以自硅衬底12的上表面部分22上移去氮化物衬垫36，其中硅衬底12的上表面部分22再次被曝光。在一个示范实施例中，氮化物衬垫36将在随后的蚀刻处理期间和/或随后的硅化处理期间保护TEOS隔片34。
参见图29-32，在示范的实施例中，可以实施进一步的蚀刻和平面化处理以相对于硅衬底12在高度上使氮化物行18和SOG层30的上表面降低到上表面部分22上方的预选高程或高度。氮化物行18和SOG层30的这种预选高度便于随后形成的与衬底12有关的外延结构的预选高度的形成。所形成的柱或支柱38从硅衬底12的曝光的上表面部分22向上延伸穿过圆柱形开口32。在一个示范实施例中，柱或支柱38包含自硅衬底12的曝光上表面部分22生长或形成的外延硅。柱38具有上表面39并且在一个示范实施例中，所形成的上表面39在高度上低于氮化物行18的上表面47，其中示范的高程差大约是1000至大约1500埃。示范的柱38包含大约1000至大约1500埃的高度(从大约上表面部分22至上表面39测得的)。另一方面，还可以根据相对于自硅衬底12延伸的氮化物行18的高度的百分比高度关系来考虑外延硅柱38的示范高度。例如，所形成的外延硅38从上表面部分22延伸到氮化物行18的高度的大约50％至大约70％以内，以及另一个示范范围为氮化物行18的高度的大约60％至大约65％。在某些实施例中，外延硅柱38将用作或充当电荷存储器件或数据存储元件(例如电容器件)和在随后的处理中形成的晶体管之间的电触点，这将在下面进行更全面地解释。从另一方面考虑，柱38将用来或充当结点区域，例如源/漏区，这一点在后面将进行更全面地解释。
形成外延硅柱38的示范备选过程是在衬底12上方沉积传导材料，其中圆柱形开口32被填充了传导材料。在这个备选过程中，自圆柱形开口32向外延伸的传导材料通过示范的平面或薄层蚀刻被移去，优选地向下到达氮化物行18的上表面47。传导材料接着被凹进成圆柱形开口32，留下传导材料在高度上低于氮化物行18的上表面47，其中示范的高程差是大约1000至大约1500埃。示范的传导材料包括未掺杂或掺杂的多晶硅，其中未掺杂的多晶硅在某个处理阶段将被掺杂。
仍然参见图29-32，传导注入(图中未示出)被实施以将传导掺杂剂提供到衬底12的上表面部分22从而形成扩散区或结点41。在注入方法的一个示范实施例中，传导掺杂剂基本上穿过柱38而被注入，基本上将传导掺杂剂的整体留在硅衬底12内。另一方面，传导掺杂剂的一部分保留在柱38中，从而留下柱38导电形成扩散区或结点41的一部分。示范的扩散区41包含源/漏区，比如漏区。在另一个示范实施例中，柱38被传导掺杂，但是未形成扩散区或结点41的一部分，并且因此形成随后形成的晶体管的扩散区或结点41和电容器之间的电触点。在又一个示范实施例中，柱38和扩散区41包含晶体管的一对源/漏区中的一个的整体，其中柱38电耦合至随后形成的电容器。在示范的处理方法中，传导注入(图中未示出)被实施以将传导掺杂剂基本上仅提供到柱38内并且接着柱38被退火以从柱38将传导掺杂剂向外扩散进入硅衬底12从而至少形成扩散区41的一部分。在备选的示范实施例中，未形成扩散区41，其中传导注入(图中未示出)被实施以将传导掺杂剂基本上仅提供到柱38内，其中柱38包含一对源/漏区中的一个的整体。另一方面，扩散区41还包含一对源/漏区中的一个的一部分并且柱38包含该对源/漏区中的一个的另一部分。
应当理解，示范的柱38通常是环形的或圆柱形的，并且可能或不可能具有在可选地形成的氮化物衬垫36和/或TEOS隔片34之间的空的空间。氮化物材料40被设于衬底12上方以及圆柱形开口32中以填充柱38、氮化物衬垫36和/或TEOS隔片34之间的任何空的空间并将氮化物材料40设于柱38和SOG层30的上方。氮化物材料40被深腐蚀以形成上表面49，所述上表面49被凹进，其在高度上低于SOG层30的上表面37并且低于氮化物流道18的上表面47(氮化物材料40被示出为具有结合的可选氮化物衬垫36)。使氮化物材料40凹进的示范蚀刻包括平面或薄层反应离子蚀刻，其使氮化物材料40凹进以使SOG层30和TEOS隔片34曝光。示范的氮化物材料40是充当阻挡或硬掩模40的牺牲层，以在随后的处理(比如移去SOG层30和TEOS隔片34)期间保护外延硅柱38。
参见图33-36，湿法蚀刻或蒸汽蚀刻被实施以移去SOG层30和TEOS隔片34，并且优选地完全移去SOG层30和TEOS隔片34。示范的蚀刻包括选择性蚀刻，以在氮化物和硅材料如氮化物衬垫28、硬掩模40、氮化物流道18和硅衬底12的上表面部分22处停止蚀刻。选择性蚀刻形成被氮化物衬垫28、柱38(包括硬掩模40)和氮化物流道18限定的开口42。示范的选择性蚀刻包括稀释的氢氟酸蚀刻和/或缓冲氧化物蚀刻。
参见图37-40，干法/湿法氮化物穿孔蚀刻被实施以从隔离区14、硅衬底12、和上表面部分22的上方移去氮化物衬垫28。穿孔蚀刻还从柱38移去硬掩模40的若干部分。在示范的实施例中，直接在柱38上方的硬掩模40的厚度基本上大于柱38的侧面上方的硬掩模40的厚度，以允许穿孔蚀刻能够从柱38移去硬掩模40的若干侧面部分同时将硬掩模40的基本部分直接留在柱38上。
仍然参见图37-40，选择性干法蚀刻被实施以移去邻近柱38的衬底12的上表面部分22并且向下到隔离区14。选择性蚀刻还移去隔离区14的若干部分并且留下硅衬底12的若干部分直接保持在柱38的下面或之下并称为硅支持结构46。示范的硅支持结构46通常是环形或圆柱形的，类似于在高度上于硅支持衬底结构46上方延伸的柱38。选择性蚀刻扩大了开口42以形成具有由硅支持结构46、硅衬底12的上表面48、和隔离区14的上表面50限定的底部外围的开口44。在一个示范实施例中，穿孔蚀刻将蚀刻或使硅衬底12凹进以稍微降低隔离区14的上表面50，留下上表面48在高度上低于上表面50。
仍然参见图37-40，绝缘薄膜52(例如氧化物)在硅衬底12的曝光部分和柱38的曝光部分上方形成。硅衬底12的曝光部分包括由上表面48和硅支持结构46限定的开口44的底部外围。柱38的曝光部分包括柱38的侧壁。在一个示范实施例中，绝缘薄膜52将包含二氧化硅并用来或充当用于随后形成的晶体管的栅氧化层或栅介质。形成栅介质52的示范方法包括在上表面48的曝光硅表面、硅支持结构46和柱38的侧壁上生长氧化物。
在一个示范实施例中，硅支持结构46将用来或充当用于随后形成的晶体管的沟道的若干部分。因此，从柱38的底部部分至上表面48测得的硅支持结构46的长度将通常限定随后形成的晶体管沟道46的垂直长度。此外，因为晶体管沟道46相对于衬底12的取向在通常垂直或正交方向上延伸，并且从另一方面说来，因为晶体管沟道46垂直于衬底12的水平或主要上表面(上表面部分22未示出但是作为柱38和衬底12之间的接触面存在)延伸，晶体管沟道46将在示范实施例中限定示范的垂直晶体管设计。另外，示范的垂直晶体管设计将包括示范实施例中的垂直围绕晶体管或垂直围绕栅晶体管。应当理解，晶体管沟道46(或者称为垂直沟道46)的长度将取决于选择性蚀刻处理步骤，例如选择性蚀刻的时间长度被允许移去和向下蚀刻进硅衬底12(即选择性蚀刻进入衬底12的深度)。
参见图41-44，传导材料在栅介质52上方沉积并且将用来或充当晶体管栅或字线54。形成用于晶体管栅54的传导材料的示范方法包括在开口44内沉积多晶硅材料，通过向下至氮化物流道18的CMP处理移去多晶硅材料的若干部分，并且接着使多晶硅材料凹进开口44内以降低外延硅柱38。例如，所形成的晶体管栅54的上表面55在高度上低于外延硅柱38的上表面39大约1000埃。在一个示范实施例中，晶体管栅54的多晶硅材料被凹进以形成在高度上低于衬底12的上表面的上表面55(例如，柱38和衬底12之间的接触面)。利用包含硅化钛和硅化钴的示范硅，可选的硅化层(图中未示出)在晶体管栅54的上方形成。
参见图45-48，绝缘材料或层56在硅衬底12、栅结构54、外延硅柱38和氮化物流道18上方形成。绝缘层56填充开口44。示范的绝缘层56包括旋涂玻璃层和TEOS层。绝缘层56的最外面部分通过CMP或其他平面蚀刻方法被移去以使氮化物流道18曝光，留下绝缘层56在各自氮化物流道18之间以行配置延伸。接下来，氮化物流道被形成图案并且被选择性蚀刻以形成伸过氮化物流道18的开口62从而使衬底12的上表面部分58曝光。应当理解，氮化物流道18的若干部分保持从硅衬底12以及其上方向上延伸。示范的硅衬底12的上表面部分58被通常配置成正方形并且与绝缘层56和保留在硅衬底12上方的氮化物流道18的若干部分邻接或被其围绕。传导注入(图中未示出)被实施以将传导掺杂剂提供到衬底12的上表面部分58从而形成有效面积59，例如扩散区或结点。在一个示范实施例中，扩散区59将包含用于随后形成的器件(例如晶体管)的源/漏区59。在又一个示范实施例中，扩散区59将包含源/漏区，用来与扩散区或结点41补充和协同操作。示范的扩散区59包含一对源/漏区中的一个，例如源区。
参见图49-50，这样的图形说明了按照某些示范实施例的、在图1-48的处理阶段之后(例如图45-48的处理阶段之后)的处理阶段的半导体构造100。图49表示类似于图46的可视取向的、在随后处理阶段的半导体构造100的可视取向。图50表示类似于图48的可视取向的、在随后处理阶段的半导体构造100的可视取向。应当了解，图50是图49的半导体构造100根据图49视图的取向旋转了90°的视图。图49-50说明了与示范的电荷耦合器件或数据存储元件(如电容器件)电耦合的示范的晶体管器件。这样的晶体管和电容器的示范组合表示包含存储单元(如DRAM)的存储器和/或逻辑电路。示范的晶体管器件通常被标以数字69并且示范的电荷存储器件或数据存储元件(如电容器件)通常被标以数字80。
示范的晶体管69包含栅54、栅介质52和源/漏区41和59(图50)。示范的晶体管69还包括通常表示为衬底12的区域的沟道，其中在图50中示出的电流71从源/漏区59至源/漏区41围绕栅54(和栅介质52)延伸。沟道的示范部分包含在高度上低于源/漏区41直接延伸的硅支持结构46。由硅支持结构46限定的示范的沟道部分是硅衬底12的圆柱形或环形部分。栅54通常垂直向下延伸到衬底12，通常垂直于硅衬底12的上表面(通常由源/漏区41和59的水平顶线表示的上表面，例如柱38和源/漏区42之间的接触面)。栅54被间隔并且通过栅介质52与硅衬底12绝缘。栅54相对于硅衬底12垂直延伸。然而，应当理解，栅54围绕或环绕由硅支持结构46限定的沟道部分。因此，示范的栅54将限定用于垂直晶体管的垂直围绕栅，例如垂直围绕栅晶体管。在示范的实施例中，如果柱38被限定为电触点并且不是限定为源/漏区，则晶体管69的整体在硅衬底或大块晶片12内形成。从另一方面来说，晶体管69在晶片12的最上面的表面处或之下形成。
示范的源/漏区41包含漏区。示范的源/漏区59包含源区。在一个示范实施例中，单个源/漏区59将包含用于晶体管69的整个源区。在另一个示范实施例中，在栅54的相对两侧上形成的一对源/漏区59将包含用于晶体管69的整个源区。在一个实施例中，晶体管69的激活建立从源区59向下通过下面的硅衬底12并围绕栅54底端而后返回向上通过沟道部分46并且到达漏区41的电流71。在图45-48之后的处理期间，直接在柱38上方的硬掩模40被移去并且直接在硬掩模40上方的绝缘层56的若干部分被移去以使柱38的上表面曝光。传导材料102在柱38的上方形成并与之相接触从而形成电触点。示范的传导材料102是多晶硅以形成多晶硅插头或单元插头102，用于经由柱38将晶体管69电耦合至随后形成的器件，如电容器80。
示范的电容器80包含底部单元板或存储结点72、存储结点72上方的电容器介质73和电容器介质73上方的顶部单元板74。电容器80通过外延硅柱38和多晶硅插头102电耦合至晶体管69，其中多晶硅插头102接触并电耦合至存储结点72。所形成的传导插头61(图50)从源/漏区59向上延伸并与之电耦合。传导插头61还接触数位线104的若干部分以经由源/漏区59电耦合数位线104至晶体管69。示范的数位线104包含多晶硅和/或硅化物层。示范的传导插头61包含掺杂的多晶硅。绝缘隔片70(图50)在传导插头61和绝缘层56之间形成。示范的绝缘隔片70包含氮化硅和/或氧化硅，如二氧化硅。
半导体构造100包含电容器80和晶体管69之间的中间结构。氮化物盖106在数位线部分104上方形成。绝缘隔片110在数位线104之间形成并且氮化物盖106位于其一侧以及多晶硅插头102位于其另外一侧。二氧化硅层108在氮化物盖106的上方形成。
遵照法规，本发明已经在语言上或多或少地具体就结构和方法特征进行了描述。然而，将会理解，本发明不限于所示出和描述的特定特征，因为在这里所公开的方法包含实施本发明的优选形式。因此，本发明要求属于依照等同物的原则适当解释的所附权利要求的适当范围的任何形式或修改的权利。

Claims (38)

1.一种晶体管器件，包括：
半导体衬底；
在所述半导体衬底内延伸的栅，在所述栅上方的栅介质，在所述栅的相对侧上的一对源/漏区，以及在所述半导体衬底内的沟道区，所述沟道区的至少一部分限定所述晶体管器件的最下结构；以及
其中所述栅环绕所述半导体衬底的一部分。
2.如权利要求1所述的器件，其中所述栅介质、所述对源/漏区和所述沟道区在所述半导体衬底内。
3.如权利要求1所述的器件，其中所述栅介质整体、所述对源/漏区整体和所述沟道区整体在所述半导体衬底内。
4.如权利要求1所述的器件，其中所述栅围绕所述沟道区的一部分。
5.如权利要求1所述的器件，其中所述沟道区在所述半导体内并且在高度上低于所述对源/漏区。
6.如权利要求1所述的器件，其中所述栅围绕所述沟道区的一部分并且所述栅围绕所述对源/漏区中的一个。
7.如权利要求1所述的器件，其中所述半导体衬底包括单晶硅。
8.如权利要求1所述的器件，还包括结合进DRAM器件的所述晶体管。
9.如权利要求1所述的器件，还包括数据存储元件，所述数据存储元件电耦合至所述晶体管器件从而形成存储单元，所述存储单元在所述半导体衬底上方的面积大约为4F2，其中F表示光刻限定特征的最小特征尺寸。
10.一种晶体管器件，包括：
含有上表面的半导体衬底；
一对源/漏区，其包括所述半导体衬底的部分；
沟道区，其包括在所述半导体衬底内的至少三个侧向间隔部分，并且所述三个部分的每一者相对于所述半导体衬底的上表面垂直延伸；以及
栅部分，其置于所述对源/漏区之间，所述栅环绕所述半导体衬底的一部分，其中所述对源/漏区中的一个实质上垂直延伸且在高度上限定所述晶体管装置的最高结构。
11.如权利要求10所述的器件，其中所述沟道区的所述三个部分中的一个直接在所述对源/漏区中的一个的下面延伸。
12.如权利要求10所述的器件，其中所述沟道区的所述三个部分中的一个直接在所述对源/漏区中的一个的下面延伸，并且其中所述栅在所述半导体衬底内并围绕所述沟道区的所述三个部分的一个。
13.如权利要求10所述的器件，其中所述半导体衬底包括单晶硅。
14.如权利要求10所述的器件，还包括结合进DRAM器件的所述晶体管器件。
15.如权利要求10所述的器件，还包括数据存储元件，所述数据存储元件电耦合至所述源/漏区对中的一个从而形成存储单元，所述存储单元包括所述半导体衬底上方大约4F2的面积，其中F表示光刻限定特征的最小特征尺寸。
16.一种半导体构造，包括：
从半导体衬底的上表面向上延伸的传导柱，所述传导柱包括圆形截面；
在所述半导体衬底内在所述传导柱下面并与所述传导柱电耦合的源/漏区；
晶体管沟道，其在所述源/漏区下面延伸且包括所述半导体衬底的至少一曲线部分；以及
在所述半导体衬底内并邻近所述晶体管沟道的栅，所述栅环绕所述半导体衬底的一部分，其中所述栅围绕所述源/漏区。
17.如权利要求16所述的构造，其中所述传导柱包括外延硅柱。
18.如权利要求16所述的构造，其中所述源/漏区包括漏区。
19.如权利要求16所述的构造，还包括与所述传导柱电耦合的电容器。
20.如权利要求16所述的构造，其中所述构造包括晶体管，并且还包括将所述晶体管结合进存储单元结构，其中所述传导柱将所述晶体管电耦合至电容器。
21.如权利要求16所述的构造，其中所述半导体衬底水平取向并且所述晶体管沟道垂直延伸。
22.如权利要求16所述的构造，其中所述半导体衬底包括单晶硅。
23.如权利要求16所述的构造，还包括：
另一个源/漏区，邻近与所述晶体管沟道相对的所述栅；以及
数据存储元件，电耦合至所述传导柱从而形成存储单元，所述存储单元在所述半导体衬底上方的面积为大约4F2，其中F表示光刻限定特征的最小特征尺寸。
24.一种形成半导体构造的方法，包括：
提供包含一最上表面的半导体衬底；
形成进入所述半导体衬底的开口；
在所述半导体衬底上方在所述开口内形成氧化膜；
在所述氧化膜上方提供传导栅材料并填充所述开口，所述栅环绕所述半导体衬底的一部分；
在所述半导体衬底内形成一对扩散区，其中所述对扩散区中的至少一个在所述开口的所述形成之前形成，且所述对扩散区的所述至少一个从所述最上表面向外延伸；以及
在所述半导体衬底内形成垂直延伸的沟道区。
25.如权利要求24所述的方法，还包括：
形成电容器；以及
将所述电容器电耦合至所述对扩散区中的所述至少一个。
26.如权利要求24所述的方法，其中所述对扩散区的所述至少一个包括从所述半导体衬底的所述最上表面向上延伸的外延柱且还包括：
在所述半导体衬底上方形成电容器；以及
将所述电容器电耦合至所述外延柱。
27.一种垂直晶体管结构，包括：
硅衬底；
在所述硅衬底内限定并且相对于所述硅衬底垂直延伸的沟道区；
在高度上高于所述沟道区的第一源/漏区；
在所述硅衬底内邻近所述沟道区侧向的栅，所述沟道区的至少一部分在高度上低于所述栅的整体，所述栅环绕所述半导体衬底的一部分，；以及
第二源/漏区，其与所述栅邻近；
第三源/漏区，其与所述栅邻近；以及
其中所述栅围绕所述沟道区的另一部分。
28.如权利要求27所述的结构，其中所述硅衬底包括单晶硅。
29.如权利要求27所述的结构，其中所述第一源/漏区包括漏区。
30.如权利要求27所述的结构，其中所述栅围绕所述第一源/漏区。
31.如权利要求27所述的结构，其中所述第一源/漏区在所述硅衬底上方。
32.如权利要求27所述的结构，其中所述第一源/漏区在所述硅衬底内。
33.如权利要求27所述的结构，其中所述硅衬底包括上表面，并且其中所述第一源/漏区包括从所述上表面延伸并在高度上低于所述上表面的一部分，以及包括从所述上表面延伸并在高度上高于所述上表面的另一部分。
34.如权利要求27所述的结构，其中所述第一源/漏区包括从所述硅衬底向上延伸的外延柱。
35.如权利要求27所述的结构，其中所述第一源/漏区包括在所述硅衬底内的扩散区。
36.如权利要求27所述的结构，其中所述第一源/漏区的一部分包括在所述硅衬底内的扩散区，并且所述第一源/漏区的另一部分包括从所述硅衬底向上延伸的外延柱。
37.如权利要求27所述的结构，还包括从所述硅衬底向上延伸并电耦合至所述第一源/漏区的外延柱，以及其中所述外延柱包括用于垂直晶体管的电触点。
38.如权利要求27所述的结构，还包括从所述硅衬底并且直接在所述第一源/漏区上方向上延伸的外延柱，以及所述外延柱包括用于垂直晶体管的电触点。
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US8120101B2 (en) 2012-02-21
US20080142882A1 (en) 2008-06-19
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US20060261393A1 (en) 2006-11-23
KR100918156B1 (ko) 2009-09-17
US7825462B2 (en) 2010-11-02
WO2006028775A3 (en) 2006-04-27
TWI287270B (en) 2007-09-21
CN101057322A (zh) 2007-10-17
US20060043449A1 (en) 2006-03-02
US7501684B2 (en) 2009-03-10
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