CN100583483C - Phase change memory cell and manufacturing method - Google Patents
Phase change memory cell and manufacturing method Download PDFInfo
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- CN100583483C CN100583483C CN200610168985A CN200610168985A CN100583483C CN 100583483 C CN100583483 C CN 100583483C CN 200610168985 A CN200610168985 A CN 200610168985A CN 200610168985 A CN200610168985 A CN 200610168985A CN 100583483 C CN100583483 C CN 100583483C
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Abstract
The invention relates to a phase change memory cell as part of the phase change memory device. The phase change memory cell includes first and second electrodes electrically coupled by a phase change element. At least a section of the phase change element comprises a higher reset transition temperature portion and a lower reset transition temperature portion. The lower reset transition temperature portion comprises a phase change region which can be transitioned, by the passage of electrical current therethrough, from generally crystalline to generally amorphous states at a lower temperature than the higher reset transition temperature portion.
Description
The party of joint study contract
New York IBM, Taiwan Wang Hong Internaional, Inc and technology company of German Infineon (Infineon Technologies A.G.) are the party of joint study contract.
Technical field
The present invention relates to use the high-density memory device and the manufacture method thereof of phase change storage medium, the phase change storage medium then comprises materials such as chalcogenide.
Background technology
The storage medium that turns to the basis with phase transformation is applied in the writable disc sheet widely.These materials include at least two kinds of solid-state phases, comprise as amorphous solid-state phase roughly, and the solid-state phase that is roughly crystalline state.Laser pulse is used for the writable disc sheet, with two kinds of alternate switchings, and reads the optical property of this kind material after phase change.
As these phase change storage mediums of chalcogenide and similar material, can be by applying the electric current that its amplitude is applicable to integrated circuit, and cause that crystalline phase changes.Generally speaking, amorphous its resistance that is characterized as is higher than crystalline state, and this resistance value can measure easily and indicate in order to conduct.This specific character then causes uses programmable resistor material to form the interest of non-volatile memory etc., and this circuit can be used for the arbitrary access read-write.
Be converted to crystalline state from amorphous state and be generally the low current step.Be converted to amorphous state (following denotion is for resetting (reset)) from crystalline state and be generally high electric current step, it comprises that of short duration high current density pulse is to melt or destruction crystalline texture, thereafter this phase-transition material cooling fast, the process that suppresses phase change makes that at least partly phase change structure is maintained in amorphous state.Under the perfect condition, causing that phase-transition material is converted to amorphous reset current amplitude from crystalline state should be low more good more.Desire reduces the required reset current amplitude of resetting, can by lower the phase-transition material size of component in memory and reduce electrode therewith the contact area of phase-transition material realize, therefore can apply less absolute current value and realize higher current density at this phase-transition material element.
A kind of method of this field development is devoted to form small hole on integrated circuit structure, and uses micro-programmable resistor material to fill these small holes.The patent of being devoted to these small holes comprises: the U.S. Patent No. 5,687,112 on November 11st, 1997 bulletin is entitled as " Multibit Single Cell Memory Element Having Tapered Contact ", the invention people is Ovshinky; U.S. Patent No. 5,789,277 on August 4th, 1998 bulletin is entitled as " Method of Making Chalogenide[sic] Memory Device ", the invention people is for Zahorik etc.; U.S. Patent No. 6 in bulletin on November 21st, 2000,150,253, be entitled as " Controllable Ovonic Phase-Change Semiconductor Memory Deviceand Methods of Fabricating the Same ", the invention people is for Doan etc.
When the very undersized device of hope manufacturing and when meeting the required strict technology controlling and process variable of extensive manufacturing storage device, then can have problems.One memory cell structure preferably is provided, and it has small size and low reset current, and the method for making this structure is provided, required strict state-variable when it can meet the large-scale production storage device.
Summary of the invention
The present invention describes a kind of phase change random access storage device (PCRAM) that is applicable to the large scale integrated circuit.
According to one object of the present invention, it provides a kind of phase change memory cell, and this memory cell is the part of a phase-change memory, and this phase change memory cell comprises: first and second electrode; Phase change element, it is first and second electrode electrical connection therewith; At least one part of this phase change element comprises higher replacement inversion temperature part and low replacement inversion temperature part, this low replacement inversion temperature partly places between this higher replacement inversion temperature part, should low replacement inversion temperature part be electrically connected with this first and second electrode; And this low replacement inversion temperature partly comprises phase change region, this phase change region by by electric current to be converted to roughly amorphous inversion temperature from crystalline state roughly, be lower than the inversion temperature of this higher replacement transformation temperature part.
According to another object of the present invention, it provides a kind of phase change memory cell, and this memory cell is the some of phase-change memory, and this phase change memory cell comprises: first and second electrode, and the surface of this two electrode is separated by a gap; Phase change element and is electrically connected with this first and second electrode between this first and second electrode; This phase change element is included as the outside of tubulose and by inside that this outside surrounded, this outside comprises that higher replacement inversion temperature part and this inside comprise low replacement inversion temperature part, and the replacement inversion temperature of this higher replacement inversion temperature part is higher than the replacement inversion temperature of this low replacement inversion temperature part more than 100 ℃ at least; And should low replacement inversion temperature partly comprise phase change region, this phase change region by by electric current to be converted to amorphous inversion temperature from crystalline state, be lower than the inversion temperature of this higher replacement inversion temperature part.
According to another object of the present invention, it provides a kind of in order to make the method for phase change memory cell, this memory cell is the part of phase-change memory, and the method comprises: be electrically connected first and second electrode and phase change element, this phase change element comprises phase-transition material; And, this is electrically connected step higher replacement inversion temperature part and low replacement inversion temperature part is provided, this low replacement inversion temperature partly places between this higher replacement inversion temperature part, this low replacement inversion temperature part is electrically connected with this first and second electrode, this low replacement inversion temperature partly generates phase change region, its can by by electric current between this two electrode and at crystalline state roughly and roughly change between the amorphous state, this phase change region by by electric current to be converted to amorphous inversion temperature from crystalline state, be lower than the inversion temperature of this higher replacement transformation temperature part.
According to another object of the present invention, it provides a kind of in order to make the method for phase change memory cell, this memory cell is the part of phase-change memory, this method comprises: be electrically connected first and second electrode and phase change element, this phase change element is between this first and second electrode and be in contact with it, and this phase change element comprises phase-transition material; Change the replacement inversion temperature of phase-transition material of the tubular outer of this phase change element, generating higher replacement inversion temperature with the tubular outer at this phase change element partly reaches in the tubular inner of this phase change element and generates low replacement inversion temperature part, this low replacement inversion temperature partly comprises phase change region, its can by by electric current between this two electrode and between crystalline state and amorphous state, change; And should the replacement inversion temperature change step and comprise with a material and being implanted in the outside of this phase change element, to increase the replacement inversion temperature of this outside, generate this higher replacement inversion temperature part.
Method of the present invention relates to forming in the memory cell of PCRAM and leads bridge or other phase change devices, and the method can be in order to make the small bridge of leading of other purposes.Nanometer technology device with very small phase change structure uses phase-transition material material in addition, comprises metal, medium, organic material, semiconductor etc.
Below describe structure of the present invention and method in detail.The purpose of description of contents part of the present invention is not to be to limit the present invention.The present invention is limited by claims.All embodiments of the invention, feature, purpose and advantage etc. can be passed through following specification, claims and accompanying drawing and obtain fully to understand.
Description of drawings
Fig. 1 illustrates the embodiment that film is led the bridge novel phase change memory.
Fig. 2 illustrates the current path that film among Fig. 1 is led the bridge novel phase change memory.
The film that Fig. 3 illustrates Fig. 1 is led the phase change active region of bridge novel phase change memory.
Fig. 4 illustrates the film of Fig. 1 and leads the size of bridge novel phase change memory.
Fig. 5 illustrates a pair of novel phase change memory, and it has access circuit under electrode layer, and has bit line on electrode layer.
Fig. 6 is the layout of the structure of Fig. 5.
Fig. 7 is the schematic diagram of storage array, and this storage array comprises novel phase change memory.
Fig. 8 is the calcspar of integrated circuit (IC)-components, and this integrated circuit (IC)-components comprises film resistor phase change storage array and other circuit.
Fig. 9 is the profile of substrate, and this substrate comprises by the formed circuit of FEOL, and makes in a step of the novel phase change memory structure of shop drawings 5.
Figure 10 illustrates the initial step profile of the formation step that forms the electrode layer in Fig. 5 structure.
Figure 11 A and 11B illustrate plane graph and the profile that Figure 10 structure is carried out patterning, and it forms electrode and is stacked in the electrode layer.
Figure 12 is illustrated in the profile that forms the corresponding step that sidewall isolates on the electrode storehouse of Figure 11 B.
Figure 13 is illustrated in the profile that forms the corresponding step of one deck conductor material on the structure of Figure 12.
Figure 14 is illustrated in the profile that grinds conductor material and the corresponding step of sidewall isolation in the structure of Figure 13.
Figure 15 is illustrated in and forms phase-transition material thin layer and the profile of protecting tectal corresponding step on the structure of Figure 14.
Figure 16 A illustrates plane graph and the profile that carries out the corresponding step of patterning at the phase-transition material thin layer of Figure 15 with 16B, comprises forming banded photoresist on phase-transition material.
Figure 17 A illustrates plane graph and the profile that carries out the corresponding step of patterning at the phase-transition material thin layer of Figure 15 with 17B, comprises that the banded photoresistance to Figure 16 A and 16B is etched with the narrower banded photoresistance of formation.
Figure 18 A and 18B illustrate according to the photoresistance pattern of Figure 17 A and 17B and the phase-transition material thin layer are carried out the plane graph and the profile of the phase change list structure after the etching.
Figure 19 A and 19B illustrate the plane graph and the profile of the phase-transition material strip pattern of Figure 18 A and 18B, and it leads bridge in order to form phase-transition material on electrode layer.
Figure 20 A and 20B illustrate the plane graph and the profile of leading bridge according to the phase-transition material of pattern after etching of Figure 19 A and 19B.
The structure (comprising electrode layer and phase change bridge) that Figure 21 is illustrated in Figure 20 A and 20B goes up the profile that forms dielectric layer,
Figure 22 A and 22B are illustrated in and form plane graph and the profile of conductive plug in layer of dielectric material in the structure of Figure 21, and layer of dielectric material contacts to phase-transition material and leads bridge.
Figure 23 is illustrated in the corresponding step profile that forms patterned conductive layer on the structure of Figure 22 A and 22B.
Figure 24-41 illustrates embodiments of the invention, and wherein phase-transition material comprises higher and low transformation temperature part.
Figure 24 shows phase-transition material and is deposited on first and second electrode, and this two electrode is insulated assembly and separates.
Figure 25 illustrates the result of structure behind deposition photoresist mask mask and etching step of Figure 24.
Figure 26 shows the result of the structure of Figure 25 through the mask shearing procedure.
Figure 27 shows the result who plants element at the exposed parts cloth of phase-transition material.
Figure 28 and 29 has removed schematic diagram and profile behind the photoresist mask for phase change memory cell.
Figure 30 shows the alternative cloth planting technology of Figure 27, wherein carries out cloth with the oblique angle and plants, to generate less phase change region.
Figure 31 illustrates the profile of being done along the 31-31 line of Figure 30, illustrates by oblique angle cloth and plants the narrower phase change region that is generated.
Figure 32 is the simplification profile of phase-change memory of the present invention.
Figure 33 illustrates the memory cell access layer of Figure 32.
Figure 34 is illustrated in the result of sediment phase change formed material layer on the memory cell access layer of Figure 33.
Figure 35 is illustrated in the result who forms the offset printing mask on the phase-change material layer of Figure 34.
The phase-transition material that exposes that Figure 36 is illustrated in Figure 35 is etched with the result who generates phase change element.
Figure 37 illustrates the pruning result of the offset printing mask of Figure 36.
Figure 38 is illustrated in the generally tubular outside that phase change element exposes and carries out the result that cloth is planted.
Figure 39 illustrates and removes the offset printing mask and deposit the result of monoxide layer on the upper surface of memory cell access layer and phase change element.
Figure 40 illustrates the result who the structure of Figure 39 is carried out cmp.
Figure 41 is the simplification stereogram of the phase change element of Figure 40.
The main element symbol description
10 memory cell
11 bridge of memory material
12 first electrodes
13 second electrodes
14 insulation assemblies
12a, 13a, 14a upper surface
16 active channels
20 Semiconductor substrate
23,24 polysilicon word lines
25,26,27 n type terminals
28 common source line
29,30 embolism structures
31 electrode layers
32～34 electrode assemblies
35a, the b insulated gate
36,37 film bridge of memory material
38 tungsten plugs
39 substrate assemblies
40 patterned conductive layers
41,42 metal bit lines
45 Y decoder and word line drivers
46 X decoder and sensing amplifiers
The 50-53 access transistor
60 storage arrays
61 column decoders
62 word lines
63 row decoders
64 bit lines
65,67 buses
66 sensing amplifiers and data are read in
69 bias voltages are arranged state machine
71 data input circuits
72 data output circuits
74 other circuit
75 integrated circuits
99 structures
101,102 grooves
103～105 through doped region
106 source electrode lines
107 polysilicons
108 silicide cover layers
109 dielectric layers
110,112,113,114 embolisms
111 polysilicon lines
115,116 through doped region
117,118 word lines
120 film dielectric layers
121 conductive electrode material layers
130～132 electrode storehouses
133,134 sidewalls
140～143 dielectric sidewall
150 electrode material layers
160～162 electrode assemblies
163,164 insulation assemblies
170 thin layers
171 protection cover layers
180 photoresist layers
180a, the banded photoresistance of 180b
190 photoresist layers
190a, the banded photoresistance of 190b
200 film storage material layers
201 protection cover layers
210,211 photoresist layers
210a, 210b, 211a, 211b, 212a, 212b light resistance structure
215 first electrode assemblies
216 second electrode assemblies
217 third electrode assemblies
218 bridge of memory material
220～222 cellular constructions
220a, b, 221a, b, 222a, b cellular construction
225～227 grooves
230 medium packed layers
240～242 embolisms
240a, the b embolism
250 conductive layers
310 phase change memory cells
311 phase change bridge
312 first electrodes
313 second electrodes
314 insulation assemblies
316 phase-transition materials
318 photoresistance masks
320 reduced size masks
322 cloth are planted
324 higher variation temperature sections
326 low transformation temperature parts
328 phase change regions
410 phase-change memories
412 memory cell access layers
414 memory cell layers
416,418 second grids
420,422 first and second embolisms
424 common source line
426 dielectric film layers
428 flat upper surfaces
430 electrode surfaces
432 phase-change material layer
434 offset printing masks
436 phase change elements
440 cloth are planted
442 tubular outer
444 inside (core)
446 oxide skin(coating)s
448 surfaces
450 outer ends
452 bit lines
454 electrode surfaces
456 central areas
Embodiment
To contrast below that Fig. 1-2 3 describes film fuse phase change memory cell of the present invention, its storage array in detail and in order to make the method for these unit.The embodiment of Figure 24-31 is first group of example of phase change memory cell, and it has higher and low replacement transformation temperature part.The embodiment of Figure 32-41 is second group of example of phase change memory cell, and it has higher and low replacement transformation temperature part.
Hereinafter common with reference to specific structure embodiment and method about narration of the present invention.Will be appreciated that it is not in order to the present invention is limited to specific disclosed embodiment and method.This method can be used other features, element, method and embodiment and implement.Similar components in different embodiment can be specified with similar label haply.
Fig. 1 illustrates the basic structure of memory cell 10, and it comprises bridge of memory material 11 on electrode layer, and electrode layer comprises first electrode 12, second electrode 13, and comprises insulation assembly 14 between first electrode 12 and second electrode 13.As shown in the figure, first and second electrode 12,13 has upper surface 12a, 13a respectively.Similarly, insulation assembly 14 also has a upper surface 14a.The upper surface 12a of electrode layer, 13a, 14a has defined the upper surface of substantial planar on the electrode layer of shown embodiment.Bridge of memory material 11 is positioned on the flat upper surfaces of electrode layer, make first electrode with lead between the bridge 11, second electrode 13 with lead contacting between the bridge 11, form via the bottom side of leading bridge 11.
Fig. 2 shows in the memory cell structure, at first electrode 12, lead the current path between the bridge 11 and second electrode 13.Access circuit can utilize different configurations and contact to first electrode 12 and second electrode 13, and then control the operation of this memory cell, make it can be programmed and be set in one of two solid-state phases that this two solid-state phase can be utilized storage medium and reversibly implement will lead bridge 11.For example, utilize chalcogenide phase change storage medium, this memory cell can be set to quite high resistivity states and quite low resistivity states, wherein leading at least one part of bridge in current path is amorphous state, to reach high resistivity state, lead the overwhelming majority of bridge in current path and then be crystalline state, to reach low resistivity state.
Fig. 3 shows the active channel of leading bridge 11, and wherein active channel 16 is brought out the zone that changes for material between at least two solid-state phases.Be understandable that active channel 16 can be very small in shown structure, to reduce in order to bring out the needed current amplitude of phase change.
Fig. 4 shows the significant dimensions of memory cell 10.The length L of active region 20 (x axle) is defined by the thickness of insulation assembly 14 (being called channel media in the drawings) between first electrode 12 and second electrode 13.This length L can be controlled by the width of the insulation assembly 14 among the control store unit embodiment.In representing embodiment, the width of insulation wall 14 can utilize film deposition techniques and form the thin sidewalls dielectric layer on the side of electrode storehouse.Therefore, the passage length L among the embodiment of memory cell is less than 100 nanometers.Passage length L among other embodiment then is 40 nanometers or following.In other embodiments, this passage length is less than 20 nanometers.Be understandable that, passage length even can be much smaller than 20 nanometers, the demand of its visual application-specific realizes as film deposition techniques such as technique for atomic layer deposition and utilize.
Similarly, in memory cell embodiment lead bridge thickness T (y axle) can be very small.Leading the bridge thickness T can be formed on the upper surface of first electrode 12, insulation assembly 14 and second electrode 13 by using film deposition techniques.Therefore, among the memory cell embodiment, leading the bridge thickness T is below 50 nanometers.Among the embodiment of other memory cell, leading bridge thickness is below 20 nanometers.Leading the bridge thickness T in other embodiments is below 10 nanometers.Scrutablely be, lead the bridge thickness T even can utilize as technique for atomic layer deposition etc. and less than 10 nanometers, demand on application-specific is decided, as long as this thickness is enough to make and leads the purpose that bridge is realized its memory element, have at least two solid-state phases and can be by applying curtage between first and second electrode and reversibly bring out even lead bridge.
As shown in Figure 4, it is also very small to lead bridge width W (z axle).In a preferred embodiment, this leads the bridge width W and is less than 100 nanometers.In certain embodiments, leading the bridge width is below 40 nanometers.
The example of memory cell has comprised the phase change storage medium leading bridge 11, comprises chalcogenide materials and other materials.Chalcogenide comprises in the following quaternary element any: oxygen (O), sulphur (S), selenium (Se) and tellurium (Te), the part of VI family on its forming element periodic table.Chalcogenide comprises chalcogen and more electropositive element or combined with radical is got.The chalcogen compound alloy comprises chalcogen compound is combined with other materials such as transition metal etc.The chalcogen compound alloy generally includes the element that is selected from the periodic table of elements the 6th hurdle more than, for example germanium (Ge) and tin (Sn).Usually, more than one compound in the column element under the chalcogen compound alloy comprises: antimony (Sb), gallium (Ga), indium (In) and silver (Ag).Many with phase transformation turn to the basis storage medium in technological document, be described, comprise following alloy: gallium/antimony, indium/antimony, indium/selenium, antimony/tellurium, germanium/tellurium, germanium/antimony/tellurium, indium/antimony/tellurium, gallium/selenium/tellurium, tin/antimony/tellurium, indium/antimony/germanium, silver/indium/antimony/tellurium, germanium/tin/antimony/tellurium, germanium/antimony/selenium/tellurium and tellurium/germanium/antimony/sulphur.In germanium/antimony/tellurium alloy family, can attempt large-scale alloying component.This composition can following feature formula be represented: Te
aGe
bSb
100-(a+b)
A researcher has described the most useful alloy and has been, the average tellurium concentration that is comprised in deposition materials is far below 70%, typically be lower than 60%, and the tellurium content range in general kenel alloy is from minimum 23% to the highest by 58%, and the best is the tellurium content between 48% to 58%.It is about 5% that the concentration of germanium is higher than, and its average range in material generally is lower than 50% from minimum 8% to the highest by 30%.Best, the concentration range of germanium is between 8% to 40%.Remaining main component then is an antimony in this composition.Above-mentioned percentage is atomic percent, and it is 100% for all constituent elements summation.(Ovshinky ' 112 patents, the 10th～11 hurdle) comprises Ge by the specific alloy that another researcher assessed
2Sb
2Te
5, GeSb
2Te
4, and GeSb
4Te
7(Noboru Yamada, " Potential of Ge-Sb-Te Phase-change OpticalDisks for High-Data-Rate Recording ", SPIE v.3109, pp.28-37 (1997)).More generally, transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and above-mentioned mixture or alloy can combine with germanium/antimony/tellurium to form the phase change alloy, and it includes programmable electrical resistance property.The specific examples of spendable storage medium, as described in 11-13 hurdle in Ovshinsky ' 112 patents, its example is listed reference at this.
The phase change alloy can be changed for general amorphous first configuration state and between for second configuration state of general crystalline solid state at material according to its sequence of positions in this element active channel zone.These materials are at least Bistable." amorphous " speech refers to more inordinate relatively structure, and it is than monocrystalline property more out of order, and has detectable feature, as the resistance value higher than crystalline state." crystalline state " speech refers to structure relatively more orderly, and therefore it include detectable feature, for example lower than amorphous state resistance value than amorphous state orderliness more.Typically, phase-transition material can switch to all detectable different conditions between complete crystalline state and the complete amorphous state by electricity.Other are subjected to the change of amorphous state and crystalline state and the material behavior that influences comprises atom order, free electron density and activation energy.This material is changeable to become different solid-state or changeable becoming by two or more solid-state formed mixtures, provides from amorphous state to the grey exponent part between the crystalline state.Electrical property in this material also may change thereupon.
The phase change alloy can switch to another phase from a kind of phase by applying electric pulse.The previous observation point out, short, pulse is by a relatively large margin tended to phase with phase-transition material and changed over and be roughly amorphous state.Long, tend to phase with phase-transition material than the pulse of low amplitude and change over and be roughly crystalline state.Short, the energy in the pulse is enough big by a relatively large margin, therefore is enough to destroy the bond of crystalline texture, and is enough short simultaneously, therefore can prevent that atom is arranged in crystalline state once more.Do not having under the situation of inappropriate experiment, can determine to be specially adapted to the suitable pulsed quantity varied curve that specific phase changes alloy.At the further part of this paper, this phase-transition material should be understood with the GST designate simultaneously, also can use the phase-transition material of other types.Described in this article a kind of material that is applicable among the PCRAM is Ge
2Sb
2Te
5, and be commonly referred to GST.
The present invention contrasts phase-transition material and is described.Yet also can use other storage mediums (being also referred to as programmable material sometimes).In the present invention, storage medium is that its electrical characteristics (as resistance value etc.) can be by applying the material that energy changes; This change can be stepped change, sequential change or the mixing of the two.Other programmable storage mediums that can be used in the other embodiments of the invention comprise doping N
2GST, Ge
xSb
y, or other change the material that decides resistance with different crystalline states; Pr
xCa
yMnO
3, PrSrMnO, ZrO
xOr other utilize electric pulse to change the material of resistance states; Or other use electric pulse to change the material of resistance states; Tetra cyanogen subculture dimethyl benzene quinone (TCNQ, 7,7,8,8-tetracyanoquinodimethane), methane fullerene 66 phenyl C61 methyl butyrate (PCBM, methanofullerene6,6-phenyl C61-butyric acid methyl ester), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCNQ, the TCNQ or any other polymeric material that mix with other materials, it includes the bistable controlled with electric pulse or multistablely decides Resistance states.Other examples of programmable resistance storage medium comprise: GeSbTe, GeSb, NiO, Nb-SrTiO
3, Ag-GeTe, PrCaMnO, ZnO, Nb
2O
5, Cr-SrTiO
3
Information such as manufacturing, element material, use and operation about the phase change random access storage device, see also U.S. Patent application No.11/155,067, the applying date is 2005/6/14, and name is called " Thin Film Fuse Phase Change Ram and Manufacturing Method ".
Fig. 5 shows the structure of PCRAM unit.This element is formed on the Semiconductor substrate 20.As the insulation system of shallow trench spacer medium (STI) (not shown) etc., paired memory cell access transistors row have been isolated.This access transistor act as common source zone and n type terminal 25,27 with n type terminal 26 and act as drain terminal and form among P type substrate 20. Polysilicon word line 23,24 is as the grid of access transistor.Medium packed layer (not shown) is formed on the polysilicon word line.This layer is the conductive structure of patterning, forms as common source line 28 and embolism structure 29,30.Electric conducting material can be tungsten or other materials, and is fit to the combination as the material of embolism and line construction.Common source line contact is to the source region 26, and row in the array and act as common source line.Embolism structure 29,30 contacts respectively to drain terminal 25,26.The upper surface that packed layer (not shown), common source line 28 and embolism structure 29,30 all have general planar is fit to use the substrate as forming electrode layer 31.
Film bridge of memory material 36 (for example GST) is positioned at a side on the electrode layer 31, forms first memory cell across insulative sidewall 35a, and film bridge of memory material 37 (for example GST) are positioned at opposite side on the electrode layer 31, form second memory cell across insulated gate 35b simultaneously.
One medium packed layer (not shown) is positioned at film leads on the bridge 36,37.The medium packed layer comprises silicon dioxide, polyimides, silicon nitride or other medium packing materials.In an embodiment, this packed layer comprises quite good heat and electrical insulator, provides to lead good heat of bridge and electric insulating effect.Tungsten plug 38 contacts to electrode assemblie 33.Include the patterned conductive layer 40 of metal or other electric conducting materials (being included in the bit line in the array structure), be positioned on the medium packed layer, and contact to embolism 38 and lead the access of the memory cell of bridge 36 and 37 for corresponding to film to set up.
Fig. 6 is presented at the structure on the Semiconductor substrate 20 of Fig. 5 in the mode of layout.Therefore, the arrangement of word line 23,24 is parallel to common source line 28 in fact, the common source line in the memory cell array and arranging.Embolism 29,30 contacts the terminal of the access transistor to the Semiconductor substrate and the bottom side of electrode assemblie 32,34 respectively.Film bridge of memory material 36,37 is positioned at electrode assemblie 32,33, and 34 and insulated gate 35a, on the 35b, insulated gate 35a, 35b spaced electrodes assembly.Embolism 38 contact is to leading the electrode assemblie 33 between bridge 35 and 37 and the bottom side of the metal bit line under patterned conductive layer 40 41 (being transparent) in Fig. 6.Metal bit line 42 (nontransparent) also is illustrated among Fig. 6, to emphasize the array layout of this structure.
In operation, correspond to the access of the memory cell of leading bridge 36, control signal to word line 23 and realize that word line 23 is connected to film with common source line 28 via terminal 25, embolism 29 and electrode assemblie 32 and leads bridge 36 by applying.Electrode assemblie 33 is connected to the bit lines in patterned conductive layer 40 via contact embolism 38.Similarly, correspond to the access of the memory cell of leading bridge 37, control signal to word line 24 and realize by applying.
Scrutable is can use multiple different materials in the structure of Fig. 5 and 6.For example, can use copper metallization.The metallization of other types such as aluminium, titanium nitride and tungstenic material etc. also can be used.Simultaneously, also can use as non-metallic conducting materials such as polysilicon through mixing.Employed electrode material in described embodiment is preferably titanium nitride or tantalum nitride.Perhaps, this electrode can be TiAlN or aluminium nitride tantalum, maybe can comprise the element that is selected from more than in following group: titanium (Ti), tungsten (W), molybdenum (Mo), aluminium (Al), tantalum (Ta), copper (Cu), platinum (Pt), iridium (Ir), lanthanum (La), nickel (Ni) and ruthenium (Ru) and by alloy that above-mentioned element constituted.Insulated gate 35a between electrode, 35b can be silicon dioxide, silicon oxynitride, silicon nitride, aluminium oxide or other medium with low dielectric constant.Perhaps, insulating barrier can comprise and is selected from following group element more than one between electrode: silicon, aluminium, fluorine, nitrogen, oxygen and carbon.
Fig. 7 illustrates the schematic diagram of storage array, the description that it can be done with reference to figure 5 and 6 and implementing.Therefore, the label among Fig. 7 corresponds to the label in Fig. 5 and 6.Scrutable is that the array structure shown in Fig. 7 can utilize other cellular constructions and implement.In the explanation of Fig. 7, common source line 28, word line 23, with word line 24, be parallel to Y-axis haply.Bit line 41 and 42 is parallel to X-axis haply.Therefore, Y decoder and word line driver in square 45 are connected to word line 23,24.X decoder in square 46 and one group of sensing amplifier then are connected to bit line 41,42.Common source line 28 is connected to access transistor 50,51,52,53 source terminal.The grid of access transistor 50 is connected to word line 23.The grid of access transistor 51 is connected to word line 24.The grid of access transistor 52 is connected to word line 23.The grid of access transistor 53 is connected to word line 24.The drain electrode of access transistor 50 is connected to electrode assemblie 32 and leads bridge 35 with connection, leads 35 on bridge and then is connected to electrode assemblie 34.Similarly, the drain electrode of access transistor 51 is connected to electrode assemblie 33 and leads bridge 36 with connection, leads 36 on bridge and then is connected to electrode assemblie 34.Electrode assemblie 34 is connected to bit line 41.Convenient for diagram, electrode assemblie 34 is positioned at diverse location with bit line 41.Be understandable that in other embodiments, different memory cell are led bridge can use different electrode assemblies.Access transistor 52 and 53 also is connected to corresponding memory cell on bit line 42.As seen, common source line 28 is shared by two array storage units institute among the figure, and row are wherein arranged along Y-axis.Similarly, electrode assemblie 34 is shared by two memory cell of delegation in array institute, and the row in array then is to arrange along X-axis.
Fig. 8 is the simplification calcspar according to the integrated circuit of the embodiment of the invention.Integrated circuit 75 comprises storage array 60, and it utilizes the film fuse phase change memory cell and builds on the Semiconductor substrate.Row decoder 61 is connected to many word lines 62, and each row in the storage array 60 and arranging.Column decoder 63 is connected to multiple bit lines 64, these bit lines in the storage array 60 each row and arrange, and read and programming data in order to the thin film phase change memory cell from array 60.Address is supplied to column decoder 63 and row decoder 61 on bus 65.Sensing amplifier in the square 66 and data input structure are connected to column decoder 63 via bus 67.Address provides to column decoder 63 and row decoder 61 from bus 65.Sensing amplifier and data in square 66 are read in circuit, are connected to column decoder 63 via data/address bus 67.Data are from the input/output end port of integrated circuit 75 or from other inside or the external data sources of integrated circuit 75, and the data input structure to square 66 is provided via Data In-Line road 71.In described embodiment, this integrated circuit comprises other circuit 74, is supported and the integration module of SoC function can be provided as general processor or proprietary application circuit or with film insurance phase change memory cell array.The sensing amplifier of data from square 66 be via DOL Data Output Line road 72, and be sent to the input/output end port of integrated circuit 75, or be sent to integrated circuit 75 inner or other outside data purposes.
Use bias voltage to arrange the controller of state machine 69 in the present embodiment, the control bias voltage is arranged the application of service voltage 68, for example reads, programmes, wipes, erase-verifying and programming affirmation voltage etc.This controller can use known dedicated logic circuit.In alternate embodiment, this controller comprises general processor, and it can be applicable in the same integrated circuit, and this integrated circuit is carried out computer program and controlled the operation of this element.In another embodiment, this controller has used the combination of specific purpose logical circuit and general processor.
Fig. 9 is illustrated in the structure 99 after the FEOL, forms the standard CMOS element in the illustrated embodiment, and it corresponds to word line, source electrode line and access transistor in the array shown in Figure 7.In Fig. 9, source electrode line 106 cover in the Semiconductor substrate through doped region 103, wherein correspond to the source terminal of second access transistor on right side among first access transistor in left side among the figure and the figure through doped region 103.In this embodiment, source electrode line 106 extends to the upper surface of structure 99.In other embodiments, this source electrode line also not exclusively extends to the surface.Through the drain electrode of first access transistor so far of doped region 104 correspondences.Include the word line of polysilicon 107 and silicide cover layer 108, as the grid of this first access transistor.Dielectric layer 109 is positioned on this polysilicon 107 and the silicide cover layer 108.Embolism 110 contacts so far through doped region 104, and the conductive path surface of structure 99 so far is provided, and is connected to the memory cell electrode in the aftermentioned mode.Include the grid of the word line of polysilicon lines 111 and silicide cover layer (not indicating) as this second access transistor.Embolism 112 contact is to through doped region 105 and the upper surface of conductive path to structure 99 is provided, and is connected to the memory cell electrode in the aftermentioned mode.Isolating trenches 101,102 with this link to embolism 110 and 112 double transistor structure, separate with adjacent double transistor structure.In the left side of figure, illustrate through doped region 115, word line polysilicon 117 and embolism 114.On the right side of figure, illustrate through doped region 116, word line polysilicon 118 and embolism 113.Structure 99 in Fig. 9 provides in order to form the substrate of memory cell device, comprises first and second electrode and bridge of memory material, the following detailed description in detail.
Figure 10 shows the next step of this technology, comprising silicon nitride being arranged or as the film dielectric layer 120 of other materials such as silicon dioxide, silicon oxynitride, aluminium oxide, being formed on the surface of structure 99.Then, the conductive electrode material layer 121 as titanium nitride (TiN) or the electric conducting material that is fit to as titanium nitride etc. (for example tantalum nitride, aluminium alloy, copper alloy, polysilicon etc. through mixing) is formed on the dielectric layer 120.
Figure 11 A and 11B show the next step of this technology, wherein conductive electrode layer 121 and dielectric layer 120 patterned with definition electrode storehouse 130,131,132 on the surface of structure 99 (131a in Figure 11 A, 132a, 133a).In one embodiment, the electrode storehouse is defined by mask offset printing step, and this step has produced patterned light blockage layer, then carries out known dimensional measurement and determining step, and then etching titanium nitride and silicon nitride and in order to the structure of cambium layer 121 and 120.This storehouse has sidewall 133 and 134.
Figure 12 illustrates the next step of this technology, wherein dielectric side walls 140,141,142,143 earlier by the conformal thin film dielectrics layer (not shown) of the sidewall that forms storehouse and storehouse therewith in storehouse 130, on 131,132 the sidewall, then anisotropically this thin film dielectrics layer of etching so that it is removed between the storehouse and the zone on storehouse surface, and residual being formed on the sidewall.In this implementation of processes example, comprise silicon nitride or other dielectric materials, for example silicon dioxide, silicon oxynitride, aluminium oxide etc. in order to the material that forms sidewall 140,141,142,143.
Figure 13 shows the next step of this technology, and wherein second electrode material layer 150 is formed at storehouse 130,131,132 and sidewall 140,141,142,143 on.This electrode material layer 150 has comprised titanium nitride or other suitable electric conducting materials, for example tantalum nitride, aluminium alloy, copper alloy, the polysilicon through mixing etc.
Figure 14 shows the next step of this technology, and wherein second electrode material layer 150, sidewall 140,141,142,143 and storehouse 130,131,132 are subjected to etching and complanation, to define electrode layer on the substrate that structure 99 is provided.The embodiment of grinding technics comprises chemical mechanical milling tech, then carries out brush cleaning and liquid or gas cleaning procedure, and this is well known in the art.Electrode layer has comprised electrode assemblie 160,161,162, and the insulation assembly between electrode assemblie 163,164.Electrode layer in described embodiment has smooth in fact upper surface.In this embodiment, the partial structure of insulation assembly 163,164 also extends under the electrode assemblie 161, and electrode assemblie 161 and source electrode line are isolated.Can use different materials in electrode assemblie and insulation assembly in other illustration structures.
Figure 15 illustrates the next step of this technology, and wherein thin film phase change storage material layer 170 is formed on the substantial planar surface of electrode layer.This storage medium utilizes out-of-alignment sputter to carry out under about 250 ℃.When employed phase change storage medium is Ge
2Sb
2Te
5The time, the film thickness that is generated is about below 60 nanometers.Embodiment involves and whole wafer is sputtered to thickness is about 40 nanometers on its flat surfaces.In certain embodiments, the thickness of thin layer 170 is less than 100 nanometers, and more preferably is below 40 nanometers.In the embodiment of storage device, the thickness of thin layer 170 is less than 20 nanometers, for example 10 nanometers.After forming thin layer 170, form protection cover layer 171.This protection cover layer is included in silicon dioxide or other dielectric materials of formed low temperature depositing on the thin layer 170.This protection cover layer 171 is preferably good electricity and heat insulator, and protects storage medium can not expose in subsequent step, and for example the photoresistance strip step may injure this storage medium.This technology involves and forms the low-temperature substrate medium, utilizes to be lower than 200 ℃ technology as temperature and to form for example silicon nitride layer or silicon dioxide layer.One of technology that is fit to applies silicon dioxide for plasma reinforced chemical vapour deposition (PECVD).Form after this protective coating 171, can utilize as high density plasma chemical vapor deposition method high temperature technologies such as (HDPCVD), and apply the medium packed layer on storage medium.
Figure 16 A and 16B illustrate the next step of this technology, wherein form photoresist layer 180 and patterning in the mask lithography process, and to define banded photoresistance 180a, 180b is on thin layer 170 and protection cover layer 171.Shown in Figure 16 A, insulation assembly 163,164 exposes to banded photoresistance 180a, between the 180b.According to employed lithography process, this banded photoresistance is thin more good more.For example, the width of this banded photoresistance equals the minimum feature size F of employed lithography process, and wherein in current mask lithography process, the minimum feature size of technology can be the order of magnitude of 0.2 micron, 0.14 micron or 0.09 micron.Apparently, this implementation of processes example can reach narrower minimum feature size along with improving of lithography process.
Figure 17 A and 17B illustrate the next step of this technology, the banded photoresistance 180a of Figure 16 A wherein, and 180b is through pruning, to form narrower banded photoresistance 190a, 190b.Shown in Figure 17 B, the thickness of the photoresistance 190 through pruning is also less than the thickness of the photoresist layer among Figure 16 B 180.In one embodiment, this banded photoresistance is pruned with isotropic etching, and it has used technologies such as reactive ion etching.This etch process is trimmed to littler live width with banded photoresistance.At narrower banded photoresistance 190a, among the embodiment of 190b, its width is less than 100 nanometers.At narrower banded photoresistance 190a, among other embodiment of 190b, its width is below 40 nanometers.Photoresistance is pruned and to be utilized oxygen plasma and etching photoresistance isotropically, and then in the lithography process of 0.09 micron (90 nanometer) minimum feature size, its width and thickness is trimmed to about 40 nanometers.In alternate embodiment, the silicon nitride of hard mask layer such as one deck low temperature depositing or silicon dioxide etc. can place the bottom of photoresistance pattern, to avoid storage medium being caused the etching injury when the photoresistance divesting technology.
Figure 18 A and 18B show the next step of this technology, shaped like narrow photoresistance 190a wherein, and 190b is used as etching mask; simultaneously carry out the offset printing etching at film storage material layer 200; to define banded storage medium 200a, no matter whether 200b have protective coating 201.As shown in the figure, banded storage medium 200a, 200b extend across insulation assembly 163,164 and.In this implementation of processes example, storage medium comprises the GST chalcogenide materials, and utilizes as chloride or reactive fluorochemical ion etching and carry out etching.
Figure 19 A and 19B illustrate the next step of this technology, wherein form another photoresist layer 210,211,212 and patterning, with definition light resistance structure 210a, 210b, 211a, 211b, 212a, 212b.This element structure corresponds to paired memory cell, and is as described below.This element structure is than banded storage medium 200a, and 200b is wide, because its width equals the width that employed lithography process (for example light shield lithography process) can reach, and not through pruning.Therefore, width in certain embodiments equals the minimum feature size F in order to the lithography process that forms this layer.
Figure 20 A and 20B illustrate the next step of this technology, light resistance structure 210a wherein, 210b, 211a, 211b, 212a, the left etching mask of 212b, by etched trench 225,226 for the spacer medium structure of structure 99 and be etched between each row unit perpendicular to the groove 227 of word line, and definition unit structure 220a, 220b, 221a, 221b, 222a, 222b (is 220 in Figure 20 B, 221,222).This element structure 220a comprises first electrode assemblie 215, second electrode assemblie 216 and third electrode assembly 217.Insulation assembly 163 is separated first electrode assemblie 215 and second electrode assemblie 216.Insulation assembly 164 is separated first electrode assemblie 215 and third electrode assembly 217.Bridge of memory material 218 is positioned at electrode assemblie 215,216,217 and insulation assembly 163,164 on, on structure 220, to set up two memory cell.
Figure 21 shows the next step of this technology, and the medium packed layer 230 that wherein has a flat upper surfaces is formed on the electrode structure and inserts groove and irrigation canals and ditches between electrode structure.In this implementation of processes example, packed layer 230 utilizes high density plasma chemical vapor deposition (HDPCVD) to deposit, then carry out cmp and forms afterwards with cleaning.The medium packed layer can comprise silicon dioxide, silicon nitride and other insulating material, preferably has good heat and electrical insulation property.
In certain embodiments, outside the medium packed layer or replace the medium packed layer, and provide for the thermal insulation structure of leading bridge.In an embodiment, before applying the medium packed layer, this thermal insulation structure is by providing the thermal insulation cover layer leading on the bridge (218), and it is covers electrode layer optionally.The representative materials of heat insulator layer comprises the material that following element combinations forms: silicon, carbon, oxygen, fluorine and hydrogen.Be suitable as the heat insulator of thermal insulation cap rock, comprise silicon dioxide, hydrogen-oxygen carborundum, polyimides, polyamide and fluorocarbon polymer.Other materials that are suitable in the heat insulation separator can comprise fluorinated silicon dioxide, siloxanes (silsesquioxane), poly-inferior aromatic ether (polyarylene ether), Parylene (parylene), fluoropolymer, fluorine-containing amorphous carbon, diamond class carbon, porous silica for example.In other embodiments, thermal insulation structure has comprised the cavity of filling with gas in the medium packed layer, and the medium packed layer is formed at leads on the bridge 218 so that insulation effect to be provided.Single or multiple lift all can provide heat and electric insulating effect.
Figure 22 A and 22B illustrate the next step of this technology, and wherein the through hole (not shown) carries out etching in packed layer 230, arrives electrode material by storage medium and packed layer.This via etch process can be utilized single anisotropic etching process and etching packed layer and storage material layer perhaps use two-stage technology, earlier etching packed layer, the etching storage material layer with second etch chemistries again with first etch chemistries.After through hole forms, insert through hole, contact the embolism 240 (240a among Figure 22 A of first electrode assemblie (for example assembly 215) to the electrode structure with formation with tungsten metal or other electric conducting materials, 240b), 241,242, to be electrically connected with circuit on the electrode layer.In this implementation of processes example, as substrate, so the field is known, inserts with tungsten metal or other suitable electric conducting materials again with diffusion barrier layer and/or adhesion layer for through hole.This structure is then carried out planarization with cmp, and carries out cleaning.At last, apply clean etch process, to form clean structure.
Figure 23 shows the next step of this technology, wherein forms patterned conductive layer 250 and contacts embolism to the packed layer, and the required bit line of memory element and other conductors are provided, and produces the structure shown in Fig. 5.In this implementation of processes example, use copper alloy to inlay metallization process, wherein deposit fluorine silex glass (FSG) on exposed surface and form patterned conductive layer, then form default photoresistance pattern.Then implement to be etched with to remove the fluorine silex glass that exposes, then deposition substrate and Seed Layer are in this pattern.Then implementing copper electroplates to fill this pattern.After plating, carry out annealing steps, and then carry out grinding technics.Other embodiment can use Solder for Al-Cu Joint Welding technology, or other known metallization process.
Unit described herein comprises two hearth electrodes and medium therebetween, and is positioned on the electrode, leads bridge across the phase-transition material of medium.This hearth electrode and medium are formed in the electrode layer on FEOL CMOS logical construction or other functional circuit structures, provide and can support built-in memory bank and the functional circuit structure on single-chip easily, and this wafer can be for example SoC element.
Figure 24-31 shows the phase change memory cell embodiment of manufacturing of the present invention.Figure 24 shows first and second electrode 312,313, and it is isolated by insulation assembly 314.Phase-transition material 316 is deposited on electrode 312,313 and the insulation assembly 314.Figure 25 show deposition photoresistance mask 318 on the phase-transition material 316, the then result after removing not masked 318 phase-transition materials that covered 316, remove step and typically use suitable etch process to carry out.This step will generate phase change element, and especially phase change bridge 311.Afterwards, photoresistance mask 318 is pruned to generate the reduced size mask 320 among Figure 26.The width of reduced size mask 320 is much smaller than the minimum offset printing characteristic size in order to generation mask 318.Shearing procedure is typically pruned technology by the photoresistance oxygen plasma and is carried out, but also can use other technologies.Reduced size mask 320 roughly places the central authorities of the length of phase change bridge 311, exposes will lead bridge 311, plants technology for the cloth of follow-up Figure 27.
Cloth is planted the constituent that step 322 (for example ion step) can be used single-element or a plurality of elements, and increase phase-transition material 316 when changing when (when the temperature of phase-transition material 316 when amorphous state roughly is changed to crystalline state roughly) and replacement (when phase-transition material 316 when crystalline state roughly is changed to amorphous state roughly) transformation temperature.These elements comprise carbon, silicon, nitrogen and aluminium.Removing of mask 318 can produce phase change memory cell 310, and it comprises the phase change bridge 311 of Figure 28 and 29 figure.Phase change bridge 311 has comprised higher variation temperature section 324 in the both sides of low transformation temperature part 326.In this embodiment, cloth is planted in order to improve the transformation temperature part of phase change bridge 311.In one embodiment, when higher variation temperature section 324 for amorphous state roughly and low transformation temperature part 326 during for crystalline state roughly, the transformation temperature of higher variation temperature section 324 typically is higher than at least than 100 ℃ of the transformation temperatures that hangs down transformation temperature part 326.Along with electric current passes through first and second electrode 312,313, plant before phase-transition material part 324 can carry out phase change at the cloth of phase change region 328 both sides, be positioned at the phase change region 328 of the part 326 on the insulation assembly 314, can and roughly switch between the amorphous state at crystalline state roughly.In certain embodiments, cloth is planted can be in order to reducing the transformation temperature of part 326, but not in order to improve its transformation temperature.
Figure 30 and 31 illustrates wide-angle cloth and plants 330, compares with the phase change region 328 of Figure 29 figure, and it generates narrower phase change region 328.This kind result helps further current concentration in phase change region 328, to reduce needed electric current and energy when generating desirable roughly crystalline state to amorphous phase change roughly.
The advantage of the invention described above in Figure 24-31 is, by placing between the higher variation temperature section 324 and separating phase transformation zone 328 than low transformation temperature part 326, can produce bigger thermal insulation effect to phase change region 328, with so that reduce reset current and electric energy.
Another aspect of the present invention relates to when higher and low transformation temperature part 324,326 and is crystalline state roughly or the thermal conductivity during amorphous state roughly.Preferably, when the two was roughly amorphous state, the thermal conductivity of higher variation temperature section 324 was less than the thermal conductivity of (more preferably at least 50% less than) low transformation temperature part 326.Similarly, when the two was roughly crystalline state, the thermal conductivity of higher variation temperature section 324 was less than the thermal conductivity of (more preferably at least 50% less than) low transformation temperature part 326.These factors help further phase change region 328 thermal insulations with part 326.Suitable cloth is planted element and is comprised nitrogen, oxygen and silicon.
Another aspect of the present invention relates to resistivity higher and low transformation temperature part 324,326.Preferably, when the two was roughly amorphous state, the resistivity of higher variation temperature section 324 was greater than the resistivity of (more preferably at least 50% greater than) low transformation temperature part 326.Similarly, when the two was roughly crystalline state, the resistivity of higher variation temperature section 324 was greater than the resistivity of (more preferably at least 50% greater than) low transformation temperature part 326.In addition, when the two was roughly amorphous state, the resistance value of higher variation temperature section 324 was greater than the resistance value of (more preferably at least 50% greater than) low transformation temperature part 326.Similarly, when the two was roughly crystalline state, the resistance value of higher variation temperature section 324 was greater than the resistance value of (more preferably at least 50% greater than) low transformation temperature part 326.These aspects help the phase change region 328 of current concentration in low transformation temperature part 326 is beneficial to reduce transformation temperature and energy, especially when resetting.
Preferably, higher variation temperature section 324 is for amorphous state roughly and be maintained at roughly amorphous state because material when amorphous state roughly thermal conductivity and conductivity typically less than thermal conductivity and conductivity when the crystalline state roughly.
Figure 32-41 has described the alternate embodiment of Figure 24-31 embodiment, and wherein phase change element is between electrode surface.The phase change element of this embodiment has the outside of generally tubular, round inside or core.Outside inversion temperature typically is higher than inside.The outside helps the internal heat insulation is beneficial in roughly amorphous state and the roughly phase change between the crystalline state.
Figure 32 is the simplification profile of the novel phase change memory 410 of manufacturing of the present invention.Element 410 comprises the memory cell access layer 412 that is formed on the substrate (not shown) and is formed at memory cell layers 414 on the level of access 412.Level of access 412 typically comprises access transistor; Also can use the access device of other types.Level of access 412 comprises first and second polysilicon word line, and it is as second grid 416,418, first and second embolism 420,422 and a common source polar curve 424, and above-mentioned each parts all are positioned within the dielectric film layer 426.
In Figure 36, the part of not masked 434 protections is removed in the layer 432, stays roughly columned phase change element 436 in the present embodiment.Figure 37 show roughly cylindric (present embodiment) through pruning offset printing mask 438, being created on the generation result on the phase change element 436.Through the width or the diameter of trim mask 438, much smaller than minimum offset printing characteristic size in order to the technology that generates mask 434.Prune typically and carried out, but also can use other technologies with photoresistance oxygen plasma pruning technology.Afterwards, element that the structure utilization of Figure 37 is suitable or material carry out cloth and plant 440, and that is for example discussed when Figure 27 is such.This cloth is planted generation phase change element 436, and it has the outside 442 of generally tubular, around inside or core 444.Cloth is planted step makes outside 442 replacement transformation temperature be higher than inner 444.Outside 442 replacement transformation temperature is preferably at least greater than 100 ℃ of inner 444 replacement transformation temperatures.
Offset printing mask 438 through pruning is removed, and then deposition is as the oxide of silicon dioxide, to generate oxide skin(coating) 446, as shown in figure 39.Then carry out cmp at the structure of Figure 39, to generate as the structure of Figure 40 and generate surface 448, surperficial 448 comprise the outer end 450 of phase change element 436.Afterwards, metal bit line 452 is formed on the surface 448, and bit line 452 contacts outer end 450 to phase change element 436 as second electrode with electrode surface 454.
Figure 41 is a sketch, and roughly columned phase change element 436 is shown, and it comprises the outside 442 and inner 444 of generally tubular.The section of the generally tubular outside 442 of phase change element 436 can be roughly columned section, as shown in the figure; Yet other section shapes of generally tubular outside 442 also are possible, comprise rule or irregular polygon, with have the shape of curve and/or linear section.
Outside 442 heat insulators as inside 444 are to help the variation of inside 444.Inner 444 by being changed to roughly amorphous state by electric current from crystalline state roughly, and its inversion temperature is lower than outside 442 inversion temperature.Inner 444 have central area 456, and its inside along inner 444 is provided with.Inner 444 carry out phase change before, central area 456 can be earlier be changed to roughly amorphous state from crystalline state roughly, because inner end points is cooled off by adjacent electrode surface 430,454 formed cooling effects.Therefore, the central area may be in inner 444 in use, uniquely can be effectively be changed to roughly amorphous part from crystalline state roughly, and therefore as inner 444 phase change region.Yet in other embodiments, inner 444 whole or major part can be converted to roughly amorphous state from crystalline state roughly, make inside 444 all or all can be used as phase change region.
In the present invention describes employed vocabulary as on, under, top, the end etc., only be used to make the reader to understand the present invention more, but not in order to restriction the present invention.
Though the present invention is described with reference to preferred embodiment, will be appreciated that the present invention is not limited to the content of its detailed description.Substitute mode and alter mode advise in previous description, and other substitute modes and alter mode will can be expected for those skilled in the art.Particularly, according to structure of the present invention and method, all have be same as in fact assembly of the present invention in conjunction with and reach identical result in fact with the present invention, do not break away from spiritual category of the present invention.Therefore, all these substitute modes and alter mode are intended to drop on the present invention among the category that appending claims and equivalent thereof defined.
Any patent application of mentioning in preamble and open text are all classified the application's reference as.
Claims (24)
1. phase change memory cell, this memory cell is the part of phase-change memory, this phase change memory cell comprises:
First and second electrode;
Phase change element, first and second electrode of itself and this is electrically connected;
At least one part of this phase change element comprises higher replacement inversion temperature part and low replacement inversion temperature part, this low replacement inversion temperature partly places between this higher replacement inversion temperature part, should low replacement inversion temperature part be electrically connected with this first and second electrode; And
This low replacement inversion temperature partly comprises phase change region, this phase change region by by electric current to be converted to amorphous inversion temperature from crystalline state, be lower than the inversion temperature of this higher replacement transformation temperature part.
2. phase change memory cell as claimed in claim 1, wherein the replacement inversion temperature of this higher replacement inversion temperature part is higher than at least 100 ℃ of this low replacement inversion temperature replacement inversion temperatures partly.
3. phase change memory cell as claimed in claim 1, wherein:
The surface of this first and second electrode is separated by a gap; And
This phase change element places between this first and second electrode.
4. phase change memory cell as claimed in claim 1, wherein this phase change element is included as the outside of tubulose and by the inside that this outside surrounded, this outside comprises that higher replacement inversion temperature part and this inside comprise low replacement inversion temperature part.
5. phase change memory cell as claimed in claim 1, wherein when this higher replacement inversion temperature part partly was crystalline state with this low replacement inversion temperature, the thermal conductivity of this higher replacement inversion temperature part was less than the thermal conductivity of this low replacement inversion temperature part.
6. phase change memory cell as claimed in claim 1, wherein when this higher replacement inversion temperature part partly was crystalline state with this low replacement inversion temperature, the thermal conductivity of this higher replacement inversion temperature part thermal conductivity than this low replacement inversion temperature part at least was little by 50%.
7. phase change memory cell as claimed in claim 1, wherein when this higher replacement inversion temperature part partly was crystalline state with this low replacement inversion temperature, the resistivity of this higher replacement inversion temperature part was greater than the resistivity of this low replacement inversion temperature part.
8. phase change memory cell as claimed in claim 1, wherein when this higher replacement inversion temperature part partly was crystalline state with this low replacement inversion temperature, the resistivity of this higher replacement inversion temperature part resistivity than this low replacement inversion temperature part at least was big by 50%.
9. phase change memory cell as claimed in claim 1, wherein when this higher replacement inversion temperature part partly was crystalline state with this low replacement inversion temperature, the resistance value of this higher replacement inversion temperature part was greater than the resistance value of this low replacement inversion temperature part.
10. phase change memory cell as claimed in claim 1, wherein when this higher replacement inversion temperature part partly was crystalline state with this low replacement inversion temperature, the resistance value of this higher replacement inversion temperature part resistance value than this low replacement inversion temperature part at least was big by 50%.
11. phase change memory cell as claimed in claim 1, wherein this phase change element comprises first and second higher replacement inversion temperature part, and above-mentioned two parts are positioned at the not homonymy of this low replacement inversion temperature part.
12. phase change memory cell as claimed in claim 1, but wherein in this higher replacement inversion temperature part cloth be implanted with cloth and plant element, but should cloth plant element be not present in should low replacement inversion temperature partly in.
13. phase change memory cell as claimed in claim 12 comprises in following at least a but wherein should cloth plant element: carbon, silicon, oxygen, nitrogen and aluminium.
14. phase change memory cell as claimed in claim 1, wherein this phase change element comprises the composition that is selected from following group of material more than two kinds: germanium, antimony, tellurium, selenium, indium, titanium, gallium, bismuth, tin, copper, palladium, lead, silver, sulphur and gold.
15. phase change memory cell as claimed in claim 1, wherein this first and second electrode comprises element and the alloy thereof that is selected from following group: titanium, tungsten, molybdenum, aluminium, tantalum, copper, platinum, iridium, lanthanum, nickel and ruthenium.
16. a phase change memory cell, this memory cell are the some of phase-change memory, this phase change memory cell comprises:
First and second electrode, the surface of this two electrode is separated by a gap;
Phase change element and is electrically connected with this first and second electrode between this first and second electrode;
This phase change element is included as the outside of tubulose and by inside that this outside surrounded, this outside comprises that higher replacement inversion temperature part and this inside comprise low replacement inversion temperature part, and the replacement inversion temperature of this higher replacement inversion temperature part is higher than the replacement inversion temperature of this low replacement inversion temperature part more than 100 ℃ at least; And
This low replacement inversion temperature partly comprises phase change region, this phase change region by by electric current to be converted to amorphous inversion temperature from crystalline state, be lower than the inversion temperature of this higher replacement inversion temperature part.
17. the method in order to the manufacturing phase change memory cell, this memory cell is the part of phase-change memory, and this method comprises:
Be electrically connected first and second electrode and phase change element, this phase change element comprises phase-transition material; And
This electrical connection step provides higher replacement inversion temperature part and low replacement inversion temperature part, this low replacement inversion temperature partly places between this higher replacement inversion temperature part, this low replacement inversion temperature part is electrically connected with this first and second electrode, this low replacement inversion temperature partly generates phase change region, its can by by electric current between this two electrode and between crystalline state and amorphous state, change, this phase change region by by electric current to be converted to amorphous inversion temperature from crystalline state, be lower than the inversion temperature of this higher replacement transformation temperature part.
18. method as claimed in claim 17, wherein this electrical connection step comprises and forms this phase change element between this first and second electrode and be in contact with it.
19. method as claimed in claim 17, wherein this replacement inversion temperature higher and phase-transition material that partly provides step to comprise the tubular outer that changes this phase change element than low replacement inversion temperature.
20. method as claimed in claim 17, wherein this higher and low replacement inversion temperature replacement inversion temperature of partly providing step to comprise this tubular outer that increases this phase change element.
21. method as claimed in claim 17, this higher and low replacement inversion temperature replacement inversion temperature of partly providing step to comprise at least one part phase-transition material that changes this phase change element wherein is to generate higher replacement inversion temperature part and this hangs down replacement inversion temperature part.
22. method as claimed in claim 21, wherein this higher and low replacement inversion temperature partly provides in the some that step is included in this phase change element cloth to plant material, to change the replacement inversion temperature of this part.
23. method as claimed in claim 21, wherein this higher and low replacement inversion temperature partly provides in the some that step is included in this phase change element cloth to plant material, to increase the replacement inversion temperature of this part.
24. the method in order to the manufacturing phase change memory cell, this memory cell is the part of phase-change memory, and this method comprises:
Be electrically connected first and second electrode and phase change element, this phase change element is between this first and second electrode and be in contact with it, and this phase change element comprises phase-transition material;
Change the replacement inversion temperature of phase-transition material of the tubular outer of this phase change element, generating higher replacement inversion temperature with the tubular outer at this phase change element partly reaches in the tubular inner of this phase change element and generates low replacement inversion temperature part, this low replacement inversion temperature partly comprises phase change region, its can by by electric current between this two electrode and between crystalline state and amorphous state, change; And
This replacement inversion temperature changes step and comprises with a material and being implanted in the outside of this phase change element, to increase the replacement inversion temperature of this outside, generates this higher replacement inversion temperature part.
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