CN101042924B - Method and apparatus for determining the time of flash memory element sensing - Google Patents
Method and apparatus for determining the time of flash memory element sensing Download PDFInfo
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- CN101042924B CN101042924B CN200610065593A CN200610065593A CN101042924B CN 101042924 B CN101042924 B CN 101042924B CN 200610065593 A CN200610065593 A CN 200610065593A CN 200610065593 A CN200610065593 A CN 200610065593A CN 101042924 B CN101042924 B CN 101042924B
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Abstract
This invention discloses one method to determine one flash element sense time, which comprises the following steps: discharging the first and second reference circuit level; determining first and second control signals. This invention also discloses one device to determine the flash element sense time, which comprises one first current tank, one second tank, one first reference page buffer area, second one, first reference level and second one, wherein, the first reference line is coupled between the first current tank and first reference buffer area and the second one between the second current tank and second reference buffer area.
Description
Technical field
The present invention relates to a kind of device that determines a sensing time method and carry out described method, refer to a kind of device that determines a sensing time method of the page buffer (page buffer) in the memory cell array at a flash element (memory cell array) and carry out described method especially.The triggering of described sensing time decision control signal is with initial reading and verification operation in described flash element.
Background technology
In a NAND type flash memory, the data that are stored in the internal storage location are read via a page buffer.Described page buffer also is used in and reads checking (read verification) and has writing on checking (programverification) and the erase verification (erase verification) of identity function.There is the aspect of many kind designs described page buffer.Fig. 1 is the design aspect of a kind of page buffer of routine, it is published in " A 3.3V 32 Mb NAND flash memory withincremental step pulse programming scheme " (IEEE Journal of Solid-State-Circuit, Vol.30, No.11, p.1149-1155, November 1995).Its read operation (read operation) is described below.At first, a word line (word line) (figure does not show) switches to low level, and making does not have electric current to take place in internal storage location.Afterwards, bit line (bitline) BL makes its ground connection discharge by conducting (turn on) NMOS 102 and 103.Then, bit line BL by close (turn off) NMOS 103 and 104 and conducting PMOS 101 make it be charged to V
CcThe mirror electric current (mirrored current) that the use one of described page buffer is provided by PMOS 101 promotes the current potential of bit line BL.Described mirror electric current with flow through one by the current ratio of access unit (accessed cell) (figure do not show), to define the current potential of described bit line BL.If describedly be in low starting voltage (low threshold voltage) by access unit, promptly be in erase status (erase state), it will be switched on and will have when reading with verification operation than the bigger electric current of described mirror electric current by described word line so.Therefore, bit line BL will discharge and NMOS 105 will be closed gradually.If describedly be in high starting voltage (high thresholdvoltage) by access unit, promptly be in write state (program state), the current potential of so described word line is can't conducting described by access unit.Therefore, described mirror electric current rises to high level state with bit line BL, with conducting NMOS 105.Behind a special time (being the signal development time, signal development time), described will be by the state of access unit by triggering in the bolt-lock (latch) that one " READ " pulse signal is sent to described page buffer and conducting NMOS 106.Therefore, be stored in and describedly will be sent to described page buffer by the data in the access unit.
In U.S. Pat 6,671, give up in 204 as the current mirror mode of Fig. 1 and change the page buffer circuit that adopts as Fig. 2.Selected when reading as bit line BLE, another bit line BLE then is taken as and covers bit line (shielding bit line) and use.Fig. 3 is the sequential chart of each signal among Fig. 2.In zone 2, at first bit line BLE and BLO are by conducting NMOS 201 and 203 and ground connection is discharged, and wherein signal VIRPWR is a ground connection.At this moment, node SO also discharges by conducting NMOS 202 and 204.Enter after the zone 3, signal BLSHFO switches to low level, and word line WL is thus lifted to gradually that high level signal BLSHFE then is biased into 2.0V and signal PLOAD drops to low level.This moment, node SO was thus lifted to V
CcAnd pairs of bit line BLE is charged to (2.0V-V
Th), V wherein
ThFor the starting voltage of NMOS 204 and be generally 1.0V.The starting voltage of the bias voltage of described 2.0V and NMOS 204 will be clamped down on the current potential of (clamp) bit line BLE.After the current potential of bit line BLE is stable, promptly enter zone 4.Among zone 4, signal BLSHFE is pulled to earth level (grounded) to close NMOS 204. in other words, if the signal on bit line BLE promptly begins development. had low starting voltage by access unit and be switched on, bit line BLE will be discharged into one than electronegative potential so. on the contrary, if had high starting voltage by access unit, it will can not be switched on and bit line BLE will remain on precharge potential (pre-charge voltage) so.Afterwards, enter zone 5 at signal development time (i.e. zone 4).At this, NMOS 204 is by conducting once more, but the current potential of signal BLSHFE only has 1.3V.If bit line BLE is in low level (NMOS 204 is switched on), has V so
CcThe node SO of level will discharge into bit line BLE.Yet if bit line BLE is in 1.0V or is describedly had high starting voltage by access unit, node SO will remain on V so
CcLevel and NMOS 204 close.By triggering a pulse PBLCHM, the state of node SO will be sent to a register 205 afterwards.In this routine techniques, triggering described pulse PBLCHM needs a timer (timer).Described timer will calculate a schedule time, switch to high level to guarantee signal PLOAD in zone 4.In zone 6, all bit lines and node SO will be grounded discharge once more subsequently.In zone 7, all control signals are with disabled (disabled).
U.S. Pat 6,925,005 is disclosed a kind of method for sensing in order to follow the trail of the position of internal storage location at bit line direction and word-line direction.Its memory cell array is distinguished into the several piece zone.Each zone has a reference bit lines in order to control the sensing time in described zone.Described reference bit lines has a reference unit (reference cell) on the word line of each intersection.That is, all reference bit lines have and the identical connection of normality bit line (normal bit line).Yet this kind design will make the starting voltage of adjusting described reference unit become inefficent.Another consideration is the problem about the drift of described reference unit starting voltage and interference (drifting/disturbance), and its normality bit line and reference bit lines by the next-door neighbour is caused.That is, when the normality unit was written into, corresponding word line rose to high level and has influence on the starting voltage of reference unit.In like manner, the drift of the starting voltage of described reference unit also can occur in erase operation (erase operation).
At another routine techniques, U.S. Pat 6,304 in 486, is then used a signal reference bit lines (signal referencebit line) and a plurality of reference unit.Each described reference unit is positioned on the crossover location of described signal reference bit lines and a plurality of word lines.It represents that each page or leaf (page) has a reference unit.After described reference unit passes through erase verification, will start the erase verification of normality unit.In addition, when described reference unit by after writing checking, will start the checking that writes of normality unit.Yet if one of them reference unit lost efficacy, its corresponding word line can't access normality unit so.Consideration in addition is, described reference unit is because of the integrity problem that checking and erase verification are caused that writes of the repetition of normality unit.
In addition, U.S. Pat 5,754,475 adopts a plurality of reference bit lines for being applied in the multilevel-cell design (multi-level cell design).Wherein the friendship crossover location in each word line and every described reference bit lines has a reference unit.Reference unit on each reference bit lines all has a starting voltage of adjusting (pre-tuned) in advance.Therefore yet this kind design is very consuming time in adjusting starting voltage in advance, has increased manufacturing cost widely and infeasible.32,000 word lines are for example arranged in 1GbNAND type flash element, therefore will have 96,000 reference units need adjust its starting voltage.Another problem then is the problem about the drift and the interference of described reference unit starting voltage, and its normality bit line and reference bit lines by the next-door neighbour is caused.
Above-mentioned routine techniques all needs a timer to control a control signal (for example signal PBLCHM among Fig. 2) to open the operation of beginning to read or write checking.In addition, described timer will calculate a schedule time and can be transformed into high level to guarantee signal PLOAD in the zone 4 of Fig. 3.In fact, by the sensing time (promptly in the zone 5 of Fig. 3, pulse PBLCHM rises to the time point of high level) that described timer is controlled, be to determine through computer simulation earlier, be implemented on the hardware circuit again.Therefore, this sensing time by described timer control causes lost efficacy (fail) because of bit line RC value (product of resistance value and capacitance) because of the variation that processing procedure caused most probably.
Summary of the invention
Fundamental purpose of the present invention provides a kind of sensing time method and the device of carrying out described method that determines a page buffer of the memory cell array in the flash element automatically.Secondary objective of the present invention provides a kind of method and apparatus to eliminate in a flash element threshold voltage shift and the interference that is caused reference unit when writing with erase operation.
For achieving the above object, the present invention discloses the device of a kind of sensing time of a page buffer that determines the memory cell array in the flash element, and it comprises: one first reference bit lines, one first electric current groove, one first reference page buffer zone, one second reference bit lines, one second electric current groove and one second reference page buffer zone.Described first reference bit lines is coupled between described first electric current groove and the described first reference page buffer zone, and described second reference bit lines is coupled between described second electric current groove and the described second reference page buffer zone.The described first and second electric current grooves all are arranged on outside the described memory cell array, and wherein said memory cell array is the position of normality unit and normality bit line.Described first and second reference bit lines discharge into one first predetermined voltage and one second predetermined voltage via the described first and second electric current grooves respectively, to determine one first control signal and one second control signal, the generation of described second control signal is determined by the voltage that the state and of described first control signal is coupled to the node of described second reference bit lines, and described first and second control signals are provided to the described page buffer in the described memory cell array, and the rise time of described second control signal determines the described sensing time.Therefore, the drift of the reference unit starting voltage that is produced when writing with read operation can be eliminated.In addition, the described first and second electric current grooves provide described first reference bit lines and described second reference bit lines, one grounding path respectively and are separately positioned on the distal-most end of the described first and second reference page buffer zones of distance.
In one embodiment, the described first and second electric current grooves by an independent reference unit (for example: the NAND unit) constitute, and its control grid is connected to a reference word line.In another embodiment, the described first and second electric current grooves all comprise plural fuse.(for example: MOS) be connected in series, its each described transistorized grid is connected to a reference word line to each fuse jointly after described a plurality of fuse parallel connections with a transistor.These fuses are in order to the flow through size of current of described electric current groove of adjustment.In addition, the normality word line of the described reference word line of the described first and second electric current grooves and normality unit is electrically isolated from one another.Therefore, the drift of reference unit starting voltage can effectively be eliminated.In addition, device of the present invention comprises one first in addition with reference to covering bit line and one the 3rd reference bit lines, in order to cover described first and second reference bit lines respectively.
About a sensing time method that determines a page buffer of the memory cell array in the flash element of the present invention, it comprises: discharge first reference bit lines that is coupled to one first reference page buffer zone via one first electric current groove (1); (2) via one second electric current groove one second reference bit lines that is coupled to one second reference page buffer zone is discharged; (3) when the voltage of described first reference bit lines arrives one first predetermined voltage, produce one first control signal; (4) when the voltage of described second reference bit lines arrives one second predetermined voltage, produce one second control signal.The generation of wherein said second control signal is determined by the current potential that the state and of described first control signal is coupled to the node of described second reference bit lines, described first and second control signals are provided to the described page buffer in the described memory cell array, and the generation time of described second control signal determines the described sensing time.
Description of drawings
Fig. 1 page buffer circuit diagram in the conventional NAND type flash element of demonstrating;
Fig. 2 page buffer circuit diagram in another conventional NAND type flash element of demonstrating;
Fig. 3 is the sequential chart of each signal of Fig. 2 when read operation;
Fig. 4 memory cell array synoptic diagram that the present invention is correlated with of demonstrating;
Fig. 5 (a) and 5 (b) are the circuit diagram of two embodiment of the first electric current groove;
Fig. 5 (c) and 5 (d) are the circuit diagram of two embodiment of the second electric current groove;
Fig. 6 is the circuit diagram of an embodiment of the first reference page buffer zone;
Fig. 7 is the circuit diagram of an embodiment of the second reference page buffer zone; With
Fig. 8 is the sequential chart of Fig. 4 each signal when read operation.
Embodiment
Below will be by a description of drawings embodiment who determines a sensing time method of a flash element and carry out the device of described method of the present invention.
Fig. 4 synoptic diagram that adopts a memory cell array 4 of a sensing time device 5 that determines a flash element of the present invention of demonstrating.Described memory cell array 4 comprises a string selection wire (string select line) SSL, a ground source electrode line (groundsource line) GSL, a plurality of word line (WL0～WLn) and a plurality of normality cell bit line (normal cell bitline) (BL0～BLm).Wherein (WL0～WLn) is coupled to the control grid (control gate) of a plurality of normalities unit 40 to each bar word line, and (BL0～BLm) is coupled to other string select transistor (string selecttransistor) SST, its other normality page of cells buffer zone (PB0～PBm) and other ground source transistor (groundsource transistor) GST to each bar normality cell bit line.The device 5 of a sensing time of a flash element that determines of the present invention comprises: one first reference bit lines RBL0, one second group of reference bit lines RBL1 and RBL2, one first electric current groove 52, one second electric current groove 54, one first reference page buffer zone RPB0 and one second reference page buffer zone RPB1.The described first reference bit lines RBL0 is coupled between described first electric current groove 52 and the described first reference page buffer zone RPB0, described second group of reference bit lines comprises one second reference bit lines RBL1 and one the 3rd reference bit lines RBL2, and it is coupled between described second electric current groove 54 and the described second reference page buffer zone RPB1.All (physical layout of BL0～BLm) is identical, and it reaches by identical processing procedure with described normality cell bit line for the physical layout of each reference bit lines RBL0, RBL1 and RBL2 (physical layout); But the source electrode of each reference bit lines RBL0, RBL1 and RBL2 and its corresponding string select transistor SST (source electrode) there is no and is electrically connected.Therefore, (BLO～BLm) is because of environment temperature or parameter variation (parameter variation) that processing procedure caused for each reference bit lines RBL0, RBL1 and RBL2 and described normality cell bit line, for example resistance capacitance product variation (RC variation), its effect just can be cancelled each other.In addition, writing or during erase operation, in order to eliminate the problem of reference unit (figure does not show) threshold voltage shift that is arranged in the described first and second electric current grooves 52 and 54, the described first and second electric current grooves 52 and 54 all are arranged on outside the described memory cell array 4 and are separately positioned on the distal-most end of described first and second reference page buffer zone RPB0 of distance and RPB1.In addition, the described first and second electric current grooves 52 and 54 are respectively unique grounding path of the described first reference bit lines RBL0 and described second group of reference bit lines RBL1 and RBL2.The device 5 that determines the sensing time of a flash element of the present invention comprises one first in addition with reference to covering bit line SBL0, and it is coupled in the described first reference page buffer zone RPB0 and in order to cover the described first reference bit lines RBL0.In when operation, if the described second reference bit lines RBL1 is set via 54 discharges of the described second electric current groove, so described the 3rd reference bit lines RBL2 will be by the described second reference page buffer zone RPB1 ground connection, to cover the described second reference bit lines RBL1; Vice versa.In other words, if described the 3rd reference bit lines RBL2 is set via the described second electric current groove 54 discharge, the so described second reference bit lines RBL1 will be by the described second reference page buffer zone RPB1 ground connection, to cover described the 3rd reference bit lines RBL2.
The circuit diagram of two embodiment of Fig. 5 (a) and the described first electric current groove 52 of 5 (b) demonstration.With reference to figure 5 (a), the described first electric current groove 52 realizes that with a NAND unit its control grid is connected to a reference word line RWL.Described NAND unit is one to have the reference unit (reference cell) and the described reference word line RWL that can adjust starting voltage and only reading, checking is in high level when (comprise and write checking and erase verification). in addition, described reference word line RWL and normality cell word lines be electrical isolation each other, therefore can not produce interference. when reading or verify, described normality page of cells buffer zone (control signal of PB0～PBm) will start and the control signal of described first and second reference page buffer zone RPB0 and RPB1 also will start. afterwards, described first and second reference page buffer zone RPB0 and RPB1 with output signal to described normality page of cells buffer zone (PB0～PBm), be stored in the data of described normality unit 40 with sensing. the result, the output signal of described first and second reference page buffer zone RPB0 and RPB1 is (as the signal PLOAD among Fig. 2, PBLCHM and PBLCHC) will trigger automatically, and not needing the additional designs counter to control the triggering of above-mentioned output signal. the first electric current groove 52 among Fig. 5 (b) comprises a plurality of fuse FUSE, each described fuse FUSE is connected in series with a transistor MOS, describedly a plurality ofly protect that the grid that is connected to the described first reference bit lines RBL0 and each described transistor MOS after the silk parallel connection is connected to described reference word line RWL. Fig. 5 (c) jointly and 5 (d) have similar structure with Fig. 5 (a) and 5 (b) respectively, two embodiment of its described second electric current groove 54 of demonstrating, its effect with two extra control signal SEL1 and described two the control signal SEL1 of SEL2. and SEL2 is described below. when MOS1 is switched on and MOS2 when being closed, the described second reference bit lines RBL1 will via the described second electric current groove 54 discharged and described the 3rd reference bit lines RBL2 will be via the described second reference page buffer zone RPB1 ground connection, to cover the described second reference bit lines RBL1. in like manner, when MOS2 is switched on and MOS1 when being closed, described the 3rd reference bit lines RBL2 will via the described second electric current groove 54 discharged and the described second reference bit lines RBL1 will be via the described second reference page buffer zone RPB1 ground connection, to cover described the 3rd reference bit lines RBL2. Fig. 6 is the circuit diagram of the embodiment of the described first reference page buffer zone RPB0, in order to determine one first control signal (for example signal PLOAD of Fig. 2) to switch to the time point of high level, be the end point of signal development time. Fig. 7 is the circuit diagram of the embodiment of the described second reference page buffer zone RPB1, in order to determine one second control signal (for example signal PBLCHM or the BLCHC of Fig. 2) to switch to the time point of high level, promptly start and read, write the sensing time of checking or erase verification. reference diagram 2,6 and 7, described first and second control signals will be provided to a page buffer that comprises two registers 205 and 206.
Below cooperate Fig. 8 to describe the principle of work of Fig. 6 in detail, wherein Fig. 8 is the sequential chart of Fig. 4 each signal when read operation.Suppose that signal VBL no matter be even bitlines or odd bit lines when being set in order to access data, all is designed to the waveform as VBLE among Fig. 3.In the zone 2 of Fig. 8, the at first described first reference bit lines RBL0 is grounded discharge by conducting NMOS 601.At this moment, node R SO0 is also discharged.Enter zone 3 afterwards, signal RBLSHF remains on 2.0V and signal RPLOAD is pulled to low level.Because node R SO0 is thus lifted to V by conducting PMOS 604
CcAnd signal PHI is a high level, and therefore a phase inverter 605 that comprises QP and QN will receive the input signal of a high level, and therefore according to the circuit design of Fig. 6, signal PLOAD will be pulled to low level.Simultaneously, the described first reference bit lines RBL0 will be stabilized in about 1.0V and signal RWL ' (being the signal on the described reference word line RWL) will rise to high level and make that the described first reference bit lines RBL0 can be via the discharge of the described first electric current groove, 52 ground connection (ginseng Fig. 5 (a) or 5 (b)).Enter zone 4 afterwards, signal RPLOAD switches to high level to close PMOS 604.At the same time, signal RWL ' have high level and make the described first reference bit lines RBL0 via the described first electric current groove 52 ground connection.Therefore, node R SO0 will begin to discharge into the described first reference bit lines RBL0 via NMOS603.When the current potential of node R SO0 and the described first reference bit lines RBL0 discharges into one first predetermined voltage (for example 0.3V), described phase inverter will sense the low level signal of node R SO0 and export a high level signal, make signal PLOAD switch back high level (path 1 of ginseng Fig. 8) once more, its expression signal development time is finished.This interval scale is discharged into the current potential of about described first predetermined voltage corresponding to the normality cell bit line by access unit with low starting voltage and the signal of node SO (ginseng Fig. 2) has been ready to be connected to described normality cell bit line.The level of signal PLOAD will be held in zone 6, yet signal PHI changes into low level.Reading signal RD, erase verification signal EVR and writing validation signal PVR among Fig. 6 is high level in order to the original state of guaranteeing signal PLOAD.In addition, NMOS 602 continues conducting, makes described first with reference to covering bit line SBL0 ground connection, in order to cover the described first reference bit lines RBL0.
Fig. 7 is the circuit diagram of the embodiment of the second reference page buffer zone RPB1, and wherein said the 3rd reference bit lines RBL2 is set in order to cover the described second reference bit lines RBL1.Ginseng Fig. 5 (c) or 5 (d), in the present embodiment, signal SEL1 continues to remain on high level.Cooperation is with reference to figure 8, and signal PLOAD switches to high level when regional 4 finish.After entering zone 5, node R SO1 is conducting to the described second reference bit lines RBL1.In other words, when the described second reference bit lines RBL1 discharges into one second predetermined voltage (for example 0.3V) by the described second electric current groove 54, MOS 701 will be switched on and node R SO1 will be from V
CcHigh level and discharged.When the current potential of node R SO1 drops to about 0.5V
CcThe time, phase inverter Q1 will sense a low imput, and export a signal PUL.Described signal PUL imports a circuit D1 and reads and write verification operation (ginseng U.S. Pat 6 to produce a pulse signal PBLCHM (path 2 of ginseng Fig. 8) in order to startup with described signal RD and the said write validation signal PVR of reading, Fig. 7 of 671,204 and Fig. 9).In addition, described signal PUL can import a circuit D2 to produce a pulse signal PBLCHC in order to start erase verification operation (Figure 16 of ginseng U.S. Pat 6,671,204) with described erase verification signal EVR.Circuit A among Fig. 7 (comprising a capacitor C 1, phase inverter Q2 and Q3) is in order to the generation of delayed pulse signal PBLCHM and PBLCHC, yet described circuit A can omit.Circuit B (comprising a capacitor C 2 and a phase inverter Q4) is in order to the pulsewidth of decision pulse signal PBLCHM and PBLCHC.As shown in Figure 7, the generation of the described second control signal PBLCHM (or PBLCHC) is determined by the current potential that the state and of the described first control signal PLOAD is coupled to the node R SO1 of the described second reference bit lines RBL1.In a NAND type flash element, the normality unit need be wiped free of and write.And erase verification is similar to read operation with the operation that writes checking, and the device that determines a sensing time method of a flash element and carry out described method therefore of the present invention is also applicable to above-mentioned erase verification with write the operation of checking.For example, at Fig. 2, signal PBLCHM is be triggered (active) when reading and writing checking (Fig. 9 and Fig. 7 of ginseng U.S. Pat 6,671,204); Signal PBLCHC is be triggered when erase verification (Figure 16 of ginseng U.S. Pat 6,671,204).
The circuit of Fig. 6 and Fig. 7 in conjunction with the circuit of Fig. 4 in order to automatically, accurately and not need use timer ground to produce control signal PLOAD, PBLCHM and PBLCHC.In addition, method and apparatus proposed by the invention can omit in the routine techniques in decision sensing necessary computer simulation step during the time, and does not also need to consider the situation under the extreme operating environment (for example abnormal environment temperature or operating voltage) when the described NAND type flash element of design.In addition, method and apparatus of the present invention also can be eliminated the problem of the threshold voltage shift of reference unit when writing the operation of checking or erase verification.In sum, the present invention can reach its intended purposes really.
Technology contents of the present invention and technical characterstic disclose as above, yet the those skilled in the art still may be based on teaching of the present invention and announcement and made all substitutions and modifications that do not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise the various substitutions and modifications of the present invention that do not deviate from, and is contained by appended claim.
Claims (25)
1. one kind determines the flash memory element sensing time method, and described flash element comprises a page buffer and a plurality of normalities unit that is arranged in a memory cell array, it is characterized in that described method comprises following steps:
Via one first electric current groove one first reference bit lines that is coupled to one first reference page buffer zone is discharged;
Via one second electric current groove one second reference bit lines that is coupled to one second reference page buffer zone is discharged;
When the voltage of described first reference bit lines arrives one first predetermined voltage, produce one first control signal; With
When the voltage of described second reference bit lines arrives one second predetermined voltage, produce one second control signal;
The generation of wherein said second control signal is determined by the current potential that the state and of described first control signal is coupled to the node of described second reference bit lines, described first and second control signals are provided to the described page buffer in the described memory cell array, and the rise time of described second control signal determines the described sensing time.
2. decision flash memory element sensing time method according to claim 1 is characterized in that described second control signal reads, writes checking or smear checking in order to startup.
3. decision flash memory element sensing time method according to claim 1, it is characterized in that comprising in addition with reference to the step of covering bit line ground connection with one first, described first reference is covered bit line and is coupled to the described first reference page buffer zone, to cover described first reference bit lines.
4. decision flash memory element sensing time method according to claim 1, it is characterized in that comprising in addition step with one the 3rd reference bit lines ground connection, described the 3rd reference bit lines is coupled to described second reference page buffer zone and the described second electric current groove, to cover described second reference bit lines.
5. decision flash memory element sensing time method according to claim 1 is characterized in that the physical layout of described first and second reference bit lines is identical with the physical layout of the bit line of described normality unit.
6. decision flash memory element sensing time method according to claim 1 is characterized in that described first electric current groove or the described second electric current groove comprise a NAND unit, and its control grid is connected to a reference word line.
7. decision flash memory element sensing time method according to claim 6 is characterized in that described reference word line when reading, writing checking or smearing checking, is in high level.
8. decision flash memory element sensing time method according to claim 6 is characterized in that the described second electric current groove comprises in addition:
One the first transistor is connected in series with described second reference bit lines and described NAND unit; With
One transistor seconds is connected in series with one the 3rd reference bit lines and described NAND unit, and wherein said the 3rd reference bit lines is in order to cover described second reference bit lines.
9. decision flash memory element sensing time method according to claim 1, it is characterized in that the described first or second electric current groove comprises a plurality of fuses, an each described fuse and a transistor series connection, described a plurality of fuses parallel connections and each transistorized grid are connected to a reference word line jointly.
10. decision flash memory element sensing time method according to claim 9 is characterized in that the described second electric current groove comprises two transistors in addition, is connected in series described second reference bit lines and one the 3rd reference bit lines respectively, uses for covering control.
11. decision flash memory element sensing time method according to claim 1 is characterized in that described flash element is a NAND type flash element.
12. decision flash memory element sensing time method according to claim 1 is characterized in that the described first and second electric current grooves are arranged on outside the described memory cell array.
13. a device that determines the flash memory element sensing time, described flash element comprise a page buffer and a plurality of normalities unit that is arranged in a memory cell array, it is characterized in that described device comprises:
One first electric current groove;
One second electric current groove;
One first reference page buffer zone;
One second reference page buffer zone;
One first reference bit lines is coupled between described first electric current groove and the described first reference page buffer zone; With
One second reference bit lines is coupled between described second electric current groove and the described second reference page buffer zone;
Wherein said first and second reference bit lines discharge into one first predetermined voltage and one second predetermined voltage via the described first and second electric current grooves respectively, to determine one first control signal and one second control signal, the generation of described second control signal is determined by the voltage that the state and of described first control signal is coupled to the node of described second reference bit lines, and described first and second control signals are provided to the described page buffer in the described memory cell array, and the rise time of described second control signal determines the described sensing time.
14. the device of decision flash memory element sensing time according to claim 13 is characterized in that described first electric current groove or the described second electric current groove comprise a NAND unit, its control grid is connected to a reference word line.
15. the device of decision flash memory element sensing time according to claim 14 is characterized in that the normality word line electrical isolation of described reference word line and described normality unit.
16. the device of decision flash memory element sensing time according to claim 13 is characterized in that comprising in addition one first with reference to covering bit line, it is connected to the described first reference page buffer zone to cover described first reference bit lines.
17. the device of decision flash memory element sensing time according to claim 16 is characterized in that described first is earthy to cover described first reference bit lines with reference to covering bit line.
18. the device of decision flash memory element sensing time according to claim 13 is characterized in that comprising in addition one the 3rd reference bit lines, is coupled in described second reference page buffer zone and the described second electric current groove, in order to cover described second reference bit lines.
19. the device of decision flash memory element sensing time according to claim 18 is characterized in that described the 3rd reference bit lines ground connection, in order to cover described second reference bit lines.
20. the device of decision flash memory element sensing time according to claim 13 is characterized in that the physical layout of described first and second reference bit lines is identical with the physical layout of the bit line of described normality unit.
21. the device of decision flash memory element sensing time according to claim 13, it is characterized in that the described first or second electric current groove comprises a plurality of fuses, an each described fuse and a transistor series connection, described a plurality of fuse parallel connection, each described transistorized grid is connected to a reference word line jointly.
22. the device of decision flash memory element sensing time according to claim 21 is characterized in that the described second electric current groove comprises two-transistor in addition, is connected in series described second reference bit lines and one the 3rd reference bit lines respectively, uses for covering control.
23. the device of decision flash memory element sensing time according to claim 13 is characterized in that the described first and second electric current grooves are arranged on outside the described memory cell array.
24. the device of decision flash memory element sensing time according to claim 23 is characterized in that the described first and second electric current grooves are arranged at the distal-most end of the described first and second reference page buffer zones of distance respectively.
25. the device of decision flash memory element sensing time according to claim 13 is characterized in that described flash element is a NAND type flash element.
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| CN200610065593A CN101042924B (en) | 2006-03-24 | 2006-03-24 | Method and apparatus for determining the time of flash memory element sensing |
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| CN200610065593A CN101042924B (en) | 2006-03-24 | 2006-03-24 | Method and apparatus for determining the time of flash memory element sensing |
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| CN103811071B (en) * | 2012-11-15 | 2016-10-19 | 北京兆易创新科技股份有限公司 | The read method of a kind of high reliability NAND Flash and system thereof |
Citations (3)
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|---|---|---|---|---|
| US5930172A (en) * | 1998-06-23 | 1999-07-27 | Advanced Micro Devices, Inc. | Page buffer for a multi-level flash memory with a limited number of latches per memory cell |
| US6304486B1 (en) * | 1999-12-20 | 2001-10-16 | Fujitsu Limited | Sensing time control device and method |
| CN1601653A (en) * | 2003-09-22 | 2005-03-30 | 晶豪科技股份有限公司 | Device for opening character line decoder by balance of reference line |
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2006
- 2006-03-24 CN CN200610065593A patent/CN101042924B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5930172A (en) * | 1998-06-23 | 1999-07-27 | Advanced Micro Devices, Inc. | Page buffer for a multi-level flash memory with a limited number of latches per memory cell |
| US6304486B1 (en) * | 1999-12-20 | 2001-10-16 | Fujitsu Limited | Sensing time control device and method |
| CN1601653A (en) * | 2003-09-22 | 2005-03-30 | 晶豪科技股份有限公司 | Device for opening character line decoder by balance of reference line |
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