CN101237029B - Memory device - Google Patents
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- CN101237029B CN101237029B CN 200810005166 CN200810005166A CN101237029B CN 101237029 B CN101237029 B CN 101237029B CN 200810005166 CN200810005166 CN 200810005166 CN 200810005166 A CN200810005166 A CN 200810005166A CN 101237029 B CN101237029 B CN 101237029B
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Abstract
A memory device is provided, which includes a first conductive layer, a second conductive layer, and a memory layer interposed between the first conductive layer and the second conductive layer. The memory layer includes a first portion and a second portion, each of which includes at least a nanoparticle. The nanoparticle includes a conductive material coated with an organic film. The first portion is in contact with the first conductive layer and the second conductive layer, and a side surface of the first portion is surrounded by the second portion.
Description
Technical field
The semiconductor device that the present invention relates to memory element and have this memory element.
Background technology
In recent years, having the semiconductor device that is integrated in a plurality of circuit on the insulating surface and has various functions is developed.In addition, also carry out for being arranged on the exploitation that electric wave that antenna that semiconductor device is set up receives is converted to electric energy and utilizes this electric energy to carry out the semiconductor device of data transmit-receive.This semiconductor device is called as wireless chip (being also referred to as ID label, IC tag, IC chip, RF (radio frequency) label, wireless identification tag, electronic tag or RFID (radio-frequency (RF) identification)), and has been introduced into a part of market.
Majority in these semiconductor devices that have been practical comprises circuit (being also referred to as IC (integrated circuit) chip) and the antenna that uses such as Semiconductor substrate such as silicon.And this IC chip is by formations such as memory circuit (being also referred to as memory), control circuits.Especially, many data storage circuit can be stored by arranging, just the semiconductor device with higher function and high added value can be provided.Yet although silicon substrate is expensive, these semiconductor devices are required to make with low cost.This is cause with the much the same needs of disposable commodities because small semiconductor device as wireless chip is waited in expectation.Therefore, in recent years, the OTFT (below, be also referred to as " organic tft "), organic memory etc. that organic compound are used for control circuit and memory circuit etc. are developed (for example, with reference to patent document 1) energetically.
[patent document 1] Japanese Patent Application Publication 2002-26277 communique
Form memory element as the storage area of organic memory by organic compound layer is set between pair of electrodes, and when data writing, utilize the variation such as electrical characteristics such as resistance values that occurs owing to applying of voltage.In many cases, this organic compound layer forms by vapour deposition.
In the situation about forming using vapour deposition, owing to only use the part of vaporized organic compound, so the utilization ratio of material is low.And obsolete material also evaporates, and therefore has the large problem of energy input in the manufacturing process.
In addition, by making in the situation of organic memory of the vapour deposition of metal mask, need the position alignment operation of metal mask.Therefore, the rate of finished products because of the bad product in location aimed at reduces.
Summary of the invention
Therefore, provide memory element with the objective of the invention is easy, cheapness and high finished product rate.In addition, the purpose of this invention is to provide the semiconductor device with described memory element.
In the present invention, memory element has at least the first conductive layer, the second conductive layer, is clipped in the accumulation layer between the first conductive layer and the second conductive layer.This accumulation layer is made of the nano particle that the electric conducting material that is covered by organic film forms, and can use damp process to form.Typically say, can adopt liquid droplet ejection method or print process etc., wherein more preferably form accumulation layer with liquid droplet ejection method.For example, spray (ejection) and will be dispersed in by the nano particle that the electric conducting material that is covered by organic film consists of composition in the solvent as drop, and carry out drying and evaporate this solvent, form accumulation layer.Accordingly, can improve the utilization ratio of material and form easily memory element.In addition, owing to rate of finished products increases, so memory element can be provided at an easy rate.
Note, the organic film that covers nano particle is equivalent to have the gathering that prevents nano particle in injected constituent (being also referred to as blasting materials) and with the dispersant of the function of particle-stabilised dispersion, for example, consisted of by the material that can form with the electric conducting material that nano particle has coordinate bond or surfactant etc.In addition, blasting materials also is included in the material (such as reducing agent) that uses when making nano particle, adhesive, plasticizer, silane coupling agent etc. sometimes except comprising electrical-conductive nanometer particle, dispersant, solvent.Therefore, at least all if electric conducting material that has with nano particle forms the material of coordinate bond or surfactant etc. and consists of the organic film that covers nano particle by dispersant, and the material that uses can be included in the manufacturing nano particle time, adhesive, plasticizer, silane coupling agent etc.
By above-mentioned memory element is applied voltage, the electrical characteristics that change memory element are come data writing.For example, electrical characteristics comprise resistance value.When data writing, the conductive part that the welding by the nano particle that is made of electric conducting material of the first paired conductive layer and the second conductive layer forms is electrically connected.That is to say, utilize the resistance change that is produced by the short circuit between the first conductive layer and the second conductive layer to write.
In addition, the first conductive layer of the memory element before writing alternately is connected to the second conductive layer by a plurality of dielectric film and a plurality of conductive layers that are made of the electric conducting material in the nano particle that are made of organic film.That is to say, the first conductive layer be connected the relation of conductive layer and also can be described to the structure that connects by a plurality of capacity cells that multilayer connects.Therefore, writing of being undertaken by applying of voltage can be expressed as also that described capacity cell carries out by destroying.In the case, described insulating barrier has at least than described the 3rd conductive layer and manys the structure of one deck.
In this manual, write voltage so long as by to applying voltage between the first conductive layer and the second conductive layer voltage of the electrical property change of memory element being got final product, and this is had no particular limits.In this manual, the minimum value of this applied voltage that needs for the electrical characteristics that make memory element change significantly is recited as writes voltage.In addition, read voltage and be in order to read write element not and the difference of the electrical characteristics between the write element and the applied voltage that uses, it is not so long as make the voltage of the electrical property change degree of memory element get final product, and this is had no particular limits.
In addition, sometimes the first conductive layer and the second conductive layer are recited as electrode.
One of the present invention is a kind of memory element, comprising: the first conductive layer; The second conductive layer; Be clipped in the accumulation layer between described the first conductive layer and described the second conductive layer, wherein, described accumulation layer comprises the conductive part (being also referred to as first) that utilizes part (being also referred to as second portion) that the nano particle formed by the electric conducting material that is covered by organic film consists of and described nano particle welding and form, and described the first conductive layer and described the second conductive layer are electrically connected by described conductive part.
One of the present invention is a kind of memory element, comprising: the first conductive layer; The second conductive layer; Be clipped in the accumulation layer between described the first conductive layer and described the second conductive layer, wherein, described accumulation layer comprises the part of utilizing the nano particle formed by the electric conducting material that is covered by organic film to consist of, described nano particle welding and space between the conductive part that forms and the side that is formed on this conductive part and the described part that is made of nano particle, and described the first conductive layer and described the second conductive layer are electrically connected by described conductive part.
One of the present invention is a kind of memory element, comprising: the first conductive layer; The second conductive layer; Be clipped in the accumulation layer between described the first conductive layer and described the second conductive layer, wherein, described accumulation layer comprises utilizes part, the space that is formed on this part inboard and described nano particle that the nano particle is formed by the electric conducting material that is covered by organic film consists of welding and the conductive part that forms in this space, and this conductive part is used for described the first conductive layer and the electrical connection of described the second conductive layer.
One of the present invention is a kind of memory element, comprising: the first conductive layer; The second conductive layer; Be clipped in the accumulation layer between described the first conductive layer and described the second conductive layer, wherein, described accumulation layer comprises the part of utilizing the nano particle formed by the electric conducting material that is covered by organic film to consist of, described nano particle welding and the conductive part and the space that form, and, described the first conductive layer and described the second conductive layer are electrically connected by described conductive part, and the side of described conductive part is centered on by the described part that is made of nano particle by described space.
In said structure, also can provide insulating barrier or semiconductor layer between at least one party in accumulation layer and the first conductive layer and the second conductive layer.
For example, accumulation layer forms by liquid droplet ejection method.In addition, insulating barrier and semiconductor layer also can form by liquid droplet ejection method.In the case, preferably form insulating barrier with the insulating properties organic compound.
In addition, one of the present invention also can be the semiconductor device that disposes a plurality of above-mentioned memory elements by rectangular.And each of these a plurality of memory elements also can be connected to thin-film transistor.
According to the present invention, can be easy and high finished product rate ground make the semiconductor device that has the memory element of superior Performance And Reliability and possess this memory element.Therefore, can provide at an easy rate memory element and the semiconductor device with superior Performance And Reliability.
Description of drawings
Fig. 1 is the figure of a configuration example of explanation memory element of the present invention;
Fig. 2 A to C is the figure of the action mechanism of explanation memory element of the present invention;
Fig. 3 A and 3B are the figure of an example of the vertical view of the accumulation layer of expression before and after writing;
Fig. 4 is the figure of a mode of expression liquid-droplet ejecting apparatus;
Fig. 5 A to 5C is the figure of a configuration example of explanation memory element of the present invention;
Fig. 6 A to 6C is the figure of a configuration example of explanation semiconductor device of the present invention;
Fig. 7 A to 7C is the figure of the memory cell that has of explanation semiconductor device of the present invention;
Fig. 8 A to 8C is the figure of a configuration example of explanation memory element of the present invention;
Fig. 9 A to 9C is the figure of a configuration example of explanation semiconductor device of the present invention;
Figure 10 A to 10C is the figure of the memory cell that has of explanation semiconductor device of the present invention;
Figure 11 A to 11D is the figure of a mode of explanation thin-film transistor;
Figure 12 is the figure of a configuration example of explanation semiconductor device of the present invention;
Figure 13 A to 13C is the figure of a configuration example of explanation semiconductor device of the present invention;
Figure 14 A and 14B are the figure of a part in the cross section of explanation semiconductor device of the present invention;
Figure 15 A and 15B are the figure of a part in the cross section of explanation semiconductor device of the present invention;
Figure 16 A and 16B are the figure of explanation semiconductor device of the present invention;
Figure 17 A to 17D is the figure of the semiconductor device of explanation shaped like chips of the present invention;
Figure 18 A to 18F is the figure that explanation is equipped with the article of semiconductor device of the present invention;
Figure 19 is the figure that explanation is equipped with the portable phone of semiconductor device of the present invention;
Figure 20 is the figure of the voltage-current characteristic of the memory element made according to embodiment 1 of expression;
Figure 21 is the figure along the section of film thickness direction of the accumulation layer of the memory element made according to embodiment 1 of expression;
Figure 22 is the sectional view of the memory element made according to embodiment 1;
Figure 23 is the sectional view of the memory element made according to embodiment 1;
Figure 24 is the ideograph of memory element of the present invention;
Figure 25 A and 25B are the figure of a structure of the memory element after expression writes.
Selection figure of the present invention is Fig. 2.
Embodiment
Below, illustrate with reference to accompanying drawing about embodiments of the present invention and embodiment.But the ordinary person of affiliated technical field can understand at an easy rate a fact and be exactly, and the present invention is not limited to the following description, and its mode and detailed content can be transformed to various forms and not break away from aim of the present invention and scope thereof.Therefore, the present invention should not be interpreted as only being limited in the content that execution mode shown below and embodiment put down in writing.Notice that in the structure of the present invention of following explanation, sometimes common use represents the symbol of same section in different accompanying drawings.
A configuration example of memory element of the present invention is described with reference to Fig. 1.Memory element shown in Figure 1 comprises the first conductive layer 110, the second conductive layer 112, is clipped in the accumulation layer 111 between the first conductive layer 110 and the second conductive layer 112, and wherein accumulation layer 111 utilizes the nano particle that is formed by the electric conducting material that is covered by organic film to consist of.Figure 24 illustrates the ideograph of memory element, and wherein Reference numeral 113 represents the nano particle that organic films, 114 expressions are made of electric conducting material.As shown in figure 24, the second conductive layer 112 is arranged on described the first conductive layer 110, and clipping alternate configurations in the middle of it has the dielectric film that is made of organic film 113 to reach the zone of the nano particle 114 that is made of electric conducting material.In other words, the first conductive layer 110 alternately is connected to the second conductive layer 112 by a plurality of dielectric films that are made of organic film 113 with by the conductive layer that the electric conducting material in a plurality of nano particles 114 consists of.Thus, the first conductive layer be connected the structure that capacity cell that the relation of conductive layer also can be described to connect by multilayer connects.
The action mechanism of memory element of the present invention at first, is described with reference to Fig. 2.Vertical view and the sectional view of the memory element after the sectional view of the memory element before Fig. 2 A represents to write, Fig. 2 B and 2C represent to write.Before applying voltage, the accumulation layer 111 before namely writing utilizes the nano particle that is formed by the electric conducting material that is covered by organic film to consist of.Therefore, accumulation layer 111 does not have conductivity, and the resistance value of memory element is high.When applying voltage between to the first conductive layer 110 of this memory element and the second conductive layer 112, little electric current flows through accumulation layer 111, thereby produces Joule heat.Because this Joule heat, organic film is decomposed, and the nano particle that is made of electric conducting material is in contact with one another and welding.Thus, accumulation layer 111 is by low resistance, and is last, and shown in Fig. 2 C, the first conductive layer 110 and the second conductive layer 112 are electrically connected by the conductive part 120 that is formed by welding, thereby memory element becomes short-circuit condition.The resistance change of the memory element before and after as mentioned above, voltage applies.
According to above-mentioned action mechanism, utilize the resistance change of the memory element that applies voltage and produce, carry out data and write.
What in addition, be formed on conductive part 120 in the accumulation layer 111 after writing is shaped as column, taper or spherical.Certainly, be not limited to the shape such as above-mentioned description, as long as have by the function of conductive part 120 with the first conductive layer 110 and 112 electrical connections of the second conductive layer, get final product.In addition, its cross section is owing to the welding of the nano particle that consists of with electric conducting material forms, thereby sometimes has irregularly shapedly, and is not limited to symmetrical shape.In addition, at least one conductive part 120 is formed in the accumulation layer 111, it is formed the position be not particularly limited.
In addition, space 121 be formed on conductive part 120 around.Because the conductive part 120 that is formed by decomposition and the welding of organic film occupy the zone less than the zone of occupying of the nano particle before the welding, so produce space 121.Because produce this space 121, accumulation layer 111 itself is not shunk, so the second conductive layer 112 is not subjected to stress.Therefore, the second conductive layer 112 does not produce distortion, keeps certain distance between the first conductive layer 110 and the second conductive layer 112 after writing yet.Thus, in the situation that other layers etc. are provided at the second conductive layer 112, the film that does not need to worry these other layers peels off etc.Notice that the shape in space 121 roughly depends on the shape of conductive part 120, but depends on the material for accumulation layer 111.
Note, although in accumulation layer 111, might occur can not make the first conductive layer 110 and the second conductive layer 112 to be electrically connected the situation that the conductive part that is electrically connected with the first conductive layer 110 is formed.Therefore, accumulation layer 111 can also have the conductive part that only is electrically connected with the first conductive layer 110 except having said structure.In addition, according to the formation of described conductive part, in the accumulation layer 111 of the many parts of the welding amount of nano particle, produce the space.Therefore, accumulation layer 111 can also have the space around described conductive part.Certainly, shape and the quantity in described conductive part and described space are also had no particular limits.
Note, shown in Figure 25 B, sometimes do not produce the space around the conductive part 120.Therefore, write accumulation layer 111 afterwards and needn't have the space.In addition, as mentioned above, the cross section of conductive part 120 has irregularly shaped sometimes, and for example the welding amount according to nano particle also can be conductive part such shown in Figure 25 A 120.
An example of the vertical view of the accumulation layer 111 before and after Fig. 3 represents to write.Vertical view among Fig. 3 is illustrated in the section along 1/2 part of film thickness direction of accumulation layer 111.Accumulation layer 111 before Fig. 3 A represents to write, the accumulation layer 111 after Fig. 3 B represents to write.
Next, the material that can be used for each layer is described.As the first conductive layer 110 and second conductive layer 112 of memory element of the present invention, can adopt to have the high metal of individual layer or laminated construction and conductivity, alloy, compound etc.
For example, except such as the gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), aluminium (Al), manganese (Mn), titanium (Ti), the metal of tantalum (Ta) etc., perhaps the nitride of metal material (for example, titanium nitride, tungsten nitride, molybdenum nitride) in addition, can also enumerate the first family that belongs to the periodic table of elements or the metal of second family, namely such as lithium (Li), the alkali metal such as caesium (Cs), such as magnesium (Mg), calcium (Ca), the alkaline-earth metal such as strontium (Sr), and comprise any these alloys (for example, Mg:Ag, Al:Li) etc.In addition, can also use rare earth metals such as europium (Er), ytterbium (Yb) and comprise these alloy etc.In addition, also can use indium tin oxide as nesa coating (below, be written as ITO), siliceous indium tin oxide, contain the indium oxide (abbreviation: IZO) etc. of 2wt% to 20wt% zinc oxide (ZnO).
Notice that the first conductive layer 110 is by formation such as vapour deposition, sputtering method, CVD method, print process, galvanoplastic, electroless plating method, spin-coating methods.
The second conductive layer 112 forms by vapour deposition, sputtering method, CVD method, print process, spin-coating method.
As the electric conducting material that is used to form nano particle, use the metallic element that is selected from gold (Au), silver (Ag), platinum (Pt), nickel (Ni), copper (Cu), palladium (Pd), tantalum (Ta), iridium (Ir), rhodium (Rh), tungsten (W), aluminium (Al), iron (Fe), zinc (Zn), tin (Sn), titanium (Ti), the indium (In) etc. or with the alloy material of these elements as main component.In addition, can also be mixed with the metal sulfide of cadmium (Cd), zinc (Zn); The oxide of germanium (Ge), silicon (Si), zirconium (Zr), barium (Ba) or above-mentioned metallic element etc., in the halide one or more.In addition, also can use ITO as nesa coating, siliceous indium tin oxide, IZO etc. as electric conducting material.
Note, using under the two or more element or the situation of compound as electric conducting material, its admixture is had no particular limits.For example, above-mentioned two or more element or each of compound were existed equably, can make again wherein any partially at central part.
The particle diameter of nano particle is that 1nm is above and below the 200nm, and it is above and below the 100nm to be preferably 1nm, and the particle diameter that is contained in the nano particle in the blasting materials is preferably evenly.
In addition, nano particle also can pass through any formation in vapour deposition, liquid phase method, the solid phase method, and its manufacture method is had no particular limits.
Note, when applying voltage, according to the electric conducting material that consists of nano particle hole (void) occurs between particle sometimes.This is because the very fast cause of crystal growth rate of electric conducting material.By being set as very low to the applied voltage of memory element or using alloy material as nano particle, can suppress the generation in above-mentioned hole.Therefore, can obtain the higher memory element of reliability.
The organic film that covers nano particle is equivalent to have the gathering that prevents nano particle in solvent and with the dispersant of the function of particle-stabilised dispersion.Therefore, the compound of formation organic film is made of the material that can form with the metallic element that electric conducting material has coordinate bond or surfactant etc.Here, comprise amino, mercapto (SH), sulfane two bases (S-), hydroxyl (OH), oxygen base (O-), carboxyl (COOH), the cyano group (material of the not share electron pair that nitrogen CN) etc., sulphur, oxygen atom etc. have as forming the material of coordinate bond with metallic element, can enumerating.For example, can use the azanol class such as monoethanolamine; Aminated compounds such as polymine, polyvinylpyrrolidone; Alcohols is such as polyvinyl alcohol; The alkyl sulfide alcohols; The dithiol class; Glycols such as ethylene glycol, diethylene glycol (DEG), macrogol; Polyacrylic acid; Carboxymethyl cellulose etc.In addition, as surfactant, for example can use anion surfactant such as two (2-second hexyl) sulfo-butanedioic acid, neopelex; The Arrcostab of non-ionic surface active agent such as poly-alkyl diol, alkyl phenylate etc.; Fluorine class surfactant; Has the copolymer of polymine and polyethylene glycol oxide etc.Note, when to the dispersant more than the nano particle use 30wt%, the viscosity increased of blasting materials, the therefore preferred above and dispersant below the 30wt% of 1.0wt% that uses.
The nano particle that above-mentioned electric conducting material by being covered by organic film consists of is dispersed in the solvent and is ejected.As solvent, can make water or organic solvent, this organic solvent can be water-miscible organic solvent or water-insoluble organic solvent.For example, as water-miscible organic solvent, can enumerate ethanol such as methyl alcohol, ethanol, propyl alcohol, butanols, glycerine, DPG, ethylene glycol; Ketone such as acetone, methylethylketone; Glycol ethers such as glycol monoethyl ether, ethylene glycol monoethyl ether, ethylene glycol monobutyl ether, diethylene glycol monobutyl ether; 2-Pyrrolidone; Water-soluble organic compounds containing nitrogen is such as N-first pyrrolidones; Ethyl acetate etc.As water-insoluble organic solvent, can enumerate alkane such as octane, nonane, decane; Cycloalkanes; Aromatic series such as toluene, dimethylbenzene, benzene, dichloro-benzenes.Certainly, do not need only to use a kind of in these solvents, as long as be not separated each other at solvent, just can mix the use multi-solvents.
Fig. 4 illustrates a mode for the liquid-droplet ejecting apparatus of liquid droplet ejection method.Each shower nozzle 205, the shower nozzle 212 of drop injection unit 203 are connected with control unit 207, and it is by being drawn pre-set figure by computer 210 controls.About the opportunity of drawing, for example get final product take the mark 211 that forms at substrate 200 as benchmark.Perhaps, also can be take the edge of substrate 200 carry out as benchmark.Use image unit 204 to detect these benchmark, and graphics processing unit 209 is transformed to digital signal with it, computer 210 identifications this and produce control signal, and it is sent to control unit 207.As image unit 204, can use imageing sensor that utilizes charge coupled cell (CCD) or complementary metal oxide semiconductors (CMOS) etc.The information of the figure that will form on substrate 200 is deposited in the memory media 208, based on this information control signal is delivered to control unit 207, thereby controls respectively each shower nozzle 205, the shower nozzle 212 of drop injection unit 203.The material that sprays is fed to respectively shower nozzle 205, shower nozzle 212 from material source of supply 213 and material source of supply 214 through piping.
Shower nozzle 205 inside have the space of filling liquid material and the nozzle of jet shown in dotted line 206.Although do not illustrate in the accompanying drawing, shower nozzle 212 also has the internal structure same with shower nozzle 205.For example, in shower nozzle 205 situation different with the jet size of shower nozzle 212, can draw simultaneously different materials with different width.Certainly, also can draw simultaneously identical material with different width.
In the situation of using large-sized substrate, shower nozzle 205 and shower nozzle 212 can scan along the direction of arrow in the accompanying drawings freely, and can freely set the zone of drawing, thereby also can draw a plurality of identical figures at a substrate.In addition, can freely set the zone of drawing by objective table is moved.Certainly, shower nozzle and objective table are moved.
In addition, the viscosity of the material of injection is preferably below the 20mPas, and this is in order to make material successfully from nozzle ejection.In addition, the surface tension of the material of injection is preferably below the 40mN/m.Yet, can suitably regulate according to the solvent that adopts, purposes etc. viscosity of blasting materials etc.For example, will in solvent, disperse the viscosity of the blasting materials of gold or Nano silver grain to be set as more than the 5mPas and below the 20mPas, got final product.
By using above-mentioned liquid-droplet ejecting apparatus, the blasting materials that will be dispersed in by the nano particle that the electric conducting material that is covered by organic film consists of in the solvent is ejected on the desirable position, then carries out drying so that the solvent gasification.Although this drying condition is according to employed solvent and difference, for example, when using propyl alcohol as solvent, processes and get final product carrying out drying about 5 minutes under 100 ℃.In addition, also can be provided with by heating when spraying the substrate of the first conductive layer 110, to shorten the dry required time.
Notice that blasting materials also is included in the material that uses when making nano particle, adhesive, plasticizer, silane coupling agent etc. sometimes except comprising electric conducting material, dispersant, solvent.Use heat reactive resin as adhesive, such as enumerating the organic resins such as polyimides, acrylic acid, novolac resin, melmac, phenol resin, epoxy resin, silicones, furane resins, diallyl phthalate resin.In addition, because the convergent force of heat reactive resin by using adhesive, can suppress to occur nano particle inhomogeneous weld each other.And, by using these resins, the viscosity that can regulate blasting materials.
Therefore, cover the organic film of the nano particle that consists of accumulation layer 111 except comprising dispersant, sometimes also comprise solvent, the material (such as reducing agent) that when making nano particle, uses, adhesive, plasticizer, silane coupling agent etc.In addition, solvent is retained in the organic film sometimes.As mentioned above, the organic film that consists of accumulation layer 111 is made of the material that can form with the metallic element that nano particle has coordinate bond or surfactant etc. at least, but also can have the material that uses when the manufacturing nano particle, adhesive, plasticizer, silane coupling agent etc.
In addition, although the situation that forms accumulation layer 111 with liquid droplet ejection method has been described hereinbefore, also can be by making the blasting materials high viscosity and using the print process take silk screen printing as representative to form accumulation layer 111.Print process is also compared with vapour deposition etc., can improve the utilization ratio of material and form easily accumulation layer 111.But, be not limited to these methods, also can form with other damp process accumulation layer 111.
In addition, the first conductive layer 110 and the second conductive layer 112 also can form by using liquid droplet ejection method.
According to above-mentioned operation, can easy and high finished product rate ground manufacturing memory element of the present invention.Because memory element of the present invention can not be wiped the data that write in the memory element once, so can prevent from rewriting caused forgery.So, the good memory element of manufacturing property and reliability at an easy rate.
About the voltage that memory element of the present invention is applied, both can apply the voltage higher than the second conductive layer 112 to the first conductive layer 110, can apply the voltage higher than the first conductive layer 110 to the second conductive layer 112 again.
In addition, the structure of memory element is not limited to structure shown in Figure 1, also can adopt structure shown in Figure 5.Memory element shown in Fig. 5 A comprises the first conductive layer 110, layer 300, accumulation layer 111 and the second conductive layer 112, wherein, layer 300 and accumulation layer 111 be by the first conductive layer 110 and 112 clampings of the second conductive layer, and be contacted with layer and be formed with accumulation layer 111 on 300.Note, the film thickness of layer 300 is had no particular limits, but it is above and below the 50nm to be preferably 0.1nm.
Shown in Fig. 5 A, by being provided, insulating barrier can further reduce the leakage current that flows into when reading voltage in the write element not applying.Therefore, can be reduced in the power consumption that needs when reading.
In addition, as mentioned above, by making accumulation layer 111 attenuates, can reduce the voltage that writes of memory element of the present invention.Yet, write voltage although when carrying out filming, can reduce, just increase leakage current when reading if excessively carry out filming.In this case, it is effectively providing insulating barrier.
This insulating barrier can form by vapour deposition, sputtering method, CVD method, print process, spin-coating method, sol-gel process or liquid droplet ejection method etc.Especially, preferably with having the organic compound of insulating properties and forming by liquid droplet ejection method.In the case, be ejected on the desirable position by the composition that wherein said organic compound or its reactive material are dissolved in the organic solvent, and remove this solvent, form insulating barrier.Therefore, be used to form the solvent of the composition of accumulation layer 111 by adopting and be used to form the solvent conduct that is separated between the organic solvent of insulating barrier, even when forming insulating barrier, not exclusively get rid of organic solvent, also can spray the constituent that forms accumulation layer 111.Therefore, need to not provide separately the drying process of removing solvent in order to form insulating barrier, for example, be enough to as long as when forming insulating barrier, the substrate that is provided with the first conductive layer 110 just heated.In addition, this drying process can be processed in conjunction with carrying out with the drying of carrying out when forming accumulation layer 111 in the operation in the back.And, owing to have low-density characteristic by liquid droplet ejection method with the insulating barrier that the organic compound with insulating properties forms, so compare with method by utilizing other or with the insulating barrier that other insulating material forms, layer 300 almost is not set causedly writes increasing of voltage, thereby can be reduced in the leakage current that flows into when reading in the write element not.
In addition, layer 300 also can be semiconductor layer, can use inorganic semiconductors such as molybdenum oxide, tin oxide, bismuth oxide, silicon fiml, vanadium oxide, nickel oxide, zinc oxide, SiGe, GaAs, gallium nitride, indium oxide, indium phosphide, indium nitride, cadmium sulfide, cadmium telluride, Strontium titanate films to form.
This semiconductor layer also can form by liquid droplet ejection method or print process.In addition, as other formation method, can use vapour deposition, electronic beam method, sputtering method, CVD method, spin-coating method, sol-gel process etc.
In addition, the structure of memory element is not limited to the structure shown in Fig. 5 A, also can shown in Fig. 5 B, be contacted with the second conductive layer 112 layering of reliefs 300.In addition, shown in Fig. 5 C, also can be contacted with the first conductive layer 110 and the second conductive layer 112 ground and form two layers 300.
As mentioned above, by providing insulating barrier or semiconductor layer with being contacted with at least one party in the first conductive layer and the second conductive layer, can reduce the leakage current that when reading, flows in the write element not.Therefore, can also reduce power consumption.
In the present embodiment, with reference to accompanying drawing the semiconductor device with memory element of the present invention is described, is typically storage device.Be the situation of passive matrix in this structure of describing storage device.
Fig. 6 A represents a configuration example of the semiconductor device shown in the present embodiment.Semiconductor device 400 comprises that wherein memory element 401 is set to rectangular memory cell array 411, decoder 412 and 413, selector 414, read/write circuits 415.Notice that the structure of semiconductor device 400 shown here is an example, also can comprise other circuit such as sense amplifier, output circuit, buffer.
Notice that decoder 412 and 413, selector 414, read/write circuits 415, interface etc. both can similarly be formed on the substrate with memory element, can be used as again the IC chip and were arranged on the outside.
Fig. 7 represents the vertical view of memory cell array 411 and an example of sectional view.Fig. 7 A represents the vertical view of the part of memory cell array 411.
In memory cell array 411, be provided with memory element 401 rectangularly.Memory element 401 comprises at substrate: the first conductive layer 510; Accumulation layer; The second conductive layer 512, wherein, this first conductive layer 510 extends at first direction (A-B), and this accumulation layer and the second conductive layer 512 extend in the second direction vertical with first direction (C-D).Note, between a plurality of accumulation layers and the second conductive layer 512, be provided with at the upwardly extending partition wall of second party (insulating barrier) 520, will be at the upper adjacent memory element of first direction (A-B) separately by utilizing this partition wall (insulating barrier) 520.Note, can be by be formed for each layer of memory element 401 with the material shown in the execution mode 1.In Fig. 7 A, covering partition wall (insulating barrier) 520 and the 512 ground settings of the second conductive layer have been omitted and as the insulating barrier of diaphragm.
Notice that the first conductive layer 510 in the present embodiment is equivalent to the first conductive layer 110 in the execution mode 1, and accumulation layer is equivalent to accumulation layer 111.In addition, the second conductive layer is equivalent to the second conductive layer 112 in the execution mode 1.Represent the part same with execution mode 1 with common Reference numeral, and omit for same section or detailed explanation with part of said function.
The example of the cross section structure between the A-B among Fig. 7 B presentation graphs 7A, the example of the cross section structure between the C-D among Fig. 7 C presentation graphs 7A.As the substrate 521 that is provided with memory element 401, except glass substrate, flexible substrate, can also use quartz substrate, silicon substrate, metal substrate, stainless steel lining at the bottom of, the paper made by fiber material etc.Flexible substrate refer to can crooked (having flexible) substrate, such as the plastic of being made by Merlon, polyarylate (polyarylate), polyether sulfone etc. etc.In addition, also can use film (being made by polypropylene, polyester, poly-ethylene fluoride, polyvinyl chloride etc.).
In addition, both can thin-film transistor (TFT) be set and memory element 401 was set thereon in dielectric substrate, and can use again the Semiconductor substrate such as Si or SOI substrate to replace above-mentioned substrate and form field-effect transistor (FET) and memory element 401 is set thereon at this substrate.In addition, also can be by memory element 401 and thin-film transistor or field-effect transistor be fit together to arrange.In the case, can make memory element 401 and thin-film transistor or field-effect transistor by utilizing different operations, then by with conductive film, anisotropy conductiving glue etc. memory element section and thin-film transistor or field-effect transistor being fit together to provide.
In Fig. 7 B and 7C, at first by utilizing vapour deposition, sputtering method, CVD method, print process, galvanoplastic, electroless plating method, liquid droplet ejection method etc., form the first conductive layer 110 at substrate 521.Then, by utilizing sputtering method, CVD method, print process, liquid droplet ejection method, spin-coating method, vapour deposition etc. to form partition wall (insulating barrier) 520.As partition wall (insulating barrier) 520, can use the inorganic insulating materials such as silica, silicon nitride, silicon oxynitride; Acrylic acid, methacrylic acid, with and derivative; Heat-proof macromolecule such as polyimides, aromatic polyamide, polybenzimidazoles (polybenzimidazole) etc.; Perhaps silicone resin.In addition, also can use following resin material: vinylite such as polyvinyl alcohol, polyvinyl butyral resin, epoxy resin, phenolic resins, novolac resin, acrylic resin, melmac, ammonia ester resin etc.In addition, can also use the organic materials such as benzocyclobutene, Parylene, fluoro arylene ether, polyimides; Contain the composition of water-soluble homopolymer and water solubility copolymer etc.In addition, cross section between A-B is in the cross section of the partition wall shown in Fig. 7 B (insulating barrier) 520, and the side of partition wall (insulating barrier) 520 can have above and less than 60 degree of 10 degree, be preferably the above and following angle of inclination of 45 degree of 25 degree for the surface of the first conductive layer 110.Moreover the side of partition wall (insulating barrier) 520 is preferably crooked.By adopting this shape, when using liquid droplet ejection method to form accumulation layer 111, can prevent that blasting materials from crossing and surpass preposition greatly and enlarge.Then, as mentioned above, form accumulation layer 111 at the first conductive layer 110 by the use liquid droplet ejection method.And, form the second conductive layers 112 in accumulation layer 111 by use vapour deposition, sputtering method, CVD method, print process or liquid droplet ejection method etc.Then, covering partition wall (insulating barrier) 520 and the second conductive layer 112 ground provide the insulating barrier 522 as diaphragm.Diaphragm can use silica, silicon nitride, silicon oxynitride etc., and can prevent the intrusion of moisture or oxygen etc.
In addition, the cross section between C-D is in the cross section of the first conductive layer 110 shown in Fig. 7 C, and the side of the first conductive layer 110 preferably has approximate vertical with respect to the surface of substrate 521 or 10 degree are above and the inclination of less than 90 degree.And the first conductive layer 110 also can have radius of curvature continually varying shape.Notice that approximate vertical refers to 90 degree (± 1 degree).By adopting this shape, can improve the coverage rate of the accumulation layer 111 that is layered on the first conductive layer 110 and second conductive layer 112 etc.
Because the blasting materials that is used to form accumulation layer 111 is liquid, so be subject to being formed the very large impact of the surface state in district.Thus, also can control to partition wall (insulating barrier 520) processing of wetability.The wetability of the surface of solids is subjected to the chemical property on surface and the impact of physical surface shape (surface roughness).In the present invention, the processing of control surface wetability refers to form the processing in the zone with wetability different from this blasting materials in the adhering zone of the blasting materials of liquid state.The zone that wetability is different refers to variant with respect to the blasting materials wetability, i.e. the different zone of the contact angle of blasting materials.The zone that the contact angle of blasting materials is large is the lower zone of wetability (below be also referred to as low wetability district), and the little zone of contact angle is the higher zone of wetability (below be also referred to as the high wettability district).When contact angle was large, the liquid injection material did not enlarge on area surfaces, and when contact angle hour, blasting materials enlarges.Like this, the zone that wetability is different has different surface energies.The surface energy in the zone that wetability is low is low, and the surface energy in the high zone of wetability is large.
The difference of wetability is the relativeness in two zones.Here, form low wetability district by the partition wall that will form the district (insulating barrier) 520 in accumulation layer 111, can form the zone with wetability different with desirable formation zone.As the method that optionally forms low wetability district, can use following methods etc.: form mask layer, and use this mask layer optionally to form the method for the layer that is consisted of by low wetability material; Optionally reduce the surface treatment method of wetability.
Method as change, control surface wetability has by utilizing irradiation Energy Decomposition surface mass, makes the area surfaces modification and the method for wettability change.As the low material of wetability, can use the material that comprises fluorocarbon radical (fluorocarbon chain) or the material that comprises silane coupling agent.Because silane coupling agent can form monomolecular film, thus can effectively carry out modification, thus wettability change at short notice.In addition, silane coupling agent is arranged on the substrate by the material that not only will have fluorocarbon chain, and the material that will have an alkyl also is arranged on the substrate, and therefore the low wetability of expression can be used.In addition, as the low material of wetability, also can use titanate esters couplant, aluminate couplant.
Liquid blasting materials moves to the high place of wetability, forms pattern so can be implemented on the more accurate position.In addition, can improve the utilization ratio of material.
In addition, shown in the cross section structure between the C-D of Fig. 8 A, the element with rectification is set between the first conductive layer 110 that also can be in memory element 401 and the substrate 521.As the element with rectification, except Schottky barrier type, PIN type, PN type diode, can also enumerate the transistor of diode connection etc.At this, the diode 611 that is made of the 3rd conductive layer 612 and semiconductor layer 613 is set with it contiguously at the first conductive layer for 110 times.Note, separated by interlayer dielectric film 614 corresponding to the diode 611 of each memory element.In addition, also can have the element of rectification with accumulation layer 111 opposite side settings contiguously with the second conductive layer 112.
In addition, when having when worrying the affecting of the electric field between the upper adjacent memory element of second direction (C-D), shown in Fig. 8 B, also can between the first conductive layer 110 of each memory element, partition wall (insulating barrier) 621 be set.Thus, not only can prevent the impact on the electric field between the adjacent memory element, and can prevent because the fracture of the accumulation layer 111 that the step of the first conductive layer 110 occurs when the first conductive layer 110 ground arrange accumulation layer 111 when covering.
Note, in the cross section of the partition wall shown in Fig. 8 B (insulating barrier) 621, the side of partition wall (insulating barrier) 621 can have above and less than 60 degree of 10 degree for the surface of the first conductive layer 110, is preferably the above and following angle of inclination of 45 degree of 25 degree.Moreover the side of partition wall (insulating barrier) 621 is preferably crooked.So, after partition wall (insulating barrier) 621 is set, covers the first conductive layer 110 and partition wall (insulating barrier) 621 ground and form accumulation layer 111 and the second conductive layer 112.In addition, be not limited to said structure, shown in Fig. 8 C, can also only form accumulation layer 111 at the first conductive layer 110.In the case, preferably partition wall (insulating barrier) 621 is controlled the processing of wetability, formed low wetability district.
Below, with the data write activity of explanation to memory element.At this, by utilizing electric effect, typically come the situation of data writing with reference to Fig. 6 explanation by applying voltage.Note, write by the electrical characteristic that changes memory element, and to make the initial condition (when not applying the electric state of doing the time spent) of memory element be data " 0 " that making the state after the electrical characteristic change is data " 1 ".
When to memory element 401 data writings " 1 ", at first by decoder 412 and 413 and selector 414 Selective storage elements 401.Particularly, predetermined potential V2 is applied to the word line W3 that is connected with memory element 401 by decoder 413.In addition, by decoder 412 and selector 414, the bit line B3 that is connected to memory element 401 is connected to read/write circuits 415.Then, will write current potential V1 from read/write circuits 415 and output to bit line B3.Like this, to applying voltage Vw (Vw=V1-V2) between the first conductive layer of consisting of this memory element 401 and the second conductive layer.By suitably selecting voltage Vw, physics or electrically change the accumulation layer that is arranged between this conductive layer carries out writing of data " 1 ".Particularly, accumulation layer is changed into following state to be got final product: reading under the operation voltage, the first conductive layer when data are the state of " 1 " and the resistance between the second conductive layer much smaller than data during for the state of " 0 " the first conductive layer and the resistance between the second conductive layer.For example, the first conductive layer and the second conductive layer being short-circuited gets final product.For example, voltage Vw is that 5V is above and below the 15V, perhaps-15V above and-5V is following to be got final product.
Note, control unselected word line and unselected bit line so that data " 1 " be not written to these unselected word lines and memory element that bit line is connected in.For example, making unselected word line and unselected bit line be in quick condition gets final product.In addition, the current potential that unselected word line is applied with the second conductive layer same degree gets final product.
On the other hand, when data " 0 " when being written to memory element 401, not applied electric effect to memory element 401 and get final product.From circuit operation, for example same with the situation that writes " 1 ", by decoder 412 and 413 and selector 414 come Selective storage element 401, yet will become from the output potential that read/write circuits 415 outputs to bit line B3 with the current potential of the current potential of selecteed word line W3 or unselected word line roughly the same, and will can not change memory element 401 electrical characteristic degree voltage (for example,-5V is above and 5V is following) be applied between the first conductive layer and the second conductive layer that consists of memory element 401, get final product.
Next, with reference to Fig. 6 B action when from the memory element reading out data will be described.Come reading out data by utilizing the following fact: at the memory element with data " 0 " with have between the memory element of data " 1 ", the electrical characteristic between the first conductive layer and the second conductive layer is different.For example, be described as follows read method: read under the voltage the first conductive layer of consisting of the memory element with data " 0 " and the effective resistance between the second conductive layer (below, the resistance that is called simply memory element) be R0, and be R1 at the resistance that reads the memory element that has data " 1 " under the voltage, and read by the difference of utilizing resistance.Note, satisfy R1＜＜R0.Concerning read/write circuits 415, for example can use the circuit of the resistive element 450 that has shown in Fig. 6 B and differential amplifier 451 as the structure of reading section.Resistive element 450 has resistance value Rr, and satisfies R1＜Rr＜R0.In addition, shown in Fig. 6 C, can also replace resistive element 450 with transistor 452, and also can replace differential amplifier 451 with clocked inverter 453.To clocked inverter 453 input signal φ or its inversion signal, this signal psi or its inversion signal become High when reading, become Low when not reading.Certainly, circuit structure is not limited to Fig. 6 B and 6C.
When reading out data from memory element 402, at first by decoder 412 and 413 and selector 414 come Selective storage element 402.Particularly, by decoder 413, predetermined voltage Vy is applied to the word line Wy that is connected with memory element 402.In addition, by decoder 412 and selector 414, the bit line Bx that will be connected with memory element 402 is connected to the terminals P of read/write circuits 415.As a result, the current potential Vp of terminals P becomes following value, namely by resistive element 450 (resistance value Rr) and memory element 402 (resistance value R0 or R1) Vy and V0 is carried out resistance and cuts apart the value determined.Thereby when memory element 402 had data " 0 ", the current potential Vp0 of terminals P became Vp0=Vy+ (V0-Vy) * R0/ (R0+Rr).In addition, when memory element 402 had data " 1 ", the current potential Vp1 of terminals P became Vp1=Vy+ (V0-Vy) * R1/ (R1+Rr).The result, by in Fig. 6 B, selecting Vref so that it is between Vp0 and Vp1, and in Fig. 6 C, select the change point of clocked inverter 453 so that it is between Vp0 and Vp1, can be according to data " 0 "/" 1 ", as output potential Vout output Low/High (perhaps High/Low), read.
For example, make differential amplifier 451 actions with Vdd=3V, and set Vy=0V, V0=3V, Vref=1.5V.Suppose to set R0/Rr=Rr/R1=9, Vp0=2.7V when the data of memory element be " 0 ", and output High is as Vout, and when the data of memory element are " 1 " Vp1=0.3V, and export Low as Vout.Like this, can carry out reading of memory element.
According to said method, cut apart by the difference and the resistance that utilize resistance value, read the state of the resistance of accumulation layer with magnitude of voltage.Certainly, read method is not limited to the method.For example, except the difference of utilizing resistance, can also read by the difference of utilizing current value.In addition, when the electrical characteristic of memory element has the different diode characteristic of between data " 0 " and data " 1 " threshold voltage, also can read by the difference of utilizing threshold voltage.
In addition, both can thin-film transistor (TFT) be set and memory element or memory element array were set thereon in dielectric substrate, and can use again the Semiconductor substrate such as Si or SOI substrate to replace above-mentioned dielectric substrate and form field-effect transistor (FET) and memory element or memory element array are set thereon at substrate.
Data to the semiconductor device shown in the present embodiment write not just once, can append (writing afterwards).On the other hand, because can not wipe data in the memory element that writes once, so can prevent from rewriting caused forgery.Moreover, because comprise can be easy and the memory element of the present invention made of high finished product rate ground, so can make at an easy rate the semiconductor device with superior Performance And Reliability.
Notice that present embodiment also can suitably make up with other execution modes and embodiment.Thus, the memory element that has of the semiconductor device shown in the present embodiment for example also can provide insulating barrier or semiconductor layer between at least one party in accumulation layer and the first conductive layer and the second conductive layer.
Execution mode 3
In the present embodiment, with reference to Fig. 9 the semiconductor device with memory element of the present invention is described.Note, particularly, the active array type storage device will be described.
Fig. 9 A represents a configuration example of the semiconductor device shown in the present embodiment.Semiconductor device 700 comprises memory cell array 711, decoder 712 and 713, selector 714, read/write circuits 715.In this memory cell array 711, memory cell 701 is set to rectangular.Notice that the structure of semiconductor device 700 shown here is an example, also can comprise other circuit such as sense amplifier, output circuit, buffer.
Notice that decoder 712 and 713, selector 714, read/write circuits 715, interface etc. both can similarly be formed on the substrate with memory element, can be used as again the IC chip and were arranged on the outside.
Then, with reference to Figure 10 the vertical view of the memory cell array 711 with said structure and an example of sectional view are described.Notice that Figure 10 A represents the vertical view of the part of memory cell array 711.
In memory cell array 711, be provided with a plurality of memory cell 701 rectangularly.In memory cell 701, be provided with as the thin-film transistor 721 of switch element and the memory element that is connected with this thin-film transistor 721 at the substrate with insulating surface.
The example of the cross section structure between the A-B among Figure 10 B presentation graphs 10A.Note, in Figure 10 A, omitted the partition wall (insulating barrier) 822, accumulation layer 111, the second conductive layer 112, the insulating barrier 522 that are arranged on the first conductive layer 110.
A mode of thin-film transistor 721 is described with reference to Figure 11.Figure 11 A illustrates an example using top gate type thin film transistor.Be provided with insulating barrier 901 as basilar memebrane at substrate 521, and be provided with thin-film transistor 910 at insulating barrier 901.In thin-film transistor 910, be formed with semiconductor layer 902 and can be used as the insulating barrier 903 of gate insulation layer at insulating barrier 901, and on semiconductor layer 902, be formed with gate electrode 904 across insulating barrier 903.Note, be provided with as the insulating barrier 905 of protective layer and the insulating barrier 821 that is used as interlayer insulating film at thin-film transistor 910.In addition, form the wiring 907 in the source region and the drain region that are connected respectively to semiconductor layer.
By using one deck or two-layer above multilayer insulating film such as silicon oxide film, silicon nitride film or oxygen silicon nitride membrane etc., form insulating barrier 901.Note, can be by forming insulating barrier 901 with sputtering method, CVD method etc.
As semiconductor layer 902, except the non-crystalline semiconductors such as amorphous silicon, half amorphous semiconductor, crystallite semiconductor etc., can also use crystallinity semiconductor film such as polysilicon etc.
Especially, the following crystallinity semiconductor of advantageous applications: the crystallinity semiconductor that the combination by laser beam irradiation, heat treated or heat treated and laser beam irradiation obtains the semiconductor crystallization of amorphous or crystallite.In heat treated, can use and use the crystallization method that has the metallic element of the effect that promotes the Si semiconductor crystallization such as nickel etc.
Undertaken by laser beam irradiation in the situation of crystallization, can be by the irradiation of continuous oscillation laser beam, or by having repetition rate and the pulse duration below 1 nanosecond more than the 10MHz, being preferably the irradiation of the high repetition frequency ultrashort pulse light of 1 to 100 picosecond, realize crystallization; Wherein make melting the semi-conductive melting zone of crystallinity be arranged towards the direction of illumination continuous moving of this laser beam.By this crystallization method, can obtain to have the crystallinity semiconductor that greater particle size and crystal grain boundary extend towards a direction.Drift bearing by making charge carrier is consistent with the direction that this crystal grain boundary extends, and just can improve transistorized field effect mobility.For example, can realize 400cm
2The mobility that/Vsec is above.
In the situation of the processing of the crystallization below the heat resisting temperature (about 600 ℃) that uses glass substrate as above-mentioned crystallization operation, can use large-area glass substrate.Thus, a large amount of semiconductor devices can be made to each substrate, thereby cost can be reduced.
In addition, also can be by carrying out the crystallization operation with the heating that can bear the substrate of heating-up temperature and carry out more than the heat resisting temperature of glass substrate, to form semiconductor layer 902.Typically, by using quartz substrate as dielectric substrate, and at heating amorphous or crystallite semiconductor more than 700 ℃, form semiconductor layer 902.As a result, can form the semiconductor of high crystalline.In the case, can provide the characteristics such as response speed and mobility good and can carry out the thin-film transistor of high speed motion.
Can by using the poly semiconductor of metal or a kind of conductive-type impurity that mixed, form gate electrode 904.When using metal, can use tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), aluminium (Al) etc.In addition, above-mentioned nitride metal can also be used and the metal nitride that obtains.Perhaps, also can be the stacked ground floor that is consisted of by this metal nitride and the structure that is obtained by the second layer that metal consists of.When adopting laminated construction, also can for the end of ground floor than the outside outstanding so-called hat-shaped in the end of the second layer.At this moment, be metal nitride by making ground floor, just can make it become barrier metal.That is to say, can prevent that the metal of the second layer is diffused in insulating barrier 903 or the semiconductor layer under it 902.
Note, also can form in the side of gate electrode 904 sidewall (sidewall spacer) 908.Can by following operation, form sidewall: utilize the CVD method to form insulating barrier, then utilize RIE (reactive ion etching) method to carry out anisotropic etching for this insulating barrier.
For the transistor that consists of by combined semiconductor layer 902, insulating barrier 903, gate electrode 904 etc., can use various structures such as single drain electrode structure, LDD (lightly doped drain) structure, the overlapping drain structure of grid.Figure 11 A represents to have the thin-film transistor of LDD structure, wherein with the overlapping semiconductor layer of sidewall in form low concentration impurity district 909.In addition, also can use single grid structure, multi-gate structure, double-gate structure.In this multi-gate structure, be applied in the mode of the transistor series connection of the upward gate voltage of same potential of equal value.In this double-gate structure, semiconductor layer is sandwiched between its gate electrode up and down.
By using inorganic insulating materials such as silica and silicon oxynitride, perhaps organic insulating materials such as acrylic resin and polyimide resin forms insulating barrier 821.When using rubbing methods such as spin coated, print roll coating, can use the insulating barrier that is consisted of by silica of after coating is dissolved in insulating film material in the organic solvent, carrying out heat treatment and forming.For example, can be with by lower implementing the insulating barriers that heat treatments form at 200 ℃ to 400 ℃ after the coated film that comprises siloxane bond in formation.As insulating barrier 821, the wiring that just can prevent from being formed on this layer is broken by the insulating barrier that uses the insulating barrier that forms by rubbing method or realize planarization by reflux (reflow).In addition, when forming multilayer wiring, also can effectively utilize the insulating barrier that forms by above-mentioned operation.
A wiring that can the layer identical with utilization and gate electrode 904 forms arranges the wiring 907 that is formed on the insulating barrier 821 across, and this wiring 907 has Miltilayer wiring structure.Can be by stacked a plurality of insulating barriers that have with the same function of insulating barrier 821, and form wiring thereon, form Miltilayer wiring structure.Wiring 907 is preferred by the low electrical resistant material such as combination as aluminium (Al) with use the barrier metal of refractory metal materials such as titanium (Ti) or molybdenum (Mo), namely by the laminated construction of titanium (Ti) and aluminium (Al) formation, formed by the laminated construction of molybdenum (Mo) and aluminium (Al) formation etc.
Figure 11 B illustrates the example of using bottom gate thin film transistor.Be formed with insulating barrier 901 in dielectric substrate 521, and be provided with thin-film transistor 920 thereon.In thin-film transistor 920, be provided with gate electrode 904, as insulating barrier 903 and the semiconductor layer 902 of gate insulation layer.And be provided with channel protective layer 921 thereon, be used as the insulating barrier 905 of protective layer and the insulating barrier 821 that is used as interlayer insulating film.Can also form the insulating barrier as protective layer thereon.The wiring 907 that is connected respectively to the source region of semiconductor layer and drain region can be formed on the layer of the upper or insulating barrier 821 of the layer of insulating barrier 905.Note, when adopting bottom gate thin film transistor, also can not form insulating barrier 901.
In addition, when substrate 521 when having flexible substrate, its heat resisting temperature is lower than the inlexibility substrates such as glass substrate.Therefore, preferably use organic semiconductor to form the semiconductor layer of thin-film transistor.
At this, with reference to Figure 11 C and 11D the structure that organic semiconductor is used in the thin-film transistor of semiconductor layer is described.Figure 11 C illustrates an example using staggered organic semiconductor transistor.Be provided with organic semiconductor transistor 931 having flexible substrate 930.Organic semiconductor transistor 931 comprises gate electrode 932, as the insulating barrier 933 of gate insulating film, be arranged on the semiconductor layer 934 in the overlapping place of gate electrode 932 and insulating barrier 933, and connect up and 907 be connected to semiconductor layer 934.Notice that semiconductor layer and the insulating barrier 933 that is used as gate insulating film and connecting up 907 contacts.
Can by utilizing material and the method identical with insulating barrier 903, form the insulating barrier 933 as gate insulating film.But, when when be dissolved in insulating film material in the organic solvent in coating after, forming insulating barrier by heat treatment, be lower than in heat treatment temperature in the situation of the heat resisting temperature with flexible substrate and carry out.
As the material of the semiconductor layer 934 that is used for organic semiconductor transistor, can enumerate poly-ring aromatic compounds, have the compound, phthalocyanine, charge migration type complex compound of conjugated double bond etc.For example, can use anthracene, aphthacene, pentacene, six thiophene (6T), tetracyano-p-quinodimethane (TCNQ), perylene carboxylic acid anhydrides (PTCDA), naphthoic acid acid anhydride (NTCDA) etc.In addition, as the material of the semiconductor layer 934 that is used for organic semiconductor transistor, can enumerate the pi-conjugated family macromolecule of organic high molecular compound etc.; Carbon nano-tube; Polyvinyl pyridine; Phthalocyanine metal complex etc.Especially, pi-conjugated macromolecule such as the polyacetylene, polyaniline, polypyrrole, polyethylene, polythiofuran derivative, poly-(3-alkylthrophene), poly-arylene (polyarylene) derivative, poly-arylene ethene (polyarylene vinylene) derivative that preferably use its skeleton to be consisted of by conjugated double bond.
In addition, as the formation method of the semiconductor layer of organic semiconductor transistor, can use vapour deposition, rubbing method, spin-coating method, scraper coating process (bar coating method), solution casting method (solution casting method), infusion process, silk screen print method, print roll coating method or liquid droplet ejection method.This thickness is preferably more than the 1nm and below the 1000nm, more preferably more than the 10nm and below the 100nm.
Figure 11 D illustrates the example of using the coplanar type organic semiconductor transistor.Be provided with organic semiconductor transistor 941 having flexible substrate 930.Organic semiconductor transistor 941 comprises gate electrode 932, as the insulating barrier 933 of gate insulating film, be arranged on the semiconductor layer 934 in the overlapping place of gate electrode 932 and insulating barrier 933, and connect up and 907 be connected to semiconductor layer 934.In addition, be connected to the wiring 907 and the insulating barrier and the semiconductor layer that are used as gate insulating film of semiconductor layer 934.
As long as thin-film transistor or organic semiconductor transistor can be used as switch element, just can have any structure.Note, both can with wiring 907 the first conductive layers that are utilized as in the memory element of the present invention, memory element of the present invention can be connected to again wiring 907.
In addition, also can be by forming transistor with single crystalline substrate or SOI substrate, and memory element is set thereon.The SOI substrate can form by the method for using attached with sheet (wafer), the method that is called SIMOX.In this SIMOX method, by oxonium ion being imported in the Si substrate, form insulating barrier 831 in the Si substrate interior.
For example, when single crystal semiconductor was used as substrate, shown in Figure 10 C, the field-effect transistor 832 that provides with single crystal semiconductor substrate 830 was provided memory element 801.In addition, insulating barrier 833 is set with covering the wiring be connected to field-effect transistor 832, and at this insulating barrier 833 memory element 801 is set.
Because this transistor that is formed by single crystal semiconductor, the characteristics such as its response speed or mobilance are good, so the transistor that can carry out high speed motion can be provided.In addition, because the inhomogeneities of this transistorized characteristic seldom, so the semiconductor device of realizing high reliability can be provided.
Notice that memory element 801 comprises the first conductive layer 110, accumulation layer 111, the second conductive layer 112 that is formed on the insulating barrier 833, and accumulation layer 111 is by the first conductive layer 110 and 112 clampings of the second conductive layer.
So, form memory element 801 by insulating barrier 833 is set, can freely dispose the first conductive layer 110.In other words, in the structure of Figure 10 B, need in avoiding being connected to the zone of transistorized wiring, memory element be set, yet by insulating barrier 833 is set, for example as Figure 10 C, can above transistor 832, form memory element 801.As a result, can make memory circuit further highly integrated.The first conductive layer that the wiring 907 that certainly, also field-effect transistor 832 can be had has as memory element.
Notice that although the example that accumulation layer 111 is set continuously along first direction (A-B) has been shown, these accumulation layers 111 also can only be arranged on each memory cell in the structure shown in Figure 10 B and the 10C.By adopting this structure, can further improve the utilization ratio of material.
In addition, also can substrate arrange peel ply and this peel ply form comprise transistorized layer 1030 and memory element 801 after, utilize peel ply to comprise transistorized layer 1030 and memory element 801 from substrate desquamation, use adhesion layer 1032 will comprise that transistorized layer 1030 and memory element 801 are fitted on the substrate 1031 different from above-mentioned substrate then shown in Figure 12ly.As stripping means, can make with the following method and wait: (1) is at the substrate with high-fire resistance and comprise between the transistorized layer and metal oxide layer is set as peel ply, make this metal oxide layer embrittlement by crystallization, the method that comprises transistorized layer to peel off this; (2) at the substrate with high-fire resistance and comprise arrange between the transistorized layer comprise hydrogen amorphous silicon film as peel ply, then by laser beam irradiation or etch away this amorphous silicon film, peel off this and comprise transistorized layer; (3) by machinery or use solution or fluoridize halogen gas such as NF
3, BrF
3, ClF
3Deng etching, remove the method for the substrate that is formed with the high-fire resistance that comprises transistorized layer; (4) at the substrate with high-fire resistance with comprise and metal level and metal oxide layer are set as peel ply between the transistorized layer, and make this metal oxide layer embrittlement by crystallization, and use solution or fluorinated gas such as NF
3, fluoridize halogen gas such as BrF
3, ClF
3Deng etching remove the part of metal level, the method for then in the metal oxide layer of embrittlement, physically peeling off.
In addition, by using in execution mode 2 paper made as the flexible substrate shown in the substrate 521, film, by fiber material etc. as substrate 1031, can seek to realize miniaturization, slimming, the lightweight of storage device.
Below, illustrate that with reference to Fig. 9 A for storage device be the data write activity that semiconductor device 700 carries out.Same with execution mode 2, at this electric effect is described, be typically the action when utilizing voltage to apply to carry out data writing.Note, write by the electrical characteristic that changes memory cell, yet the initial condition (not applying the state of electric effect) of memory cell is set as data " 0 ", and the setting state that will change electrical characteristic is data " 1 ".
With the situation of explanation to memory cell 701 data writings of the capable y row of x.When to memory cell 701 data writings " 1 ", at first by decoder 712 and 713 and selector 714 select storage units 701.Particularly, predetermined potential V22 is applied to the word line Wy that is connected with memory cell 701 by decoder 713.In addition, by decoder 712 and selector 714, the bit line Bx that is connected to memory cell 701 is connected to read/write circuits 715.Then, will write voltage V21 from read/write circuits 715 and output to bit line Bx.
Like this, make the thin-film transistor 721 that consists of memory cell become conducting state, and common electrode and bit line are electrically connected to memory element 722, then apply the voltage of general Vw (Vw=Vcom-V21).Vcom is that the common electrode in the memory element 722 is the current potential of the second conductive layer.By suitably selecting voltage Vw, physics or electrically change the accumulation layer that is arranged between this electrode layer carries out writing of data " 1 ".Particularly, accumulation layer is changed into following state to be got final product: reading under the operation voltage, the first conductive layer when data are the state of " 1 " and the resistance between the second conductive layer much smaller than data during for the state of " 0 " the first conductive layer and the resistance between the second conductive layer, also can make simply between the first conductive layer and the second conductive layer and produce short circuit.In addition, voltage Vw for example is set as more than the 5V and below the 15V, perhaps-15V above and-5V is following to be got final product.
Note, control unselected word line and unselected bit line so that data " 1 " be not written to these unselected word lines and memory cell that bit line is connected in.Particularly, unselected word line being applied the transistor that makes therewith the memory cell that connects becomes the current potential of cut-off state or gets final product with the current potential of Vcom same degree.
On the other hand, when data " 0 " when being written to memory cell 701, are not applied electric effect to memory cell 701, get final product.From circuit operation, for example same with the situation that writes " 1 ", by decoder 712 and 713 and selector 714 come select storage unit 701, yet make the output potential that outputs to bit line Bx from read/write circuits 715 become with the current potential of Vcom same degree or make the thin-film transistor 721 of memory cell become the current potential of cut-off state.As a result, memory element 722 is applied small voltage (for example ,-5V to 5V) or do not apply voltage, so electrical characteristic do not change, and realize writing of data " 0 ".
Below, the action when utilizing electric effect reading out data is described with reference to Fig. 9 B.By utilizing in the memory cell with data " 0 " and having between the memory cell of data " 1 ", the electrical characteristics of memory element 722 are different, carry out reading of data.For example, to be described as follows read method: for example, reading under the voltage, the resistance of memory element that formation is had the memory cell of data " 0 " becomes R0, and the resistance of memory element that formation is had the memory cell of data " 1 " becomes R1, reads by the difference of utilizing resistance.Note, satisfy R1＜＜R0.As the structure of the reading section of read/write circuits 715, for example can consider use resistive element 750 shown in Fig. 9 B and the circuit of differential amplifier 751.Resistive element has resistance value Rr, and satisfies R1＜Rr＜R0.Shown in Fig. 9 C, both can replace resistive element 750 with transistor 752, can replace differential amplifier 751 with clocked inverter 753 again.Certainly, circuit structure is not limited to Fig. 9 B and 9C.
When the memory cell 702 of the capable y row from x during reading out data, at first by decoder 712 and 713 and selector 714, come select storage unit 702.Particularly, by decoder 713, predetermined voltage V24 is applied to the word line Wy that is connected with memory cell 702, so that thin-film transistor 721 becomes conducting state.In addition, by decoder 712 and selector 714, the bit line Bx that will be connected with memory cell 702 is connected to the terminals P of read/write circuits 715.As a result, the current potential Vp of terminals P becomes following value, namely by resistive element 750 (resistance value Rr) and memory element 722 (resistance value R0 or R1) Vcom and V0 is carried out resistance and cuts apart the value determined.Thereby when memory cell 702 had data " 0 ", the current potential Vp0 of terminals P became Vp0=Vcom+ (V0-Vcom) * R0/ (R0+Rr).In addition, when memory cell 702 had data " 1 ", the current potential Vp1 of terminals P became Vp1=Vcom+ (V0-Vcom) * R1/ (R1+Rr).The result, can be in Fig. 9 B, by selecting Vref to get it between Vp0 and Vp1, and in Fig. 9 C, change point by selecting clocked inverter 753 is so that it is between Vp0 and Vp1, according to data " 0 "/" 1 ", read as output potential Vout output Low/High (perhaps High/Low).
For example, make differential amplifier 751 actions with Vdd=3V, be set as Vcom=0V, V0=3V, Vref=1.5V.Suppose to be set as R0/Rr=Rr/R1=9, and can not consider the conducting resistance (on resistance) of thin-film transistor 721, when the data of memory cell are " 0 ", become Vp0=2.7V and export High as Vout, when the data of memory cell are " 1 ", become Vp1=0.3V and export Low as Vout.Like this, can reading cells.
According to said method, utilize difference and the resistance of the resistance value of memory element 722 to cut apart, read according to magnitude of voltage.Certainly, read method is not limited to the method.For example, except the difference of utilizing resistance, can also utilize the difference of current value to read.In addition, when the electrical characteristic of memory cell has the different diode characteristic of between data " 0 " and data " 1 " threshold voltage, also can utilize the difference of threshold voltage to read.
In addition, both can thin-film transistor (TFT) be set in dielectric substrate, and memory element or memory element array are set thereon, can replace dielectric substrate by using the Semiconductor substrate such as Si or SOI substrate again, form field-effect transistor (FET) at substrate, and memory element or memory element array are set thereon.
Data to the semiconductor device shown in the present embodiment write not just once, can append (writing afterwards).On the other hand, because can not wipe data in the memory element that writes once, so can prevent from rewriting caused forgery.Moreover, because comprise can be easy and the memory element of the present invention made of high finished product rate ground, so can make at an easy rate the semiconductor device with superior Performance And Reliability.
Notice that present embodiment also can suitably make up with other execution modes and embodiment.Thus, the memory element that has of the semiconductor device shown in the present embodiment for example also can provide insulating barrier or semiconductor layer between at least one party in accumulation layer and the first conductive layer and the second conductive layer.
Execution mode 4
A configuration example of the semiconductor device with the storage device shown in the above-mentioned execution mode is described with reference to accompanying drawing in the present embodiment.
Semiconductor device shown in the present embodiment is characterised in that and can contactlessly reads and data writing.Data transfer mode roughly is divided into following three kinds of modes: with a pair of coil configuration for relatively and the electromagnetic coupled mode that communicates by mutual induction (mutual induction); The way of electromagnetic induction that communicates by induction field; And the wave mode by utilizing electric wave to communicate.Can use any mode in these modes.In addition, method to set up as the antenna that is used in the transmission of data has two kinds of methods: a kind of method is for arranging the method for antenna at the substrate that is provided with transistor and memory element, another kind method is for to arrange the terminal part at the substrate that is provided with transistor and memory element, and the antenna that will be arranged on another substrate is connected to the method that this portion of terminal assigns to arrange.
The structure of the semiconductor device shown in the present embodiment is described with reference to Figure 13.As shown in FIG. 13A, semiconductor device 20 of the present invention has the contactlessly function of swap data, and comprises power circuit 11; Clock generating circuit 12; Data demodulation/modulation circuit 13; Control the control circuit 14 of other circuit; Interface circuit 15; Memory circuit 16; Bus 17; And antenna 18.
In addition, shown in Figure 13 B, semiconductor device 20 of the present invention has the contactlessly function of swap data, and except power circuit 11; Clock generating circuit 12; Data demodulation/modulation circuit 13; Control the control circuit 14 of other circuit; Interface circuit 15; Memory circuit 16; Bus 17; And beyond the antenna 18, can also have CPU 1.
In addition, shown in Figure 13 C, semiconductor device 20 of the present invention has the contactlessly function of swap data, and except power circuit 11; Clock generating circuit 12; Data demodulation/modulation circuit 13; Control the control circuit 14 of other circuit; Interface circuit 15; Memory circuit 16; Bus 17; Antenna 18; And beyond the CPU 1, can also have the test section 2 that is consisted of by detecting element 3, testing circuit 4.
In addition, the data of memory element are not write just once, can carry out append (the writing afterwards) of data.On the other hand, because can not wipe data in the memory element that writes once, so can prevent from rewriting caused forgery.Thus, can make at an easy rate the semiconductor device with superior Performance And Reliability.
In addition, test section 2 can utilize physics or chemical gimmick detected temperatures, pressure, flow, light, magnetic, sound wave, acceleration, humidity, gas componant, liquid component and other characteristics.Notice that test section 2 comprises detecting element 3 and testing circuit 4.This detecting element 3 detects physical quantity or chemical quantity, and this testing circuit 4 converts physical quantity or the chemical quantity that this detecting element 3 detects to proper signal such as the signal of telecommunication etc.As detecting element 3, can use resistive element, capacity coupler, inductance coupling high element, photovoltaic cell, photo-electric conversion element, thermal electromotive force element, transistor, thermistor, diode etc.Notice that the quantity of test section 2 can for a plurality of, in the case, can detect a plurality of physical quantitys or chemical quantity simultaneously.
Note, refer to temperature, pressure, flow, light, magnetic, sound wave, acceleration, humidity etc. in the physical quantity of this explanation, chemical quantity refers to the chemical substance of liquid components such as the gas componant such as gas or ion etc. etc.As chemical quantity, in addition, also comprise such as the organic compound that is included in the specific biological substance (such as blood glucose value in the blood etc.) in blood, sweat, the urine etc.Particularly, when detecting chemical quantity, inevitable choice ground detects certain specific material, therefore in detecting element 3, provide in advance with the matter selective that will detect the material that reacts.For example, when the detection of biological material, preferably in detecting element 3, will with the selective biological material that will detect enzyme, antibody or the microbial cell etc. that react be fixed on macromolecule etc. and provide.
Below, a configuration example of expression semiconductor device wherein arranges antenna at the substrate that is provided with a plurality of elements and memory element in Figure 14.Notice that Figure 14 is the partial cross section figure of memory circuit 16 and antenna 18.
Figure 14 A illustrates the semiconductor device that comprises the memory circuit that forms with passive matrix.This semiconductor device comprises: be formed on the layer 1351 with transistor 1300 and 1301 on the substrate 1350; Be formed on the memory element part 1352 of the top with transistorized layer 1351 and the conductive layer 1353 that is used as antenna.
Note, although be illustrated in the top formation memory element part 1352 with transistorized layer 1351 and the situation that is used as the conductive layer 1353 of antenna here, yet the present invention is not limited to this structure, also can have transistorized layer 1351 below or in the layer identical with having transistorized layer 1351, provide memory element part 1352 or as the conductive layer 1353 of antenna.
The first conductive layer 110 in the memory element part 1352 is connected to the wiring that is connected with transistor 1301, and can by using material or the manufacture method identical with the memory element shown in the above-mentioned execution mode, form memory element part 1352.In addition, the insulating barrier 522 that covers the second conductive layer 112a and 112b and be used as diaphragm as the conductive layer 1353 ground formation of antenna.
Note, be provided with conductive layer 1353 as antenna at conductive layer 1360.Conductive layer 1,360 1310 is connected to transistor 1300 by connecting up.This wiring 1310 is by utilizing the operation formation identical with the first conductive layer 110 in the memory element part 1352.In addition, the conductive layer as antenna also can utilize the layer identical with 112b with the second conductive layer 112a to form.
For example, forming in the situation of the conductive layer that is used as antenna by the use silk screen print method, can provide this conductive layer by conductive paste optionally is printed onto desirable zone, in described conductive paste be that the conducting particles of a few nm to tens μ m is dissolved or dispersed in the organic resin with particle diameter.As conducting particles, can use any above metallic that is selected from silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and the titanium (Ti) etc., particulate or the dispersed nano particle of silver halide.In addition, as the organic resin that is included in the conductive paste, can use in the organic resin of the adhesive, solvent, dispersant and the lining material that are selected from as metallic one or more.Typically, can enumerate such as organic resins such as epoxy resin, silicone resins.In addition, when forming conductive layer, preferably after extruding conductive paste, carry out roasting.For example, in that the particulate take silver as its main component (for example, particle diameter is that 1nm is above and 100nm is following) is used as in the situation of conductive paste material, can conductive paste be solidified by under 150 ℃ to 300 ℃ temperature, carrying out roasting, obtain conductive layer.In addition, also can use with scolder or the lead-free solder particulate as main component, in the case, preferably using particle diameter is the following particulates of 20 μ m.Scolder or lead-free solder have the low advantage of cost.In addition, except above-mentioned material, pottery or ferrite etc. can also be applicable to antenna.
Can suitably select the transistor shown in the execution mode 3 etc. and be used in and be included in the transistor 1300,1301 that has in the transistorized layer 1351.
In addition, also can peel ply be set at substrate, form the conductive layer 1353 that has transistorized layer 1351, memory element part 1352 and be used as antenna at this peel ply, suitably use the stripping means shown in the execution mode 3 and peel off the conductive layer 1353 that has transistorized layer 1351, memory element part 1352 and be used as antenna, by using adhesion layer they are fitted on the substrate.As substrate, use in execution mode 2 paper made as the flexible substrate shown in the substrate 521, film, by fiber material, base film etc., can seek to realize miniaturization, slimming and the lightweight of storage device.
Figure 14 B represents to have an example of the semiconductor device of active array type memory circuit.Note, about Figure 14 B, the part that explanation is different from Figure 14 A.
Semiconductor device shown in Figure 14 B comprises: the layer 1351 with transistor 1300 and 1301 on substrate 1350; Have transistorized layer 1351 above memory element part 1356 and as the conductive layer 1353 of antenna.Note, although following situation is shown here: have transistorized layer 1351 above have memory element part 1356 and as the conductive layer 1353 of antenna, but the present invention is not limited to this structure, both can above or below the layer 1351 with transistor 1301, have memory element part 1356 and as the conductive layer 1353 of antenna, again can have transistorized layer 1351 below or have therewith memory element part 1356 in the identical layer and as the conductive layer 1353 of antenna.
In addition, also can peel ply be set at substrate, form the conductive layer 1353 that has transistorized layer 1351, memory element part 1356 and be used as antenna at this peel ply, suitably use the stripping means shown in the execution mode 3 and peel off the conductive layer 1353 that has transistorized layer 1351, memory element part 1356 and be used as antenna, by using adhesion layer they are fitted on the substrate.
Below, explanation comprises a configuration example of the semiconductor device of the first substrate and the second substrate with reference to Figure 15, this first substrate comprises terminal part and the memory element that has transistorized layer, is connected to antenna, and this second substrate is formed with the antenna that is connected to this terminal part.About Figure 15, the part different from Figure 14 is described.
Figure 15 A represents to have the semiconductor device of the storage device of passive matrix.Semiconductor device comprises: be formed on the layer 1351 with transistor 1300 and 1301 on the substrate 1350; Be formed on the memory element part 1352 of the top with transistorized layer 1351; Be connected to the terminal part of antenna; And be formed with substrate 1365 as the conductive layer 1357 of antenna.And, utilize the conducting particles 1359 that is included in the resin 1375 that conductive layer 1357 is electrically connected with the conductive layer 1360 that becomes splicing ear.Notice that the resin 1375 that has a tack by utilization will comprise the substrate 1350 with transistorized layer 1351 and memory element part 1352 etc. and the substrate 1365 that is provided with as the conductive layer 1357 of antenna fits together.
In addition, can use such as the electroconductive binder of silver paste, copper cream, carbon paste etc. or the method for use welding, will be connected with the conductive layer 1360 that becomes splicing ear as the conductive layer 1357 of antenna.Although this be illustrated in have transistorized layer 1351 above the situation of memory element part 1352 is set, but the invention is not restricted to this structure, also can have transistorized layer 1351 below or in identical therewith layer, memory element part 1352 is set.
Figure 15 B illustrates the semiconductor device of the storage device that is provided with active array type.Semiconductor device comprises: be formed on the layer 1351 with transistor 1300 and 1301 on the substrate 1350; Be formed on the memory element part 1356 of the top with transistorized layer 1351; Be connected to transistorized terminal part; And be formed with substrate 1365 as the conductive layer 1357 of antenna.And, utilize the conducting particles 1359 that is included in the resin 1375 that conductive layer 1357 is connected with the conductive layer 1360 that becomes splicing ear.Notice that the resin 1375 that has a tack by utilization will comprise the substrate with transistorized layer 1351 and memory element part 1356 etc. and the substrate 1365 that is provided with as the conductive layer 1357 of antenna fits together.
In addition, also can use such as the electroconductive binder of silver paste, copper cream, carbon paste etc. or use the method for welding, will comprise the substrate 1350 with transistorized layer 1351 and memory element part 1356 etc. and the substrate 1365 that is provided with as the conductive layer 1357 of antenna fits together.Although this be illustrated in have transistorized layer 1351 above the situation of memory element part 1352 is set, but the invention is not restricted to this structure, also can have transistorized layer 1351 below or in identical therewith layer, memory element part 1356 is set.
In addition, also can form peel ply at substrate, have transistorized layer 1351, memory element part 1352 or memory element part 1356 in this peel ply formation, by suitably using the stripping means shown in the execution mode 3, peel off and have transistorized layer 1351 and memory element part 1352,1356, then by using adhesion layer, will have transistorized layer 1351 and memory element part 1352,1356 and fit on the substrate.
Moreover, also can memory element part 1352 and 1356 be set at the substrate 1365 that is provided with as the conductive layer 1357 of antenna.That is, comprise the resin of conducting particles by utilization, will be formed with the first substrate with transistorized layer and be formed with memory element part and as the second substrate attaching of the conductive layer of antenna together.In addition, also can similarly arrange with the semiconductor device shown in Figure 14 A and the 14B and be connected to transistorized transducer.
Data to the semiconductor device shown in the present embodiment write not just once, can append (writing afterwards).On the other hand, because can not wipe data in the memory element that writes once, so can prevent from rewriting caused forgery.Moreover, because comprise can be easy and the memory element of the present invention made of high finished product rate ground, so can make at an easy rate the semiconductor device with superior Performance And Reliability.
Notice that present embodiment also can suitably make up with other execution modes and embodiment.Thus, the memory element that has of the semiconductor device shown in the present embodiment for example also can provide insulating barrier or semiconductor layer between at least one party in accumulation layer and the first conductive layer and the second conductive layer.
Execution mode 5
An example of the semiconductor device with memory element of the present invention is described with reference to accompanying drawing in the present embodiment.Figure 16 A represents the vertical view of the semiconductor device of present embodiment, the sectional view of the dotted line X-Y among Figure 16 B presentation graphs 16A.
Shown in Figure 16 A, be formed with memory element part 1404, circuit part 1421, the antenna 1431 with memory element at substrate 1400.Figure 16 A and Figure 16 B illustrate following state: be in manufacturing process midway, and be formed with memory element part, circuit part and antenna at the substrate 1400 that can anti-ly create conditions.Can be by similarly suitably selection material and manufacturing process make with above-mentioned execution mode.
Be provided with transistor 1441 and transistor 1442 across peel ply 1452, insulating barrier 1453 on substrate 1400, transistor 1441 and transistor 1442 are arranged on respectively in memory element part 1404 and the circuit part 1421.Be formed with insulating barrier 1461, insulating barrier 1454, insulating barrier 1455 at transistor 1441 and transistor 1442, and be formed with memory element 1443 at insulating barrier 1455.
The first conductive layer 110d is connected to the wiring layer of transistor 1441.On the other hand, the second conductive layer 112 is connected to the conductive layer 1457c that is layered on the wiring layer 1456a.In addition, stackedly on insulating barrier 1455 be provided with the antenna 1431 shown in conductive layer and Figure 16 A.In Figure 16 B, described conductive layer is conductive layer 1457a, conductive layer 1457b, conductive layer 1457e, conductive layer 1457f, and conductive layer 1457a and antenna 1431a, conductive layer 1457b and antenna 1431b and conductive layer 1457f and antenna 1431d are stacked respectively.Note, in the opening portion that reaches the wiring layer 1456b that is formed in the insulating barrier 1455, form conductive layer 1457e and antenna 1431c, and conductive layer 1457e is connected with wiring layer 1456b.By so, respectively antenna is electrically connected with memory element part 1404 and circuit part 1421.In addition, conductive layer 1457a, the conductive layer 1457b, conductive layer 1457e, the conductive layer 1457f that are respectively formed under antenna 1431a, antenna 1431b, antenna 1431c, the antenna 1431d also have the effect that improves the compactness between insulating barrier 1455 and the antenna.In the present embodiment, use polyimide film as insulating barrier 1455, use titanium film as conductive layer 1457a, conductive layer 1457b, conductive layer 1457e and conductive layer 1457f, and use the aluminium film as antenna 1431a, antenna 1431b, antenna 1431c and antenna 1431d.
Note, in order to connect respectively the first conductive layer 110d and transistor 1441, conductive layer 1457c and wiring layer 1456a, conductive layer 1457e and wiring layer 1456b, in insulating barrier 1455, form opening (being also referred to as contact hole).Work as enlarged openings, when increasing the contact area between the conductive layer, realize more low resistance.Therefore, in the present embodiment, set the size of opening, it is minimum that it sequentially is that the first conductive layer 110d is connected the opening that connects with transistor, secondly be the opening that conductive layer 1457c is connected with wiring layer 1456a, the opening that conductive layer 1457e is connected with wiring layer 1456b is maximum.In the present embodiment, the first conductive layer 110d is connected the opening that connects with transistor be 5 μ m * 5 μ m, the opening that conductive layer 1457c is connected with wiring layer 1456a is 50 μ m * 50 μ m, and the opening that conductive layer 1457e is connected with wiring layer 1456b is 500 μ m * 500 μ m.
In the present embodiment, make is more than the 500 μ m from insulating barrier 1460a to antenna 1431b apart from a, making the distance b from the end of the second conductive layer 112 to the end of insulating barrier 1460a is more than the 250 μ m, making the distance c from the end of the second conductive layer 112 to the end of insulating barrier 1460c is more than the 500 μ m, and making end from insulating barrier 1460c is more than the 250 μ m to antenna 1431c apart from d.Notice that partly forming has insulating barrier 1460c, transistor 1442 that the zone that is covered by insulating barrier 1460c and the zone that does not cover are also arranged in circuit part 1421.
By using this semiconductor device, from outside input part supply voltage, signal are directly inputted to the memory element part 1404, thereby data (being equivalent to information) can be written to memory element part 1404 or from memory element part 1404 reading out datas.
In addition, the structure of antenna both can be the structure that arranges with memory element with overlapping, again can for be arranged on the memory element part around nonoverlapping structure.In addition, when overlapping, its structure both can be whole overlapping structure, can be the overlapping structure of a part again.For example, when adopting antenna part and the partly overlapping structure of memory element, can reduce signal when being communicated by antenna with the action defective of the semiconductor device that causes of the impact of noise, the change of the caused electromotive force of electromagnetic induction etc.
In addition, as the signal transmission form in the semiconductor device of above-mentioned contactlessly input/output data, can use electromagnetic coupled mode, way of electromagnetic induction or microwave mode etc.Can consider that use suitably selects transmission means, and provide the suitableeest antenna according to transmission means.
Figure 17 A to 17D represents the example of the semiconductor device of shaped like chips.This semiconductor device comprises conductive layer 1502 and the memory element part 1503 as antenna that is formed on the substrate 1501.Note, in semiconductor device, except memory element, integrated circuit etc. can also be installed.
Under using the situation of microwave mode (such as UHF frequency band (860 to 960MHz frequency band), 2.45GHz frequency band etc.) as the signal transmission form in the semiconductor device, can consider the electromagnetic wavelength for signal transmission, suitably set as the shape of the conductive layer of antenna such as length etc.For example, can linear (for example, dipole antenna (with reference to Figure 17 A)), smooth shape (for example, plate aerial (with reference to Figure 17 B)) or banded (with reference to Figure 17 C, 17D) etc. will be formed as the conductive layer of antenna.In addition, the shape that is used as the conductive layer of antenna is not limited to linear, considers electromagnetic wavelength, can also be with curve shape, serpentine shape or the shape setting of making up these.
In addition, in applicable electromagnetic coupled mode or way of electromagnetic induction (for example, 13.56 the MHz frequency band) in the situation as the signal transmission form in the semiconductor device, owing to utilize the caused electromagnetic induction of variation of magnetic density, therefore, preferably will form as the conductive layer of antenna ring-type (for example, loop aerial) or helical form (for example, helical antenna).
In addition, contacting to earth in applicable electromagnetic coupled mode or way of electromagnetic induction and with metal connecting arranges in the situation of the semiconductor device that possesses antenna, and the magnetic material with magnetic permeability preferably is set between described semiconductor device and metal.Arrange in the situation of the semiconductor device possess antenna contacting to earth with metal connecting, be accompanied by the changes of magnetic field eddy current and flow through in the metal, and change by the demagnetizing field weakened field that this eddy current produces, thereby reduce communication distance.Therefore, by the material with magnetic permeability is set, can suppress the reduction of eddy current and the communication distance of metal between semiconductor device and metal.Note, as magnetic material, can use to have high magnetic permeability and few ferrite or the metallic film of high frequency loss.
In addition, when antenna is set, both can be on a substrate directly form semiconductor element such as transistor etc. and as the conductive layer of antenna, can on mutually different substrate, form respectively again semiconductor element and as the conductive layer of antenna, then with these two substrate attachings together so that semiconductor element and be electrically connected to each other as the conductive layer of antenna.
Data to the semiconductor device shown in the present embodiment write not just once, can append (writing afterwards).On the other hand, because can not wipe data in the memory element that writes once, so can prevent from rewriting caused forgery.Moreover, because comprise can be easy and the memory element of the present invention made of high finished product rate ground, so can make at an easy rate the semiconductor device with superior Performance And Reliability.
Notice that present embodiment also can suitably make up with other execution modes and embodiment.Thus, the memory element that has of the semiconductor device shown in the present embodiment for example also can provide insulating barrier or semiconductor layer between at least one party in accumulation layer and the first conductive layer and the second conductive layer.
According to the present invention, can form the semiconductor device as wireless chip.Having many uses of wireless chip is general, for example, can be by being installed in such as bank note, coin, security, bearer bond, certificate (driving license, resident's card etc., with reference to Figure 18 A), container for packing (wrapping paper, bottle etc., with reference to Figure 18 C), recording medium (DVD software, record-reproduce head etc., with reference to Figure 18 B), the vehicles (bicycle etc. are with reference to Figure 18 D), personal belongings (bag, glasses etc.), food, plant, animal, human body, clothes, daily necessities, such as commodity such as electronic equipments, use on the article such as the label of luggage (with reference to Figure 18 E and 18F).Electronic equipment refers to liquid crystal indicator, EL display unit, television equipment (also referred to as TV, TV receiver or television receiver) and portable phone etc.
Below, a mode of the electronic equipment that semiconductor device of the present invention is installed is described with reference to Figure 19.Be portable phone at the electronic equipment shown in this, it comprises: framework 1700 and 1706; Panel 1701; Shell 1702; Printed substrate 1703; Action button 1704; Battery 1705.Panel 1701 is installed in the shell 1702 in mode removably, and shell 1702 is by chimeric and be fixed to printed substrate 1703.According to the electronic equipment that panel 1701 is mounted, suitably change shape or the size of shell 1702.At printed substrate 1703 semiconductor device of a plurality of encapsulation is installed, and as one of them, can uses the semiconductor device with memory element of the present invention.Each that is installed in a plurality of semiconductor devices on the printed substrate 1703 has any function in controller, CPU (CPU:CentralProcessing Unit), memory, power circuit, audio frequency processing circuit, the transmission circuit etc.
As mentioned above, semiconductor device of the present invention has the feature of small-sized, slim and light weight.According to above-mentioned feature, can effectively utilize the framework 1700 of electronic equipment and the confined space of 1706 inside.Notice that framework 1700 and 1706 is for what represent take the face shaping of mobile phone as an example, the electronic equipment that relates to present embodiment can become according to its function or purposes and is various modes.
Notice that memory element of the present invention comprises the first conductive layer, accumulation layer, the second conductive layer, accumulation layer is by the first conductive layer and the second conductive layer clamping.In addition, the accumulation layer utilization is made of the nano particle that the electric conducting material that is covered by organic film forms, and forms by liquid droplet ejection method.Therefore, can easy and high finished product rate ground manufacturing memory element of the present invention.
Data to semiconductor device with this memory element do not write just once, can append (writing afterwards).On the other hand, because can not wipe data in the memory element that writes once, so can prevent from rewriting caused forgery.Therefore, can make at an easy rate the semiconductor device with superior Performance And Reliability.
Notice that present embodiment also can suitably make up with other execution modes and embodiment.Thus, the memory element that has of the semiconductor device shown in the present embodiment for example also can provide insulating barrier or semiconductor layer between at least one party in accumulation layer and the first conductive layer and the second conductive layer.
In the present embodiment, make the memory element that nano particle that its accumulation layer utilization forms by the electric conducting material that is covered by organic film consists of, and the structural change when for the data writing of the memory element of a configuration example of the present invention is shown.Memory element is the element of stacked the first conductive layer, accumulation layer, the second conductive layer in order on substrate, and with reference to Fig. 1 its manufacture method is described.Notice that it is square that the memory element of use is of a size of 5 μ m.
At first, form titanium film by sputtering method at substrate, obtain the first conductive layer 110.Notice that film thickness is 100nm.
Then, when using the heating plate heated substrate, forming thickness by liquid droplet ejection method is the accumulation layer 111 of 100nm.Use the solution that will be dispersed in by the Nano silver grain that organic film covers in water and the water-miscible organic solvent as blasting materials.Note, the silver concentration in the solution be approximately 22.5wt% (± 2.5wt%), the particle diameter of the nano particle that uses is as more than the 20nm and below the 30nm.In addition, use under 25 ℃ condition its viscosity to be approximately the blasting materials that 15Pas, surface tension are approximately 35mN/m.At first, in the heating plate heated substrate of 50 ℃ of uses, above-mentioned blasting materials is sprayed on the first conductive layer 110 as drop, then, be that drying was carried out in 80 ℃ of heating in 10 minutes with the Temperature Setting of heating plate, to form the accumulation layer 111 that is consisted of by the Nano silver grain that is covered by organic film.
Then, by utilizing the vapour deposition of resistance heating, forming thickness in accumulation layer 111 is the aluminium of 200nm, forms the second conductive layer 112.
Applying voltage by the memory element to acquisition like this writes.Figure 20 A is illustrated in the voltage-current characteristic of writing fashionable memory element.Note, adopt alive scanning (sweep) mode of executing that continuously changes as the applying method of voltage, and by using the limit value that resistor will flow through the electric current in the memory element to be set as 10mA.In Figure 20 A, near current value surge about 8.4V, this current value reaches the 10mA of limit value.That is to say, can learn to produce short circuit between the electrode, thereby can write memory element.
By again this memory element being applied voltage with scan mode, the voltage-current characteristic of the memory element after investigation writes.Figure 20 B represents its result.In Figure 20 B, the current value that flows through in memory element reaches the 10mA of limit value immediately after the applying of voltage.Thus, can confirm to have produced short circuit between the electrode, and correctly write.
Figure 21 to Figure 23 represents so to finish the SEM photo of the memory element that writes operation.Figure 21 represents the section along 1/2 part of film thickness direction of accumulation layer 111.Notice that when take this film thickness direction as the y direction, Figure 21 represents the xz plane.In addition, Figure 22 represents the cross section of memory element, and expression xy plane.In addition, Figure 23 also represents the cross section of memory element, and expression yz plane.
Can learn according to Figure 21 to Figure 23: formed conductive part 120 owing to write the welding of caused nano particle.In addition, can learn: the first conductive layer 110 and the second conductive layer 112 are electrically connected by above-mentioned conductive part 120 make the memory element short circuit, can realize writing.In addition, the shape of conductive part 120 is close to coniform.And, can learn: around conductive part 120, be formed with space 121, and its shape almost depends on the shape of conductive part 120.In addition, on the first conductive layer 110, can also observe the space in the part except space 121.And can learn: the second conductive layer 112 after writing does not deform.Therefore, for example form in the situation of other layers at the second conductive layer 112, the film that does not need to worry described other layers is peeled off etc.
In addition, by being exposed to according to the memory element that present embodiment is made in 85 ℃ the atmosphere 240 hours, to carry out reliability test.Even after 240 hours, this memory element can also correctly write.Thus, can know that memory element of the present invention has high reliability.
In addition, even after the heating plate that uses 150 ℃ heats 16 hours to the memory element of making according to present embodiment, this memory element does not also have short circuit, thereby can write by applying voltage.
Note, as mentioned above, accumulation layer 111 in the memory element of making according to present embodiment utilizes 80 ℃ heating plate to carry out drying after blasting materials is sprayed as drop, still, also shows the write diagnostics same with 80 ℃ situation at 140 ℃ of memory elements that carry out 10 minutes drying.
So, can easy and high finished product rate ground manufacturing memory element of the present invention.
Memory element of the present invention can not be wiped the data that write in the memory element once, so can prevent from rewriting caused forgery.So, the good memory element of manufacturing property and reliability at an easy rate.
Japanese patent application numbering 2007-024862 and 2007-024860 that this specification was accepted at Japan Office according on February 2nd, 2007 make, and described application content comprises in this manual.
Claims (12)
1. storage device comprises:
The first conductive layer;
The second conductive layer; And
Be clipped in the accumulation layer between described the first conductive layer and described the second conductive layer, wherein:
Described accumulation layer comprises first and second portion, described second portion comprises a plurality of nano particles, each of described a plurality of nano particles comprises the electric conducting material that is covered by organic film, described first comprises the current-carrying part that is contacted with described the first conductive layer and described the second conductive layer, the side of described first is centered on by described second portion, and between the side of described first and described second portion, form the space
Wherein said organic film comprises surfactant or forms the material of coordinate bond with described electric conducting material.
2. storage device comprises:
The first conductive layer;
The second conductive layer; And
Be clipped in the accumulation layer between described the first conductive layer and described the second conductive layer, wherein:
Described accumulation layer comprises first and second portion, described second portion comprises a plurality of nano particles, each of described a plurality of nano particles comprises the electric conducting material that is covered by organic film, described first comprises the current-carrying part that is contacted with described the first conductive layer and described the second conductive layer, the side of described first is centered on by described second portion, and between the side of described first and described second portion, form the space
Wherein said organic film comprises surfactant or forms the material of coordinate bond with described electric conducting material; And
Wherein said first is not contacted with described second portion.
According to claim 1 and 2 in the described storage device of any one, the particle diameter of wherein said nano particle is that 1nm is above and below the 200nm.
According to claim 1 and 2 in the described storage device of any one, wherein said organic film also comprises: reducing agent, adhesive or plasticizer.
According to claim 1 and 2 in the described storage device of any one, wherein said first is shaped as column or taper.
According to claim 1 and 2 in the described storage device of any one, also comprise layer, wherein this layer is clipped between described accumulation layer and described the first conductive layer or described the second conductive layer, and described layer be insulating barrier or semiconductor layer.
7. storage device comprises:
The first conductive layer;
The second conductive layer;
Be clipped in the accumulation layer between described the first conductive layer and described the second conductive layer; And
Transistor, this transistor are electrically connected to the memory element with described the first conductive layer, described the second conductive layer and described accumulation layer, wherein:
Described accumulation layer comprises first and second portion, described second portion comprises a plurality of nano particles, each of described a plurality of nano particles comprises the electric conducting material that is covered by organic film, described first comprises the current-carrying part that is contacted with described the first conductive layer and described the second conductive layer, the side of described first is centered on by described second portion, and between the side of described first and described second portion, form the space
Wherein said organic film comprises surfactant or forms the material of coordinate bond with described electric conducting material.
8. storage device comprises:
The first conductive layer;
The second conductive layer;
Be clipped in the accumulation layer between described the first conductive layer and described the second conductive layer; And
Transistor, this transistor are electrically connected to the memory element with described the first conductive layer, described the second conductive layer and described accumulation layer, wherein:
Described accumulation layer comprises first and second portion, described second portion comprises a plurality of nano particles, each of described a plurality of nano particles comprises the electric conducting material that is covered by organic film, described first comprises the current-carrying part that is contacted with described the first conductive layer and described the second conductive layer, the side of described first is centered on by described second portion, and between the side of described first and described second portion, form the space
Wherein said organic film comprises surfactant or forms the material of coordinate bond with described electric conducting material, and
Wherein said first is not contacted with described second portion.
9. the described storage device of any one according to claim 7 or in 8, the particle diameter of wherein said nano particle are that 1nm is above and below the 200nm.
10. the described storage device of any one according to claim 7 or in 8, wherein said organic film also comprises: reducing agent, adhesive or plasticizer.
11. the described storage device of any one according to claim 7 or in 8, wherein said first is shaped as column or taper.
12. the described storage device of any one according to claim 7 or in 8 also comprises layer, wherein this layer is clipped between described accumulation layer and described the first conductive layer or described the second conductive layer, and described layer is insulating barrier or semiconductor layer.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007-024862 | 2007-02-02 | ||
| JP2007024860 | 2007-02-02 | ||
| JP2007-024860 | 2007-02-02 | ||
| JP2007024862 | 2007-02-02 | ||
| JP2007024862 | 2007-02-02 | ||
| JP2007024860 | 2007-02-02 |
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| Publication Number | Publication Date |
|---|---|
| CN101237029A CN101237029A (en) | 2008-08-06 |
| CN101237029B true CN101237029B (en) | 2013-03-13 |
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| CN 200810005166 Expired - Fee Related CN101237029B (en) | 2007-02-02 | 2008-01-23 | Memory device |
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| JP (1) | JP2008211186A (en) |
| CN (1) | CN101237029B (en) |
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| US8415731B2 (en) | 2010-01-20 | 2013-04-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor storage device with integrated capacitor and having transistor overlapping sections |
| JP5670704B2 (en) | 2010-11-10 | 2015-02-18 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
| JP6053490B2 (en) * | 2011-12-23 | 2016-12-27 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| TWI678772B (en) * | 2017-04-28 | 2019-12-01 | 矽品精密工業股份有限公司 | Electronic package and method for fabricating the same |
| CN107170883B (en) * | 2017-07-12 | 2019-06-25 | 陕西科技大学 | A kind of flexibility TiO2The preparation method of resistance-variable storing device array |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834824A (en) * | 1994-02-08 | 1998-11-10 | Prolinx Labs Corporation | Use of conductive particles in a nonconductive body as an integrated circuit antifuse |
| JP2005116682A (en) * | 2003-10-06 | 2005-04-28 | Sharp Corp | Memory element and its fabricating process |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006352104A (en) * | 2005-05-20 | 2006-12-28 | Semiconductor Energy Lab Co Ltd | Semiconductor device, and manufacturing method thereof |
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2008
- 2008-01-17 JP JP2008007505A patent/JP2008211186A/en not_active Withdrawn
- 2008-01-23 CN CN 200810005166 patent/CN101237029B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834824A (en) * | 1994-02-08 | 1998-11-10 | Prolinx Labs Corporation | Use of conductive particles in a nonconductive body as an integrated circuit antifuse |
| JP2005116682A (en) * | 2003-10-06 | 2005-04-28 | Sharp Corp | Memory element and its fabricating process |
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| CN101237029A (en) | 2008-08-06 |
| JP2008211186A (en) | 2008-09-11 |
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