CN101414640A - 包含非易失性存储单元的集成电路及其制备方法 - Google Patents
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Abstract
本发明公开了一种包含非易失性存储单元的集成电路及其制备方法。该集成电路包含：半导体区，提供电荷以改变该非易失性存储单元的状态；电荷捕获介电层，捕获及储存电荷以定义该非易失性存储单元的状态；隧穿介电层，隔离该半导体区及该电荷捕获介电层；以及浮置栅极，储存电荷以定义该非易失性存储单元的状态，该浮置栅极的厚度至多为20纳米，该半导体区与该浮置栅极被该电荷捕获介电层及该隧穿介电层予以隔离。
Description
技术领域
本发明关于一种非易失性存储器，其通过储存电荷而定义其存储状态。
背景技术
非易失性存储器可具有用以储存电荷的电荷储存元件，而储存的电荷用以定义该非易失性存储单元的存储状态。电荷储存元件可为导电性(浮置栅极)或介电性(电荷捕获元件)。不论是导电性或介电性，电荷储存元件的电荷储存能力必须足够大，以允许快速地且可靠地读取其存储状态。
浮置栅极一般由掺杂多晶硅构成，且为了提供足够的电荷储存能力，其厚度大于或等于100纳米的多晶硅并非稀有。但是，当存储器的宽度减少时，浮置栅极的厚度/宽度的比值即增大，使得存储器的制备将较为困难，因此大厚度的多晶硅为降低存储器面积的巨大阻碍。此外，隧穿介电层的厚度必须相当的厚(就二氧化硅而言，一般厚度大于6纳米)，以提供优异的储存时间给浮置栅极上的高度移动性电荷。
相对地，电荷捕获存储器并不需要厚的隧穿介电层，而且电荷捕获元件(例如氮化硅层)的厚度一般均小于传统的浮置栅极的厚度。然而，电荷捕获元件的电荷储存能力一般均小于传统的浮置栅极的电荷储存能力。为了增加电荷储存能力(有时以＂电荷捕获密度＂为判断基准)，电荷储存元件的介电材料可内嵌纳米管芯，其材料可为钴、金或其它材料(参见Bhattacharyya等人的美国专利申请案号11/131,006；申请日为2005年5月17日；2006年11月23公开，公开号为2006/0261401)。另外，该电荷捕获元件可包含夹置于二层氮化硅层间的氧化硅层，以可提供额外的电荷捕获位置于该氧化硅层与该氮化硅的界面(参见美国专利US 6,936,884B2，公开于2005年8月30日)。
在浮置栅极存储器中，电荷储存能力可通过在浮置栅极内提供介电区而予以提升(参见Mouli等人的美国专利申请案号11/155,197；申请日为2005年6月17日；2006年12月21公开，公开号为2006/0286747)。因此，改善电荷储存元件是令人期待的。
发明内容
此一节概述本发明的部分技术特征。本发明的其它技术特征则叙述于下文中。本发明的保护范围由权利要求予以定义。
本发明提供一种非易失性存储器，其通过储存电荷而定义其存储状态。
在本发明的若干实施范例中，非易失性存储器的电荷储存元件包含电荷捕获介电层及导电层(即浮置栅极)。该浮置栅极作为电荷槽，用以提升该电荷捕获介电层的电荷储存能力。因此，该浮置栅极的厚度可予以降低，一般而言其厚度介于1至20纳米之间是适当的。
在若干实施范例中，该非易失性存储单元的50％至80％的电荷储存于该电荷捕获介电层，而其余的50％至20％的电荷储存于该浮置栅极。
电荷通过该电荷捕获介电层旁侧的隧穿介电层而隧穿进入或离开存储器。该浮置栅极与该隧穿介电层被该电荷捕获介电层予以隔离，因此该隧穿介电层的厚度可予以降低至与已知的电荷捕获存储器一样(例如3纳米的二氧化硅，其它材料也可使用)。
上文已经概略地叙述本发明的技术特征及优点，使下文的本发明详细描述得以获得优选了解。构成本发明的权利要求的其它技术特征及优点将描述于下文。本发明所属技术领域中具有通常知识者应可了解，下文揭示的概念与特定实施范例可作为基础而相当轻易地予以修改或设计其它结构或工艺而实现与本发明相同的目的。本发明所属技术领域中的普通技术人员应可了解，这类等同的结构并不脱离权利要求所提出的本发明的精神和范围。
附图说明
图1例示本发明若干实施范例的存储单元的剖示图；
图2例示适用于本发明若干实施范例的电压产生器的功能方块图；以及
图3及图4为本发明若干实施范例的能带图。
【主要元件符号说明】
110 半导体基板
120 P型沟道区
130 源极/漏极区域
140 源极/漏极区域
150 隧穿介电层
160 电荷捕获介电层
170 浮置栅极
180 阻挡介电层
190 控制栅极
210 电压产生器
具体实施方式
图1例示本发明若干实施范例的存储单元的垂直剖示图。该存储单元的有源区域为半导体区，其为半导体基板110的一部分。该半导体基板110可为单晶硅或其它适当材料。该有源区域包含P型沟道区120及N型源极/漏极区域130、140(P型与N型导电型态可予以颠倒)。为方便参考，该区域130可称为源极，而该区域140可称为漏极。事实上，在若干实施范例中，该区域130或140均可作为不同操作模式下的同一存储单元的源极或漏极。
隧穿介电层150直接形成于该有源区域上，其位于该沟道区120上方以及该源极/漏极区域130、140的局部或全部表面上。在若干实施范例中，该隧穿介电层150由二氧化硅、氮化硅、氧化钛、上述材料的组合或其它适当材料构成的膜层(参见前面提及的公开号为2006/0261401的美国专利申请案，该案的全文以引用的方式并入本文中)。一般而言，厚度为3纳米的二氧化硅层作为该隧穿介电层150是适当的，而较厚或较薄的膜层(例如1纳米至6纳米)也可使用作为该隧穿介电层150。
电荷捕获介电层160直接形成于该隧穿介电层150上。在若干实施例中，该电荷捕获介电层160为氮化硅层(可为富硅氮化硅层)，其厚度介于4纳米至14纳米之间，此一厚度并未予以限定。该电荷捕获介电层160的其它可能材料包含氮氧化硅、氮化钽、氧化钽、氮化铝及其它适当材料。在若干实施例中，当该存储器单元进行编程(program)操作后，该电荷捕获介电层160储存该存储器单元的全部电荷的50％至80％。
浮置栅极170直接形成于该电荷捕获介电层160，且由适当导电材料构成，例如掺杂多晶硅、金属或导电硅化金属。该浮置栅极170的厚度至多为20纳米，较薄的厚度(例如1纳米)也可使用。在若干实施例中，当该存储器单元进行编程操作后，该浮置栅极170储存20％至50％的电荷。
阻挡介电层180直接于该浮置栅极170上。在若干实施范例中，该阻挡介电层180由二氧化硅、氮化硅、氧化铝或其它介电材料构成。控制栅极190为形成于该阻挡介电层180上的导电层(金属层)。
电压产生器210(参见图2)可为传统的电路，其提供Vcg电压至该控制栅极190、Vsub电压至该半导体基板110、Vs电压至该源极区域130以及Vd电压至该漏极区域140。该电压产生器210与该存储单元可为同一集成电路的一部分。此外，该电压产生器210的一部分或全部可为该集成电路的外部电路。
该存储单元的操作方式可与已知的浮置栅极存储单元或电荷捕获存储单元一样。例如，提供Vcg电压(10伏特至13伏特)至该控制栅极190以及Vsub电压(接地电位)至该半导体基板110，即可编程(写入数据)该存储单元。该源极/漏极区域130、140被予以浮置。如此，该电荷捕获介电层160及该浮置栅极170将变成携带负电荷。一般而言，负电荷(例如导电带电子或/及价电带电子)从该沟道区120经由该隧穿介电层150进入该电荷捕获介电层160的导电带，其中部分电子被捕获于该电荷捕获介电层160之中，而其它电子则抵达该浮置栅极170。然而，除非本案权利要求的定义外，本发明并未取决于任何其它特定操作理论。
图3为本发明的存储单元实施编程操作的能带图，其假设该半导体基板110为单晶硅、该隧穿介电层150为二氧化硅、该电荷捕获介电层160为氮化硅、该浮置栅极170为掺杂多晶硅、该阻挡介电层180为氧化铝、该控制栅极190为金属钽。该半导体基板110的能带间隙的能量范围(即价电带与传导带间的能量)完全落入该隧穿介电层150的能带间隙的能量范围。该隧穿介电层150的能带间隙的能量范围包含该电荷捕获介电层160的能带间隙的能量范围。该电荷捕获介电层160的能带间隙的能量范围包含该浮置栅极170的能带间隙的能量范围。该浮置栅极170的能带间隙的能量范围落入该阻挡介电层180的能带间隙的能量范围。该阻挡介电层180的能带间隙的能量范围包含该控制栅极190的费米能级。
该存储单元可通过提供Vsub电压(8伏特至11伏特)至该半导体基板110，并保持该控制栅极190的电压为接地电位，以擦除该存储单元。该源极/漏极区域130、140被予以浮置。如此，该电荷捕获介电层160及该浮置栅极170的负电荷将被擦除，其可能通过传导带电子或/及价电带电子隧穿进入该沟道区120。图4为本发明的存储单元实施抹除操作的能带图，其使用的材料与图3所示者相同。
该存储单元可通过提供一电压差至该源极/漏极区域130、140，并驱动该控制栅极190至一电压位准，其介于该存储单元编程前(unprogrammed state)的阈值电压与编程后(programmed state)的阈值电压，便于读取该存储单元。
该存储单元可使用已知工艺予以制备。在若干实施例中，该半导体基板110内有P型井，该隧穿介电层150先形成于该P型井上，再依序形成该电荷捕获介电层160、该浮置栅极170、该阻挡介电层180及该控制栅极190。额外的膜层亦可能形成于该控制栅极190的上方。这些膜层的外形可在工艺的适当阶段予以定义。该源极/漏极区域130、140再根据需要予以掺杂。
本发明并不限于上文揭示的实施范例。在若干实施例中，该存储单元通过热电子注入机制进行编程(写入数据)操作。该存储单元可为多态存储单元(multi-state cell)，可能具有数个浮置栅极及多个电荷捕获元件。该存储单元可为存储阵列的一部分。浮置栅极存储器经常使用的许多存储阵列及存储单元亦可与本发明结合使用。特别而言，本发明也可使用非平面式存储单元、分裂栅存储单元、NAND、AND、NOR及其它存储阵列。
该隧穿介电层150可包含氮化硅、氮氧化硅或其它具有不同能带间隙的多层膜。该电荷捕获介电层160可由氮化硅以外的其它材料构成，且可内嵌纳米管芯或使用具有不同能带间隙的多层膜组合予以实现。本发明并不局限于平面式结构。例如，该浮置栅极、该电荷捕获介电层及该隧穿介电层可形成为在该半导体基板110内凸部(鳍板)的侧壁上的共形(conformal)膜层，或在该半导体基板110内沟槽的侧壁上的共形膜层。
本发明的若干实施范例包含集成电路，其包含非易失性存储单元。该非易失性存储单元包含半导体区，提供用以改变该非易失性存储单元的存储状态的电荷。该半导体区可为该半导体基板110、该沟道区120或该源极/漏极区域130、140。该集成电路亦可包含电荷捕获介电层(例如该电荷捕获介电层160)，其捕获及储存电荷以定义该非易失性存储单元的存储状态；隧穿介电层(例如该隧穿介电层150)，其隔离该半导体区及该电荷捕获介电层；浮置栅极，其储存电荷以定义该非易失性存储单元的状态，该浮置栅极的厚度至多为20纳米，该半导体区与该浮置栅极被该电荷捕获介电层及该隧穿介电层予以隔离。
在本发明的若干实施范例中，该电荷捕获介电层内嵌导体粒子或半导体粒子。
本发明的若干实施范例包含集成电路，其包含非易失性存储单元。该非易失性存储单元包含电荷捕获介电层，其储存电荷以定义该非易失性存储单元的存储状态；以及浮置栅极，其置放于该电荷捕获介电层上且接触该电荷捕获介电层。该非易失性存储单元具有存储状态由储存于该电荷捕获介电层及该浮置栅极的非零电荷予以定义，该非零电荷的至少50％储存于该电荷捕获介电层，且该非零电荷的至少20％储存于该浮置栅极。
本发明的技术内容及技术特点已揭示如上，然而本发明所属技术领域中的普通技术人员仍可能基于本发明的教导及公开的内容而作种种不背离本发明精神的替换及修饰。因此，本发明的保护范围应不限于实施范例所揭示者，而应包括各种不背离本发明的替换及修饰，并为权利要求所涵盖。
Claims (14)
1.一种包含非易失性存储单元的集成电路，包含：
半导体区，提供电荷以改变该非易失性存储单元的状态；
电荷捕获介电层，捕获及储存电荷以定义该非易失性存储单元的状态；
隧穿介电层，隔离该半导体区及该电荷捕获介电层；以及
浮置栅极，储存电荷以定义该非易失性存储单元的状态，该浮置栅极的厚度至多为20纳米，该半导体区与该浮置栅极被该电荷捕获介电层及该隧穿介电层予以隔离。
2.根据权利要求1的包含非易失性存储单元的集成电路，其中该非易失性存储单元具有由储存于该电荷捕获介电层及该浮置栅极的非零电荷予以定义的状态，该非零电荷的至少50％储存于该电荷捕获介电层，且该非零电荷的至少20％储存于该浮置栅极。
3.根据权利要求1的包含非易失性存储单元的集成电路，另包含：
控制栅极，该浮置栅极、该电荷捕获介电层及该隧穿介电层隔离该控制栅极与该半导体区；以及
阻挡介电层，隔离该浮置栅极与该控制栅极。
4.根据权利要求1的包含非易失性存储单元的集成电路，其中该半导体区包含该非易失性存储单元的沟道区及源/漏极区域。
5.根据权利要求1的包含非易失性存储单元的集成电路，其中该电荷捕获介电层内嵌导体粒子或半导体粒子。
6.根据权利要求1的包含非易失性存储单元的集成电路，其中该浮置栅极的厚度至少为1纳米。
7.一种包含非易失性存储单元的集成电路，包含：
电荷捕获介电层，储存电荷以定义该非易失性存储单元的状态；以及
浮置栅极，置放于该电荷捕获介电层上且接触该电荷捕获介电层；
其中该非易失性存储单元具有由储存于该电荷捕获介电层及该浮置栅极之一非零电荷予以定义的状态，该非零电荷的至少50％储存于该电荷捕获介电层，且该非零电荷的至少20％储存于该浮置栅极。
8.根据权利要求7的包含非易失性存储单元的集成电路，其另包含：
半导体区，提供电荷以改变该非易失性存储单元的状态；以及
隧穿介电层，隔离该半导体区及该电荷捕获介电层。
9.根据权利要求8的包含非易失性存储单元的集成电路，其另包含：
控制栅极，该浮置栅极、该电荷捕获介电层及该隧穿介电层隔离该控制栅极与该半导体区；以及
阻挡介电层，隔离该浮置栅极与该控制栅极。
10.一种集成电路的制备方法，该集成电路包含非易失性存储单元，该制备方法包含：
形成该非易失性存储单元的隧穿介电层于半导体区上，该半导体区提供该非易失性存储单元的一部分；
形成该非易失性存储单元的电荷捕获介电层于该隧穿介电层上；以及
形成该非易失性存储单元的浮置栅极于该电荷捕获介电层上，该浮置栅极的厚度至多为20纳米。
11.根据权利要求10的集成电路的制备方法，其中该非易失性存储单元具有由储存于该电荷捕获介电层及该浮置栅极的非零电荷予以定义的状态，该非零电荷的至少50％储存于该电荷捕获介电层，且该非零电荷的至少20％储存于该浮置栅极。
12.根据权利要求10的集成电路的制备方法，其另包含形成该非易失性存储单元的控制栅极于该浮置栅极的上方。
13.根据权利要求10的集成电路的制备方法，其中该浮置栅极的厚度至少为1纳米。
14.根据权利要求13的集成电路的制备方法，其中该浮置栅极由掺杂多晶硅构成。
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|---|---|
| TW200919737A (en) | 2009-05-01 |
| US20090096009A1 (en) | 2009-04-16 |
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