CN101447441A - 包含具有起伏的有源区的芯片的集成电路封装系统 - Google Patents

包含具有起伏的有源区的芯片的集成电路封装系统 Download PDF

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CN101447441A
CN101447441A CNA2008101616903A CN200810161690A CN101447441A CN 101447441 A CN101447441 A CN 101447441A CN A2008101616903 A CNA2008101616903 A CN A2008101616903A CN 200810161690 A CN200810161690 A CN 200810161690A CN 101447441 A CN101447441 A CN 101447441A
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chip
base portion
bonding wire
substrate
stacks
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CN101447441B (zh
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李相镐
朱钟郁
B·T·杜
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Stats Chippac Pte Ltd
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SMITH WAFER PACKAGE CORP
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Abstract

本发明公开一种集成电路封装方法，包括：提供基板；将基部芯片接合至该基板，该基部芯片具有起伏区，且该起伏区具有成形截面；以及，于该基部芯片的有源基部表面与该基板间连接键合引线，并令该键合引线延伸通过该起伏区的成形截面。

Description

包含具有起伏的有源区的芯片的集成电路封装系统
技术领域
本发明是关于集成电路封装系统，尤其是关于多芯片件的封装系统。
背景技术
于电子产业中，当如行动电话和摄录相机的产品变得越来越小时，集成电路(IC)或芯片封装件的微型化从而变得越来越重要。同时，更好的性能与较低成本已成新产品不可或缺的要素。
通常，许多个别的集成电路组件是建构于一晶片上，且成群组的集成电路组件则被分割成个别的集成电路芯片(die)。
一种用以将更多集成电路芯片放在单一封装件内的方法是在堆迭(stacking)的芯片间具有引线键合(wire bonding)的空间。该空间为以有机黏着剂的厚层或结合如：硅(Si)，陶瓷，或金属的无机材料制成的垫片(spacer)来产生。然而，堆迭的方法并不利于封装件的效能，因为这些有机黏着剂及/或无机垫片无法散热而令散热效能减低。当所堆迭的芯片数目增加，热阻将会更快速的增加。再者，此种堆迭芯片的制造成本高。
一般而言，半导体封装件根据其结构而分类成数种形式。具体来说，半导体封装件根据其组装结构而分类为成列形式(in-line type)和表面接置形式(surface mount type)。成列形式半导体封装件的例子包含双列直插式封装件(dual in-line package，DIP)和插针网格阵列封装技术(pin grid array，PGA)封装件。表面接置形式半导体封装件的例子包含四面扁平封装件(quad flat package，QFP)和球栅阵列(ball grid array，BGA)封装件。
堆迭芯片已遭遇到许多形式的打线问题。一个潜在的问题是于打线顶部芯片过程中键合引线下垂所导致的键合引线短路至该底部芯片。键合引线下垂所造成的电性短路的问题影响重大且频繁地发生于量产上。这个问题于将键合引线反向焊接到底部芯片的顶面时特别严重。
另一种形式的潜在问题是在焊接至顶部芯片时，因键合引线之线弧(wire loop)高度较预期为高，而导致键合引线短路至顶部芯片。这个问题在将键合引线以正常方式焊接到底部芯片的顶面时特别严重。
近来，为了于封装件板上获得较高的组件接置密度，相较于成列形式半导体封装件，表面接置形式半导体封装件的使用已增加。传统半导体封装件的尺寸远大于所使用的半导体芯片的尺寸。因此，此种半导体封装件无法满足该当前对于轻、薄、简单、微型化结构的需求。于是，传统的半导体封装件难以满足高度集成化微型化结构的需求。
此外，用以制造现有半导体封装件的工艺需要相对较繁复的步骤。因此，存在着通过简化制造方法来降低成本的需求。有鉴于对节省成本与改善效率的需求不断增加，找出这些问题的解答越来越重要。
如何克服上述该些问题已为人们长期探讨，但现有的开发并未公开或建议任何解决方案，所以，本领域技术人员已长期盼望有解决该些问题的方法。
发明内容
本发明包括一种集成电路封装方法，包括：提供基板；将基部芯片接合至该基板，该基部芯片具有具成形截面的起伏区；以及在该基部芯片的有源基部表面与该基板间连接键合引线，该键合引线延伸通过该起伏区的成形截面。
本发明某些实施例具有除以上所述之外或替代以上所述的，或者从以上可以显而易见得到的其它态样。通过通过阅读下列详细说明并参考附图后，本领域技术人员将明了这些态样。
附图说明
图1为本发明第一实施例的集成电路封装系统沿着图2中线1--1的剖面图；
图2为本发明第一实施例的集成电路封装系统的上视图；
图3为本发明第二实施例的集成电路封装系统类似图1的剖面图；
图4为本发明第三实施例的集成电路封装系统类似图1的剖面图；
图5为依据本发明第一实施例的芯片集聚(aggregate dice)的顶面视图；
图6为图示本发明第一实施例的制造步骤；
图7为图示本发明第一实施例的其它制造步骤；
图8为本发明第四实施例的集成电路封装系统类似图1的剖面图；
图9为本发明第五实施例的集成电路封装系统类似图1的剖面图；
图10为本发明第六实施例的集成电路封装系统类似图1的剖面图；
图11为本发明第七实施例的集成电路封装系统类似图1的剖面图；
图12为图示本发明第四实施例的制造步骤；
图13为图示图12中本发明第四实施例的其它制造步骤；
图14为图示图12中本发明第四实施例的其它制造步骤；
图15为图示图14中本发明第四实施例的其它制造步骤；
图16为本发明第八实施例的集成电路封装系统类似图1的剖面图；以及
图17为本发明实施例的集成电路封装系统的制造流程图。
具体实施方式
以下实施例为充分详细描述以使本领域技术人员可制造及使用本发明。同样，应当了解基于本申请所揭露内容可明了其它实施例，而且，系统、制造方法或机构上的变化可在不悖离本发明之范畴下进行。
以下说明将提供许多明确的细节，使能充分了解本发明。然而，本发明很显然地，能够在无这些明确细节下施行。为了避免模糊本发明，一些众所周知的电路、系统组态与制造方法步骤将不再详细叙述。同样地，用来例示本发明实施例的附图，为局部示意图而非按比例绘制，特别是某些图中的尺寸，是为使说明清晰而被特别放大。
揭露及描述在多个实施例中的某些共同特征，为清楚及容易说明、描述及理解，通常相似及相同的特征将以相同附图标记来描述。为便于描述，实施例是以第一实施例、第二实施例等予以编号，并非用以呈现其它意义或用以限定本发明。
为说明起见，本说明书中所用＂水平面(horizontal)″一词，定义成与本发明集成电路平行的平面或表面，而与其方向无关。＂垂直″一词，指与如前项所定义的水平面垂直的方向。其它用语诸如＂上″、＂以上(above)″、＂以下(below)″、＂底部″、＂顶部″、＂侧(如＂侧壁″)、＂较高″、＂较低″、＂上面的(upper)″、＂之上(over)″、以及＂之下(under)″，是相对于该水平面而定义出的。
“上(on)”一词是指在组件间有直接接触者。本说明书中所用＂处理(processing)″一词，是在形成所述构造时所需步骤，包括：材料的沉积、图案化、曝光、显影、蚀刻、清理(cleaning)以及/或是视所形成结构所需的材料的移除或修整。而“系统(system)”一词，是依照上下文意指本发明的方法及装置。
参阅图1，显示本发明第一实施例的集成电路封装系统100沿着图2中线1--1的剖面图。该集成电路封装系统100优选包含起伏区102、具有有源基部表面106且该有源基部表面106上具有焊垫108的基部芯片104、以及具有有源基板表面112的基板110。该起伏区102可通过自基部芯片104以及邻近该焊垫108的有源基部表面106移除材料而形成。
该起伏区102能包含垂直凹陷表面114，该垂直凹陷表面114平行于最接近该焊垫108的基部芯片侧面116。该起伏区102也可以包含水平凹陷表面118，该水平凹陷表面118平行于该有源基部表面106并且位在该基部芯片104的有源基部表面106下方。该垂直凹陷表面114与该水平凹陷表面118的交接处能形成用以指示出该水平凹陷表面118低于该有源基部表面106的预定深度，以及该垂直凹陷表面114到与其最接近的基部芯片104的基部芯片侧面116的预定距离的直线。
具有该垂直凹陷表面114与该水平凹陷表面118的起伏区102能形成具有矩形几何图形的成形截面。起伏区102的成形截面是不受限的且可形成任何几何图形。该几何图形可由下列组合而得：直角、曲线、有刻面(faceted)、有雕刻的(carved)、有纹理的(textured)或其它类似的表面形状。
该起伏区102的成形截面可根据需求如：可利用的制造方法、成本、应用、或类似的考量而选择。基部芯片104相对于有源基部表面106的一侧可利用基部接合层120，如：芯片黏着剂，而接合至该基板110的有源基板表面112。该基部芯片侧面116以及该起伏区102是位于该有源基板表面112上的基部接合层120的上方。焊垫108可利用键合引线124以提供基部芯片104的电路系统与基板110的有源基板表面112间的连结(connectivity)。键合引线124可利用针脚式焊接(stitch bonds)122连接至焊垫108。
具有针脚式焊接122的键合引线124可延伸远离该针脚式焊接122，且平行于该有源基部表面106，并行进于该起伏区102内侧或穿过该起伏区102内侧。可将键合引线124置放于与该垂直凹陷表面114以及该水平凹陷表面118的预定距离内。该基板110能由印刷电路板所构成，且该印刷电路板与其它部件，如：模组、连接器(connector)、显示指示器(display indicator)、开关(switches)、或通常与集成的下一阶段(next level of integration)相关连的类似部件等有连结。应注意，该基板110并不受限，且能够由封装基板所构成以形成与集成的下一阶段相连接的器件。
具有用以提供电性连接的电路系统的堆迭芯片126，利用堆迭接合层128，如堆迭黏着剂层板(laminate)或涂层(coating)，接置于该基部芯片104的有源基部表面106上。基部组件130由该基板110所构成，该基板110中部分有源基板表面112为该基部接合层120所覆盖。封装胶体132可选择地施用于该堆迭芯片126、键合引线124、以及邻近基部芯片104的有源基板表面112上，以提供对该集成电路封装系统100的保护。
如果在系统集成的下一阶段提供保护，如：在该堆迭芯片126以及基板110上其它邻近的下一阶段电路系统上具有金属密封盖，则可省略该封装胶体132。基部芯片组件134由接合于该基部组件130上的基部芯片104所构成，该基部组件130利用键合引线124以具有在该基部芯片104以及该基部组件130间的连结。
意外地发现，由于键合引线124的布线使长度减短且与该基部芯片104接近而造成电感效应减低，因而使该电路系统效能大大地改善。
参阅图2，显示本发明第一实施例集成电路封装系统100的上视图。显示了封装胶体132和有源基板表面112。该基板110中部份该有源基板表面112为该封装胶体132所覆盖。应注意，仅图示出邻近该封装胶体132的部分基板110。为清楚例示，其它可被接合至该基板110上的部件并未显示。
参阅图3，显示本发明第二实施例集成电路封装系统300类似图1的剖面图。该集成电路封装系统300优选包含起伏区102、具有有源基部表面106且有源基部表面106上具有焊垫108的基部芯片304、以及基部组件130。该起伏区102可通过自基部芯片304以及邻近该焊垫108的有源基部表面106移除材料而形成。
该起伏区102包含有角度的(angled)凹陷表面302，该凹陷表面302是由邻近焊垫108处至最接近焊垫108的基部芯片侧面116。该有角度的凹陷表面302可形成为以预定角度向最接近焊垫108的基部芯片侧面116倾斜。具有该有角度的凹陷表面302的该起伏区102，可形成具有三角几何图形的成形截面。基部芯片304相对于有源基部表面106的一侧可接合至该基部组件130的基部接合层120上。该基部芯片侧面116和该起伏区102是位于该基部组件130上方。
焊垫108可利用键合引线124以提供基部芯片304的电路系统与基部组件130间的连结。键合引线124可利用针脚式焊接122连接至焊垫108。键合引线124可行进于该起伏区102内侧或穿过该起伏区102内侧。可将键合引线124置放于与该有角度的凹陷表面302的预定距离内。该堆迭芯片126可利用堆迭接合层128而接置于该基部芯片304的有源基部表面106上方。该封装胶体132可选择地施用于该堆迭芯片126、键合引线124以及该基部组件130的周围部份上。
基部芯片组件306可由接合于该基部组件130上的基部芯片304所构成，该基部组件130利用键合引线124以具有在该基部芯片304以及该基部组件130间的连结。
参阅图4，显示本发明之第三实施例集成电路封装系统400类似图1的剖面图。该集成电路封装系统400优选包含起伏区102、具有有源基部表面106且有源基部表面106上具有焊垫108的基部芯片404、以及基部组件130。该起伏区102可通过自基部芯片404以及邻近该焊垫108的有源基部表面106移除材料而形成。
该起伏区102包含有角度的(angled)曲线凹陷表面(curved recesssurface)402，该有角度的曲线凹陷表面402是由邻近焊垫108处至最接近焊垫108的基部芯片侧面116。该有角度的曲线凹陷表面402可形成为以预定角度向最接近焊垫108的基部芯片侧面116倾斜。该有角度的曲线凹陷表面402包含具有凹进该基部芯片404中的表面，而形成一下陷的表面。具有该有角度的曲线凹陷表面402的起伏区102，可形成具有圆弧几何图形的成形截面。
基部芯片404相对于有源基部表面106的一侧可接合至该基部组件130的基部接合层120上。该基部芯片侧面116和该起伏区102是位于该基部组件130上方。焊垫108可利用键合引线124以提供基部芯片404的电路系统与基部组件130间的连结。键合引线124可利用针脚式焊接122连接至焊垫108。键合引线124可行进于该起伏区102内侧或穿过该起伏区102内侧。可将键合引线124置放于与该有角度的曲线凹陷表面402的预定距离内。该堆迭芯片126可利用堆迭接合层128而接置于该基部芯片404的有源基部表面106上方。
该封装胶体132可选择地施用于该堆迭芯片126、键合引线124以及该基部组件130的周围部份上。基部芯片组件406可由接合于该基部组件130上的基部芯片404所构成，该基部组件130利用键合引线124以具有在该基部芯片404以及该基部组件130间的连结。
参阅图5，显示依据本发明第一实施例的芯片集聚(aggregate dice)的顶面视图。显示未进行个别分割(individual singulation)的一部分晶片(wafer)502，该晶片502具有多套(replications)基部芯片104中的一个，曝露的焊垫108邻近于该有源基部表面106、切割道(saw streets)504、以及划线密封件(scribe seals)506。该划线密封件506于制造发展制造方法中对该晶片502的电路系统提供隔离与保护。
该切割道504可在分割制造方法中用以分离个别的芯片，可利用如：切割(sawing)、研磨(grinding)、激光、水刀(waterjet)、或任何其它可使用的分割方法。
图6显示本发明第一实施例的制造步骤，为该晶片502、该焊垫108、以及该切割道504的局部侧视图示。开口凹槽(open chamfers)602可通过使用阶段移除制造方法(step removal process)如：研磨、裁切(cutting)或等效之材料移除制造方法，自邻近焊垫108的切割道504以及切割道504下方移除部份或全部材料而形成。材料的移除为达到该有源基部表面106下方的预定深度。
参阅图7，图示第一实施例的其它制造步骤，为显示该晶片502、开口凹槽602、以及该基部芯片侧面116的局部图示。沿续该阶段移除制造方法，包含：利用分割制造方法如：切割、研磨、或等效的裁切制造方法来实施垂直晶片裁切702。这些垂直晶片裁切702垂直地横截该晶片502，使该晶片502随着每一个垂直晶片裁切702而被完全切割(complete singulation)。
图1中具有起伏区102的基部芯片104可通过对该晶片502的开口凹槽602进行切割制造方法而于该晶片502上形成。
参阅图8，显示本发明第四实施例的集成电路封装系统800类似图1的剖面图。该集成电路封装系统800优选包含基部芯片组件134、堆迭接合层128、以及堆迭芯片126，该堆迭芯片126具有位于堆迭芯片126后侧表面802(backside surface)附近的起伏区102。该起伏区102可包含平行于该堆迭芯片126的堆迭芯片侧面808的垂直凹陷表面804。
起伏区102也可包含平行于该后侧表面802的水平凹陷表面810。该垂直凹陷表面804与该水平凹陷表面810的交接处能形成用以指示出该水平凹陷表面810高于该后侧表面802的预定高度，以及该垂直凹陷表面804距离与其最接近的堆迭芯片侧面808的预定长度的直线。该垂直凹陷表面804距离该堆迭芯片侧面808的预定长度可大于该水平凹陷表面810高于该后侧表面802的预定高度。
具有该垂直凹陷表面804和该水平凹陷表面810的该起伏区102可形成具有矩形几何形状的成形截面。该基部芯片组件134的键合引线124连接该基部芯片104的有源基部表面106和该基板110，且可延伸通过该堆迭芯片126的起伏区102。可利用堆迭接合层128将该后侧表面802接合至该基部芯片组件134。封装胶体132可选择地施用于该堆迭芯片126以及该基部芯片组件134。
参阅图9，显示本发明第五实施例集成电路封装系统900类似于图1的剖面图。该集成电路封装系统900优选包含基部芯片组件306、堆迭接合层128、以及堆迭芯片126，该堆迭芯片126具有位于该堆迭芯片126后侧表面802附近的起伏区102。该后侧表面802可利用该堆迭接合层128而接合至该基部芯片组件306。
起伏区102可包含自邻近该堆迭芯片侧面808至该后侧表面802的有角度的凹陷表面902。该有角度的凹陷表面902可形成为以预定角度向该后侧表面802倾斜。具有该有角度的凹陷表面902的该起伏区102可形成具有三角几何形状的成形截面。封装胶体132可选择地施用于该堆迭芯片126和该基部芯片组件306上。
参阅图10，显示本发明第六实施例集成电路封装系统1000类似于图1的剖面图。该集成电路封装系统1000优选包含该基部芯片组件406、堆迭接合层128、以及堆迭芯片126，该堆迭芯片126具有位于该堆迭芯片126后侧表面802附近的起伏区102。该后侧表面802可利用该堆迭接合层128而接合至该基部芯片组件406。
该起伏区102可包含有角度的曲线凹陷表面1002，该有角度的曲线凹陷表面1002表面是由邻近该堆迭芯片侧面808到该后侧表面802。该有角度的曲线凹陷表面1002可形成为以预定角度向堆迭芯片侧面808倾斜。该有角度的曲线凹陷表面1002可包含包含具有凹进该堆迭芯片126中的表面，而形成一下陷的表面。具有该有角度的曲线凹陷表面1002的起伏区102，可形成具有圆弧几何图形的成形截面。
封装胶体132可选择地施用于该堆迭芯片126和该基部芯片组件406上。
参阅图11，显示本发明第七实施例集成电路封装系统1100类似于图1的剖面图。该集成电路封装系统1100优选包含基部芯片组件134、堆迭接合层128、以及堆迭芯片1102，该堆迭芯片1102具有位于该堆迭芯片1102后侧表面802附近的起伏区102。该后侧表面802可利用该堆迭接合层128而接合至该基部芯片组件134。该堆迭芯片1102中与该后侧表面802相对的表面的周长实质上大于该基部芯片组件134的基部芯片104的周长。
焊垫108、针脚式焊接122、基部芯片组件134的键合引线124、以及起伏区102不具有堆迭接合层128，并且，邻近基部芯片104的焊垫108的部分有源基部表面106实质上也不具有该堆迭接合层128。该起伏区102可包含平行于该堆迭芯片1102的堆迭芯片侧面808的垂直凹陷表面804。该起伏区102也可包含平行于该后侧表面802的水平凹陷表面810。
该垂直凹陷表面804与该水平凹陷表面810的交接处能形成用以指示出该水平凹陷表面810高于该后侧表面802的预定高度，以及该垂直凹陷表面804距离与其最接近的堆迭芯片侧面808的预定长度的直线。该垂直凹陷表面804距离该堆迭芯片侧面808的预定长度实质上大于该水平凹陷表面810高于该后侧表面802的预定高度。
具有该垂直凹陷表面804以及该水平凹陷表面810的起伏区102可形成具有矩形几何形状的成形截面。该起伏区102实质上不具有堆迭接合层128，且可延伸越过焊垫108、邻近焊垫108的有源基部表面106，针脚式焊接122、键合引线124、以及邻近键合引线124的部分基板110。该封装胶体132可选择地施用于该堆迭芯片1102和该基部芯片组件134上。
参阅图12，显示该第四实施例制造步骤的图式。所示为用于制造多套(multiple replications)图8的堆迭芯片126的晶片1202。晶片1202具有后侧表面802的一侧优选利用薄化制造方法(thinning process)如：研磨、磨光(sanding)、或类似的移除方法来进行材料移除。此处理步骤可减少该堆迭芯片126的厚度并且提供调整过的(conditioned)表面，以改善与图8中该堆迭接合层128接合时的黏着特性。
参阅图13，图示图12中第四实施例的其它制造步骤。该后侧表面802可沿着预定的平面直角座标1302利用后背切割制造方法(reardicing process)进行进一步处理。该后背切割制造方法优选包含宽局部贯穿切割(wide partial penetrating cut)以进入该晶片1202以及窄分离切割(narrow segregating cut)，使该晶片1202的切割沿着该预定的平面直角座标1302进行。
该后背切割制造方法可使图8中的堆迭芯片126与堆迭芯片126的起伏区102形成。延续该后背切割制造方法可使多套该堆迭芯片126被切割且可用于个别单元的组合与整合。
参阅图14，图示图12中第四实施例的其它制造步骤。已利用图12的薄化制造方法将材料移除的后侧表面802可以利用该堆迭接合层128进行层化(layered)。该堆迭接合层128可施用于该晶片1202的后侧表面802上。
参阅图15，图示图14中第四实施例的其它制造步骤。于该后侧表面802上的堆迭接合层128可利用后背切割制造方法沿着预定的平面直角座标1302而作进一步处理。该后背切割制造方法优选包含宽局部贯穿切割进入该晶片1202以及窄分离切割，使该晶片1202沿着该预定的平面直角座标1302而被切割。
该后背切割制造方法可使图8中的堆迭芯片126与该堆迭芯片126的起伏区102形成。该后背切割制造方法之延续可使多套具有该堆迭接合层128的堆迭芯片126被切割并且可用于个别单元的组合与整合。
参照图16，显示本发明第八实施例集成电路封装系统1600类似于图1的剖面图。该集成电路封装系统1600优选包含：具有基部芯片104的基部芯片组件134、堆迭芯片126、堆迭接合层128、绝缘层1602以及键合引线1604。该绝缘层1602可利用该堆迭接合层128而接合于该基部芯片组件134上。
该堆迭芯片126可接置于位在堆迭接合层128上方的绝缘层1602上，且该堆迭芯片126的电路系统可利用键合引线1604连接至该基部芯片组件134。封装胶体132可选择地施用于堆迭芯片126、键合引线1604、以及基部芯片组件134上。
参阅图17，显示用于制造本发明实施例集成电路封装系统之集成电路封装方法1700的流程图。该方法1700，包含：于方块1702，提供基板；于方块1704，将基部芯片接合至该基板，该基部芯片具有具成形截面的起伏区；以及，方块1706，在该基部芯片的有源基部表面与该基板间连接键合引线，该键合引线延伸通过该起伏区的成形截面。
更详细地说，根据本发明实施例，提供集成电路封装系统100的方法与装置之系统，是以下列方式实施：
1.提供具有源基板表面的基板。
2.将基部芯片接合至该基板，该基部芯片具有起伏区，该起伏区具有在其周围的成形截面。
3.在该基部芯片的有源基部表面与该基板间连接键合引线，该键合引线中的至少一者延伸通过该起伏区的成形截面。
因此，可发现本发明集成电路封装系统方法与装置提供了重要且且迄今为止尚未为人所知或使用的解决方法、性能、以及功能上的优点。
该所得的制造方法与架构为直接、经济、不复杂、多用途且有效率，且能适用于习知技艺而容易应用以有效且经济地制造大型芯片集成电路封装件装置(large die IC package device)。
参照特定的最佳实施例，本说明书已经对本发明进行揭示。应明了，许多的改变、修饰与变化对熟悉本领域者而言，以上的说明将使其变得很明显。因此，所有该些改变、修饰与变化皆涵盖于以下的申请专利范围内。本说明书中所揭示的内容或显示的附图是用于解释本发明，而非用于限制本发明的范畴。

Claims (10)

1、一种集成电路封装方法，包括：
提供基板；
将基部芯片接合至该基板，该基部芯片具有具成形截面的起伏区；以及
在该基部芯片的有源基部表面与该基板间连接键合引线，该键合引线延伸通过该起伏区的该成形截面。
2、如权利要求1所述的方法，其中，连接该键合引线包括在该基部芯片的有源基部表面与该基板间的针脚式焊接，该键合引线延伸通过该起伏区的该成形截面。
3、如权利要求1所述的方法，其中，将该基部芯片接合至该基板，该基部芯片具有具该成形截面的该起伏区，具该成形截面的该起伏区是成形为矩形、三角形或曲线。
4、如权利要求1所述的方法，进一步包括：
在该基部芯片上接置堆迭芯片；以及
在该堆迭芯片与该基部芯片间接合堆迭接合层，该堆迭接合层覆盖一部份该键合引线。
5、如权利要求1所述的方法，进一步包括在该基部芯片上接置堆迭芯片，该堆迭芯片具有具成形截面的起伏区延伸越过该键合引线与该基部芯片的该有源基部表面的连接。
6、一种集成电路封装系统，包括：
基板；
基部芯片，接合至该基板，该基部芯片具有具成形截面的起伏区；
以及
键合引线，连接在该基部芯片的有源基部表面与该基板间，该键合引线延伸通过该起伏区的该成形截面。
7、如权利要求6所述的系统，其中，该键合引线包括连接在该基部芯片的该有源基部表面与该基板间的针脚式焊接，该键合引线延伸通过该起伏区的该成形截面。
8、如权利要求6所述的系统，其中该基部芯片接合至该基板，该基部芯片具有具该成形截面的该起伏区，具该成形截面的该起伏区是成形为矩形、三角形或曲线。
9、如权利要求6所述的系统，进一步包括：
堆迭芯片，接置在该基部芯片上；以及
堆迭接合层，将该堆迭芯片与该基部芯片接合，该堆迭接合层覆盖一部份该键合引线。
10、如权利要求6所述的系统，进一步包括：堆迭芯片，接置在该基部芯片上，该堆迭芯片具有具成形截面的起伏区延伸越过该键合引线与该基部芯片的该有源基部表面的连接。
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