CN101454885A - 形成焊料连接的方法及其结构 - Google Patents

形成焊料连接的方法及其结构 Download PDF

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Publication number
CN101454885A
CN101454885A CNA2007800192071A CN200780019207A CN101454885A CN 101454885 A CN101454885 A CN 101454885A CN A2007800192071 A CNA2007800192071 A CN A2007800192071A CN 200780019207 A CN200780019207 A CN 200780019207A CN 101454885 A CN101454885 A CN 101454885A
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China
Prior art keywords
metal
containing layer
layer
resist
solder material
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T·H·道本皮克
J·P·冈比诺
C·D·穆西
沃尔夫冈·索特
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International Business Machines Corp
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International Business Machines Corp
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Publication of CN101454885A publication Critical patent/CN101454885A/zh
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Abstract

在第一方面中，一种方法包括淀积第一含金属层(16)到沟槽结构中，该第一含金属层(16)接触半导体结构(10)的金属化区域(12)。该方法进一步包括在抗蚀剂中对第一含金属层(16)图案化至少一个开口。该开口应该和沟槽结构对准。在至少一个开口内至少形成衬垫含金属层(20)(优选地通过电镀处理)。随后蚀刻该抗蚀剂(18)和抗蚀剂(18)下面的第一金属层(16)(在实施例中，以第二金属层(20)作为掩模)。该方法包括在蚀刻处理之后将焊料材料(22)流到沟槽中和流到衬垫含金属层(20)上。该结构是受控熔塌芯片连接(C4)结构，其包括在抗蚀剂图案中形成的至少一个电镀金属层以形成至少一个球限制冶金层。该结构进一步包括没有底切的下金属层。

Description

形成焊料连接的方法及其结构
技术领域
[0001]本发明涉及一种在半导体器件上形成焊料连接的方法，且更加具体地，涉及一种形成焊料连接同时限制或者消除在下面的一个或多个层上的底切的方法和产生装置。
背景技术
[0002]半导体器件上的焊料连接包括包含几种金属的材料，该焊料连接包括焊料块本身，该焊料块通常包括基于锡或铅的低熔点金属合金或者金属混合物。较不明显的是在焊料块的下面的材料，该材料桥接焊料块和第一金属化接触之间的导电连接，其中该第一金属化接触形成在半导体器件的流水线处理的后段。这些块下材料(UBM)也被称为球限制冶金(BLM)层，因为它们形成了焊料块的基础且仅在其中存在球限制金属的区域保持焊料材料。
[0003]在一个现有方法中，在使用C4(受控熔塌芯片连接)作为蚀刻掩模进行C4喷镀之后，对溅射的BLM膜的难熔叠层进行湿蚀刻。对于无铅(Pb-free)或者少铅(Pb-reduced)的工艺，BLM的顶层典型地包括铜或者铜和例如镍或者镍合金的另外的阻挡膜，该阻挡层典型地是电镀的。在顶层是铜的情况下，铜与基于锡的焊料材料反应以形成金属间化合的CuSn阻挡层，其对于无铅或少铅C4块的可靠性来说是重要的。在铜和阻挡材料(例如镍或者Nix)的情况下，阻挡层防止Sn和Cu的相互扩散，且同时Cu用作导电层以增强镍的电镀。
[0004]当对铜和下面的膜进行湿蚀刻时(使用焊料块和/或镍阻挡层作为蚀刻掩模)，出现块下腐蚀或者底切的问题。该湿蚀刻底切是可变的，且具有在BLM和C4之间的接合分界面处减少BLM占用面积的效果。该块下腐蚀能够达到用于金属接触的横向损失空间的多达10μm的尺寸。这由此降低了块连接的潜在的完整性。
[0005]随着半导体器件变得更小，也需要更小的焊料连接。在此情况下，随着C4间距变得更小，由于每个边缘相对一致的底切对最终总体C4结构的完整性具有更大的威胁，因此关于最终C4结构的可靠性和实用性工艺控制变得更为关键。并且，应当理解随着半导体器件变得更小，到达了其中10μm的底切是不可接受的且其将会显著地恶化器件性能的程度。
[0007]因此，在现有技术中存在克服上述不足和限制的需要。
发明内容
[0008]在本发明的第一方面中，一种方法包括，淀积第一含金属层到沟槽结构中，该沟槽结构接触半导体结构的金属化区域。该方法进一步包括在抗蚀剂中对第一含金属层图案化至少一个开口。该开口应该和沟槽结构对准。在至少一个开口内至少形成衬垫含金属层(padmetal containing layer)(优选地通过电镀处理)。蚀刻该抗蚀剂和抗蚀剂下面的第一金属层(在实施例中，利用第二金属层作为掩模)。该方法包括在蚀刻处理之后将焊料材料流入沟槽内并流到衬垫含金属层上。
[0009]在另外的实施例中，该方法包括在第一金属层下形成钝化层并在钝化区域中形成开口以形成沟槽结构。该钝化层包括氮化硅、二氧化硅和聚酰亚胺中的至少其中之一。第一含金属层包括钽、钛和钛钨合金中的至少其中之一。可在提供焊料之后进行该蚀刻。通过物理气相淀积来淀积第一含金属层。
[0010]第二含金属层包括铜，且可以通过电镀来淀积该第二含金属层。衬垫含金属层的厚度在大约1μm到大约2μm之间。通过抗蚀剂图案来控制第二金属层的纵向尺寸。在其中在铜之上使用Ni-BLM衬垫/阻挡顶层的情况下，通过电镀来淀积铜和阻挡层。
[0011]如果使用焊料镀处理，在蚀刻抗蚀剂之前将焊料材料放置在沟槽结构中。在这种情况下，在剥离去除抗蚀剂之后，焊料材料用作蚀刻第一含金属层的掩模。然而，如果使用物理焊料转移处理，在焊料转移之前剥去抗蚀剂掩模。在该焊料转移情况中，首先剥去抗蚀剂掩模并随后使用Cu或者Cu+阻挡层作为掩模对Cu之下的BLM层进行湿蚀刻或者RIE′d(反应性离子蚀刻)。该焊料材料包括无铅的含锡材料或者铅焊料。
[0012]BLM基层的蚀刻优选地包括反应性离子蚀刻且通过衬垫含金属层的纵向尺寸确定在流动之后的焊料连接的纵向尺寸。在蚀刻之后，剩余的第一含金属层和衬垫含金属层形成球限制冶金(BLM)层。
[0013]焊料的流动包括由包括焊料材料的铸模形成的大量的焊料连接。衬垫含金属层在蚀刻期间用作掩模。蚀刻是保持第一含金属层的尺寸完整性由此防止底切的干蚀刻。
附图说明
[0015]图1a到1f示出了根据本发明的实施例的工艺步骤；且
[0016]图1c′和1d′示出了根据本发明的可选的工艺步骤。
具体实施方式
[0017]本发明涉及用于在半导体器件上形成焊料连接的方法。在实施例中，即使没有完全地消除，本发明的方法也减小了焊料连接的下层的腐蚀或者底切。本发明还允许焊料块的尺寸完整性，即通过在下金属层(多个)的尺寸来控制焊料连接的大小。在实施例中，该方法包括应用抗蚀剂图案以限制块下金属化层的各部分的位置，尺寸与形状。
[0018]在实施例中，本发明对于少铅或无铅C4(受控熔塌芯片连接)制造实现了溅射和电镀BLM的组合。在实施例中，对下TiW/Ti(或等效的)阻挡层进行溅射淀积(PVD)；然而，在抗蚀剂膜上通过旋转电镀较厚的铜顶层(或者铜加阻挡层；大约1-3μm)。在实施例中，TiW/Ti阻挡层是大约0.6μm厚，其在电方面足以用于C4喷镀处理。铜的电镀导致铜被置于它的最终位置以使其在度量方面符合设计或者期望的尺寸。在抗蚀剂剥离之后，优选地利用镀Cu的衬垫或者全C4结构(在C4NP的情况下铸模转移之后)作为掩模对下面的BLM膜进行RIE图案化。在该方法中，相比现有技术，能够以更高的图案化完整度限定包括C4衬垫结构的每个BLM层。如果在铜层的顶部使用，上述方法对于镍类型的阻挡层也是适用的。在抗蚀剂剥离之后，随后优选地利用镀Cu的衬垫或者扩散阻挡衬垫或者全C4结构(在铸模转移之后)，对下面的BLM膜进行RIE图案化。这随后转化为关于结构的最终可靠性的改进的可加工性和降低的风险。
[0019]图1a示出了根据本发明的工艺步骤。该工艺步骤包括在焊接处理之前，在半导体结构10上形成金属化层12。该层10主要包括非导电材料，例如二氧化硅或者氮化硅且能够具有任何期望的厚度。该金属化层12包括任何含金属的材料或者纯金属，例如但不限于铜或铝。金属化层12还代表了半导体结构上焊料连接的期望的位置；但是，应当理解本发明考虑了焊料连接的其他位置。例如，第一金属化层12可以是通向层10内的半导体栅极的沟槽。虽然未示出，可以在层12的下面提供衬里(liner)。
[0020]以现有方式图案化钝化材料14以形成沟槽，暴露一部分的下层12。在实施例中，钝化材料14是电钝性的或非导电的，且可以包括几个层，例如氮化硅层或者二氧化硅层，但是优选地是聚酰亚胺层。但是应该理解，本发明也考虑了其他非导电或者钝化材料。
[0021]图1b示出了根据本发明的进一步的工艺步骤。在这些工艺步骤中，在层12和层10之上形成含金属层16。随后将抗蚀剂18施加于层16之上并图案化以形成开口。能够以在现有技术中已知的任何方法应用该含金属层16，例如，通过物理气相淀积(PVD)或者溅射。在实施例中，该含金属层16用作用于电镀的导电基底，且可以具有本领域技术人员已知的任意适当的厚度，且仅在尺寸上受限以保证精确的电镀处理。
[0022]在实施例中，含金属层16的厚度能够在大约0.1和1.0μm之间，优选地在大约0.2和0.8μm之间，且最优选地大约0.6μm。同时，含金属层16的材料能够改变且可以包括钛或者钨钛合金、其混合物或者任何等效物。此外，含金属层16能够包括任何金属层以改进连接的物理和化学特性。例如，该含金属层16能够包括氮化钽。
[0023]抗蚀剂层18包括抗蚀剂材料且能够通过本领域技术人员的任何已知的方法应用该抗蚀剂层18。该抗蚀剂层18能够具有任何期望的图案并形成用于完成的焊料连接的模板。因此，抗蚀剂层18确定了焊料连接的球限制层的尺寸、位置和形状。
[0024]本发明考虑了抗蚀剂对含金属层16能够具有若干开口，由此制备同时具有任意数目的焊料连接的器件。抗蚀剂层18能够具有任何厚度且仅被层的设置于开口内的厚度所限制。在本发明的范围内，抗蚀剂层18的厚度能够在1.0和5.0μm之间；但是，本发明也考虑了其他厚度。
[0025]图1c示出了根据本发明的进一步的工艺步骤。在这些工艺步骤中，在层16上在抗蚀剂层18中形成的开口内设置含金属层20。含金属层20可以具有用作块下金属化材料或者其混合物的任何材料。在实施例中，含金属层20包括铜；但是本发明考虑了其他材料。在实施例中，通过电镀提供含金属层20，例如，这允许仅在暴露含金属层16的位置处进行受控的同质生长。
[0026]在实施例中，含金属层20用作用于焊料的衬垫以及用于后续蚀刻步骤的掩模。该含金属层20能够生长到任何厚度，且在实施例中，在大约0.5和5μm厚之间，优选地在大约0.5和3μm厚之间，且最优选地在大约2和3μm厚之间。
[0027]图1d示出了根据本发明的附加工艺步骤。在这些工艺步骤中，通过湿蚀刻处理或者干蚀刻处理去除抗蚀剂层18和下面的含金属层16的一部分(没有被含金属层20覆盖的)。在该处理中，层20用作掩模。优选地，如果使用例如反应性离子蚀刻的各向异性方法，则保持了含金属层20和含金属层16的尺寸完整性；也就是说，基本上没有底切或者腐蚀。这保持了焊料连接的完整性，特别是对于较小尺寸的器件。如果使用例如湿蚀刻的各向同性方法，则可能出现含金属层16和20中的侧向腐蚀，但与现有技术中先前使用的方法相比其程度显著地减小。
[0028]图1e示出根据本发明的放置了焊料材料的块下金属化层16和20。该焊料材料可以具有任何适当的材料，包括，例如无铅(Pbf)或者少铅(Pbr)的焊料材料。此外，能够通过任何方法应用焊料材料，优选的方法是C4方法(受控熔塌芯片连接)。
[0029]在C4处理中，制备的焊料片适配于该块下金属化元件且被放置在含金属层20上。该结构随后经历回流。通过使用本发明的方法，焊料块在其基底处具有块下材料的形状和尺寸，且进一步熔化为其典型的凹面块形状。任何过量的焊料材料流到该结构外，且能够被容易地去除。图1f示出了基于块下金属化，即，含金属层20的制备而具有尺寸完整性的完成的焊料块连接。
[0030]可选的，工艺的顺序能够改变且能够在去除抗蚀剂之前或者蚀刻层16之前附加焊料材料。该处理由图1c′和1d′(其分别代替图1c和1d)示出。通过举例的方式，在图1c′中，在电镀之后将焊料材料22置于器件上且在图1d′中，在去除抗蚀剂18之后并在蚀刻之前放置材料22。在本实施例中，如果以精确的尺寸制备焊料材料，则层22用作掩模且保护含金属层16和20不受由于蚀刻方法带来的任何不利损害。在回流处理期间减小和消除了在蚀刻期间对材料22发生的损害。
[0031]另外，本发明可应用于在相同半导体器件或者晶片上同时制造一系列焊料块。在这种实施例中，创建抗蚀剂图案18以在整个器件或晶片表面的全部期望的焊料块位置提供多个开口。在电镀器件或晶片之后的任意时刻，例如使用C4处理应用焊料材料。
[0032]虽然通过本实施例描述了本发明，但本领域技术人员将认识到能够以在所附的权利要求的精神和范围内的修改实现本发明。例如，本发明能够容易地应用到块状衬底。

Claims (35)

1.一种方法，包括：
淀积第一含金属层到沟槽结构中，该第一含金属层接触半导体结构的金属化区域；
在抗蚀剂中对第一含金属层图案化至少一个开口，该开口大体上与所述沟槽结构对准；
在至少一个开口内至少形成衬垫含金属层或者双层；
剥离抗蚀剂并蚀刻抗蚀剂下的第一金属层；和
将焊料材料流入所述沟槽结构内并流到衬垫含金属层上。
2.根据权利要求1的方法，进一步包括在第一金属层下形成钝化层并在钝化层中形成开口以形成所述沟槽结构。
3.根据权利要求2的方法，其中，该钝化层包括氮化硅、二氧化硅和聚酰亚胺中的至少其中之一。
4.根据权利要求1的方法，其中，该第一含金属层包括包含钛，钨，钛钨合金的难熔金属类或者它们的合金中的至少其中之一。
5.根据权利要求1的方法，其中，在剥离抗蚀剂之后提供该焊料材料。
6.根据权利要求1的方法，其中，通过物理气相淀积来淀积该第一含金属层。
7.根据权利要求1的方法，其中，该衬垫含金属层包括铜或者具有扩散阻挡金属的铜，该扩散阻挡金属包括镍或者镍的合金。
8.根据权利要求1的方法，其中，通过电镀淀积该衬垫含金属层或者双层。
9.根据权利要求1的方法，其中，该衬垫含金属层的厚度为大约2到大约3μm之间。
10.根据权利要求1的方法，其中，通过抗蚀剂图案化来控制衬垫金属层的纵向尺寸。
11.根据权利要求1的方法，其中，在抗蚀剂的蚀刻之前将焊料材料置于沟槽内。
12.根据权利要求11的方法，其中，该焊料材料用作在蚀刻抗蚀剂之后蚀刻第一含金属层的掩模。
13.根据权利要求1的方法，其中，该焊料材料包括无铅的含锡材料或者少铅的含锡材料。
14.根据权利要求1的方法，其中，该蚀刻包括反应性离子蚀刻。
15.根据权利要求10的方法，其中，通过衬垫含金属层或者开口的纵向尺寸确定在流动之后的焊料连接的纵向尺寸。
16.根据权利要求1的方法，其中，在蚀刻之后，剩余的第一含金属层和衬垫含金属层形成了球限制冶金(BLM)层。
17.根据权利要求1的方法，其中，该焊料的流动包括由包括焊料材料的铸模形成的多个焊料连接。
18.根据权利要求1的方法，其中，该衬垫含金属层或者双层用作蚀刻期间对下层的掩模。
19.根据权利要求1的方法，其中，该蚀刻是保持第一含金属层的尺寸完整性由此防止底切的干蚀刻。
20.一种用于在半导体结构上形成焊料块期间减小块下金属化材料的腐蚀的方法，包括：
在结构中的至少金属化层之上利用沟槽形成钝化层；
在沟槽内形成第一含金属层；
通过图案化的抗蚀剂来控制至少第二含金属层的尺寸；
蚀刻图案化的抗蚀剂和该图案化的抗蚀剂下的部分第一含金属层，同时利用第二含金属层保护第一含金属层的剩余部分；和
在第二含金属层上回流焊料材料以形成焊料块，
其中，在蚀刻步骤期间控制第一含金属层基本上没有底切。
21.根据权利要求20的方法，其中，在蚀刻抗蚀剂之前附加该焊料材料且该焊料材料用作掩模。
22.根据权利要求20的方法，其中，该焊料块具有由抗蚀剂图案控制的第二含金属层的空间尺寸。
23.根据权利要求20的方法，其中，焊料材料由包括在与钝化层的沟槽重叠的位置处的焊料材料的铸模形成。
24.一种在形成焊料块期间控制焊料块尺寸的方法，包括：
形成具有配置用于焊料块的至少一个开口的抗蚀剂图案；
电镀在所述至少一个开口内的金属层；
去除抗蚀剂图案和下面的金属层；
在电镀的金属上提供焊料材料；和
回流焊料材料以形成焊料块。
25.根据权利要求24的方法，其中，在去除抗蚀剂图案之前填充该焊料材料。
26.根据权利要求25的方法，其中，该焊料材料用作蚀刻掩模。
27.根据权利要求24的方法，其中，该至少一个开口限定了电镀材料的纵向尺寸。
28.根据权利要求27的方法，其中，该电镀材料的纵向尺寸设定了焊料块的尺寸。
29.一种方法，包括：
在具有金属构造的结构上溅射第一含金属层；
在具有与该金属构造对准的沟槽的第一含金属层之上形成钝化层；
图案化该钝化层上的抗蚀剂以对第一含金属层形成开口；
电镀由抗蚀剂所界定的开口内的第二含金属层；
使用第二含金属层作为掩模，去除抗蚀剂和抗蚀剂下的第一金属层；
附加焊料材料到第二含金属层上；和
回流所述焊料材料。
30.一种受控熔塌芯片连接(C4)结构，包括在抗蚀剂图案中形成的至少一个电镀金属层，以形成球限制冶金层和没有底切的下金属层。
31.根据权利要求30的结构，包括由抗蚀剂图案分开的多个电镀金属层。
32.根据权利要求30的结构，其中，该焊料材料形成在电镀金属层上。
33.一种结构，包括：在结构中至少在金属化层之上具有沟槽的钝化层，在沟槽内并接触完成处理的金属化层的背面的第一含金属层，尺寸由位于第一含金属层之上的图案化的抗蚀剂控制的电镀金属，和在电镀的含金属层上回流以形成焊料块的焊料材料，其中，第一含金属层没有底切。
34.根据权利要求33的结构，其中，在钝化层上提供该第一含金属层。
35.根据权利要求33的结构，其中，该电镀金属是铜。
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