CN101501779A

CN101501779A - Memory device with adaptive capacity

Info

Publication number: CN101501779A
Application number: CNA2007800260948A
Authority: CN
Inventors: O·沙尔维; D·索科洛夫; A·梅斯罗斯; Z·科恩; E·格吉; G·西莫
Original assignee: Anobit Technologies Ltd
Current assignee: Apple Inc
Priority date: 2006-05-12
Filing date: 2007-05-10
Publication date: 2009-08-05
Anticipated expiration: 2027-05-10
Also published as: CN101512661A; CN101501779B; CN101512661B; CN101496110B; CN101496110A

Abstract

A method for data storage in a memory (28) that includes a plurality of analog memory cells (32) includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.

Description

Memory device with adaptive capacity

The cross reference of related application

The application advocates to enjoy the rights and interests of following patented claim: the U.S. Provisional Patent Application 60/747 that is filed on May 12nd, 2006,106, be filed in the U.S. Provisional Patent Application 60/822 on August 13rd, 2006,236, be filed in the U.S. Provisional Patent Application 60/825 on September 17th, 2006,913, be filed in the U.S. Provisional Patent Application 60/866 on November 16th, 2006,071, be filed in the U.S. Provisional Patent Application 60/866 on November 22nd, 2006,860, be filed in the U.S. Provisional Patent Application 60/867 on November 28th, 2006,399, be filed in the U.S. Provisional Patent Application 60/871 on Dec 26th, 2006,838, be filed in the U.S. Provisional Patent Application 60/882 on Dec 28th, 2006,240, be filed in the U.S. Provisional Patent Application 60/883 on January 2nd, 2007,071, be filed in the U.S. Provisional Patent Application 60/885,987 on January 22nd, 2007, and the U.S. Provisional Patent Application 60/889 that is filed on February 11st, 2007,277, the disclosure of these applications is all included this paper in to quote mode at this.

Technical field

The present invention relates generally to memory device, be specifically related to have the memory device of self-adaptation memory capacity.

Background technology

Multiple memory device, for example flash memory and dynamic RAM (DRAM) use the analog memory cell array to store data.For example, in April, 2003 at the IEEE journal, the 91st volume, the 4th phase, in " Introduction toFlash Memory " that the 489-502 page or leaf is delivered by people such as Bez, flash memory device has been described, the document is all included this paper in to quote mode herein.

In this type of memory device, each analog memory cell generally includes a transistor, and this transistor has kept the electric charge of some, and described electric charge represents to be stored in the information in the described storage unit.Write " threshold voltage " of the described storage unit of charge affects of a particular memory location, also, need apply voltage and arrive storage unit so that described storage unit can the conducting electric current.

Some memory devices are commonly referred to " single layer cell " (SLC) equipment, store single bit of information in each storage unit.Usually, the scope of the possible threshold voltage of described storage unit is divided into two zones.The magnitude of voltage that falls into a zone in these two zones is represented bit value " 0 ", and belongs to another regional magnitude of voltage representative " 1 ".More high-density equipment is commonly referred to " multilevel-cell " (MLC) equipment, two or more bits of each cell stores.In multilevel-cell, the scope of threshold voltage is divided into more than two zones, and wherein each Regional Representative is more than a bit.

For example, " the MultilevelFlash Cells and their Trade-Offs " that delivers by people such as Eitan on the 169-172 page or leaf on the journal of the international electron device conferences of holding in the New York, New York of IEEE in 1996 (IEDM), described multilayer flash cell and equipment, the document is all included this paper at this in to quote mode.The document compares several multilayer flash cells, for example type, DINOR type, AND type, NOR type and NAND type storage unit altogether.

The solid-state devices that people such as Eitan held in the Tokyo on September 21st to 24,1999 and the journal of material international conference (SSDM) the 522nd to 524 page deliver " Can NROM; a2-bit; Trapping Storage NVM Cell; Give a Real Challenge toFloating Gate Cells? " another kind of analog memory cell has been described, be called nitride ROM (NROM), the document is included this paper at this in to quote mode.3～7 February in 2002 in " A 512 MbNROM Flash Data Storage Memory with 8 MB/s Data Rate " that the 100-101 page or leaf of the journal of the international solid electronic device association of IEEE that the California, USA city of san francisco is held (ISSCC 2002) is delivered by people such as Maayan, described the NROM storage unit, it includes this paper in to quote mode herein.

Other exemplary types of analog memory cell are ferroelectric RAM (FRAM) unit, magnetic RAM (MRAM) unit and phase transformation RAM (PRAM is also referred to as phase transition storage PCM) unit.For example, in " the Future Memory Technology including Emerging NewMemories " that deliver by Kim and Koh on the 377-484 page or leaf of the international association of the 24th microelectronics (MIEL) journal first volume that the Nis at Studenica Monastery holds 16 to 19 May in 2004, described FRAM, MRAM and PRAM unit, it includes this paper in to quote mode herein.

In some applications, data are stored in the storage unit with variable density.For example, its disclosure is included in the United States Patent (USP) 6 of this paper to quote mode, 363,008, described a kind of many bits in every unit (multiple-bit-per-cell) storer that comprises a plurality of storage arrays, wherein the bit number of each cell stores is to set separately at each storage array.Reading and writing and the storage every unit than multi-bit in, prove that after tested accurate storage array is set to store the more bit number in every unit, and prove that after tested the storage array of accurately reading and writing and the every unit of storage as much bit number is set to store the less bit number in every unit.

As an alternative, include the United States Patent (USP) 6 of this paper in its disclosure in to quote mode, 456, in 528, for under a plurality of store statuss, operating a kind of flash memory Nonvolatile memory system of its storage unit usually, some selected block of its memory cell block of operation under two states or the ability of all pieces are provided.These two states are selected as in described a plurality of state the state at a distance of farthest, thereby the nargin of increase is provided in biconditional operation.

United States Patent (USP) 5,930,167, its disclosure is included this paper in to quote mode, has described a kind of storage system, and it comprises the read-only storage of flash electro-erasable programmable (EEPROM) cell array that is configured in the memory cell block that can wipe jointly.Single storage unit can be stored the data more than a bit, and reason is that it operates this single storage unit with detectable threshold range or state more than two.Described array any do not store section data and can be used as and write buffer memory, wherein these storage unit independent one by only operating to store an independent Bit data with two detectable threshold ranges.The data that enter storer initially write in the available piece with two states.Subsequently, in background (background), with a plurality of states with the described data read that is buffered, compress and write back in the less piece of described storer.

United States Patent (USP) 6,466,476, its disclosure is included this paper in to quote mode, has described every unit many bits nonvolatile memory, the different piece that it uses different every cell bit numbers to come memorying data flow.Particularly, use relatively little every cell bit number to come the data (for example, the frame head of Frame) of memory requirement altitude information integrality.The data of using big relatively every cell bit number to store to have higher fault tolerant degree (for example, the general data of expression music, image or video).

United States Patent (USP) 6,643,169, its disclosure is included this paper in to quote mode, has described a kind of type according to related data and has counted data storing method with variable every cell bit.When fidelity is not too important, can increase every cell bit number.When the fidelity outbalance, can reduce every cell bit number.In some embodiments, storer can be based on storage unit one by one and is changed between memory module.

Summary of the invention

Embodiment of the present invention provide a kind of being used for comprising the storer data storing method of a plurality of analog memory cells, and described method comprises:

Estimate the corresponding accessible memory capacity of described analog memory cell;

Based on estimated accessible memory capacity, distribute definition for described storage unit and treat to be stored in the corresponding stored configuration of the data volume in this storage unit;

According to the stored configuration of corresponding distribution, with data storage in described storage unit; And

Be installed in the host computer system and be used for after this host computer system storage data at described storer, reappraise the corresponding accessible memory capacity of analog memory cell, and, revise described stored configuration in response to the accessible capacity that is reappraised.

In some embodiments, the storage data comprise uses error correcting code (ECC) that data are encoded, coded data is converted to the analogue value in the set that is selected from a nominal analogue value and the described analogue value write corresponding storage unit, and each stored configuration is specified corresponding ECC code check and is used to store the size of set of the described nominal analogue value of data.

In one embodiment, for each analog memory cell, the storage data comprise data-switching is become to be selected from the analogue value in the set of a nominal analogue value and the described analogue value write described storage unit, and each stored configuration is all specified the nominal analogue value that is used in the described data of described analog memory cell storage.

In another embodiment, the storage data comprise data-switching are become the analogue value, and the described analogue value is write in the corresponding storage unit, and estimate that accessible memory capacity comprises the corresponding degree of distortion (distortion level) of the analogue value that influences write storage unit is estimated, and determine accessible memory capacity in response to described degree of distortion.

The distortion estimator degree can comprise from storage unit and reads the analogue value, and estimate described degree of distortion based on the analogue value that reads from described storage unit.The distortion estimator degree can comprise from reading from the analogue value of storage unit and comes reconstruct data, and calculate described degree of distortion based on the data of institute's reconstruct.In some embodiments, the calculated distortion degree can comprise reading the scalar function summation from the analogue value of described storage unit.Can comprise in response to data reading from the analogue value of storage unit and being stored in square summation of the difference between the corresponding expectation value of the data in the storage unit the summation of scalar function.In another embodiment, the calculated distortion degree comprises to be counted the quantity of following storage unit, in this storage unit, read from the analogue value of described storage unit and the difference that is stored between the corresponding expectation value of the data in the described storage unit and surpass a predetermined value in response to described data.

In disclosed embodiment, the storage data comprise programming and the checking (P﹠amp with analogue value write storage unit and use iteration; V) process is verified the analogue value that has write, and the distortion estimator degree comprises based on by described P﹠amp; The analogue value of V process verification is calculated described degree of distortion.

In another embodiment, the storage data comprise programming and the checking (P﹠amp with analogue value write storage unit and use iteration; V) analogue value that write of process verification, this process is by the programming step described analogue value of increment iteratively, and the stored configuration definition is by the P﹠amp of described iteration; The size of the programming step that the V process is used.

In yet another embodiment, the storage data comprise that treating the data that will be stored in one group of storage unit encodes with error correcting code (ECC), and coded data converts the analogue value to be used for being stored in the corresponding analog memory cell of this group storage unit, estimate that accessible memory capacity comprises that storage unit from described group reads the analogue value and to estimating, and revise stored configuration and comprise stored configuration in response to adaptive this group storage unit of the distance metric of being estimated between the analogue value that reads and the distance metric that approaches most between the effective ECC code word of the described analogue value.

In yet another embodiment, reappraise accessible memory capacity and comprise and read the data that are stored in the described storage unit, comprise in response to the detection mistake in the data that read and come adaptive described stored configuration and revise stored configuration.The storage data can comprise uses error correcting code (ECC) to the data coding, and adaptive described stored configuration can comprise the code check of revising ECC.

In some embodiments, the accessible capacity of assessment of memory cell comprises the previous programming that is applied to corresponding storage unit and erase operation is followed the trail of and estimate described accessible capacity in response to previous programming of having followed the trail of and erase operation.Estimate that accessible capacity can comprise in response to the length of the time period that has passed since previous programming and the erase operation and calculate accessible capacity.

In one embodiment, the storage data comprise that the initial part with described data converts the analogue value to and the described analogue value is write corresponding storage unit, and be written to the analogue value of described storage unit and do not wipe this storage unit by increase subsequently, the other part of described data is stored among at least some of described storage unit.

In another embodiment, the storage data comprise uses the error correcting code (ECC) that increases redundant digit for described data that data are encoded, and described redundant digit is stored in some analog memory cells, and revises stored configuration and comprise and revise a plurality of redundant digits that increase by described ECC and do not wipe described storage unit.The storage redundancy position can comprise and storage redundancy position, data separating ground.

In yet another embodiment, the memory allocated configuration comprises the set of a possible stored configuration of predefine, and revises the stored configuration that stored configuration comprises that selection is upgraded from described predefined set.Specify the non-integral bit number in every unit by the defined described data volume of at least one described stored configuration.

In yet another embodiment, the storage data are included in to be compressed data before the data write storage unit, and the stored configuration definition will be compressed the corresponding ratio of compression that is adopted to data.In a disclosed embodiment, the memory allocated configuration is included as the respective sets definition stored configuration of described storage unit.

In one embodiment, the storage data comprise the data item of accepting to be used for being stored in described storer in storage unit, the select storage unit subclass to be storing described data item in response to the stored configuration of being distributed therein, and with described store data items in selected storage unit subclass.In some embodiments, reappraising accessible memory capacity is to carry out during the section in the free time of described data not being stored and reading.

In another embodiment, distribute and revise stored configuration and comprise described stored configuration is stored in the allocation list.In some embodiments, can be before storer be installed in host computer system, the initial value of store storage configuration in the stored configuration table.In yet another embodiment, distribution and modification stored configuration are included in the data volume that is stored in the storage unit and estimate to keep between the accessible capacity predetermined nargin accordingly.In yet another embodiment, at least some distortions are caused by the leakage current in the analog memory cell, and distortion estimator comprises the estimation leakage current.

According to an embodiment of the present invention, a kind of method that is used for carrying out at the storer that comprises a plurality of analog memory cells data storage also is provided, this method comprises:

The degree of distortion of estimation among corresponding analog memory cell;

Based on estimated degree of distortion, estimate the corresponding accessible memory capacity of described analog memory cell,

Based on estimated accessible capacity, distribute definition for described storage unit and treat to be stored in the corresponding stored configuration of the data volume in the described storage unit; And

According to the stored configuration of corresponding distribution with described data storage in described storage unit.

According to an embodiment of the present invention, a kind of method that is used for carrying out at the storer that comprises a plurality of analog memory cells data storage also is provided, described method comprises:

When described storer is in user mode in host computer system, follow the trail of the corresponding accessible memory capacity of described analog memory cell;

Acceptance is used for being stored in the data of described storer;

The storage unit subclass that is used to store described data based on the accessible Capacity Selection one of being followed the trail of; And

With described data storage in the storage unit of described subclass.

In some embodiments, select subclass to comprise the storage unit of the big or small optimum matching of the data of selecting its accessible total volume and being accepted.In another embodiment, accept data and comprise the reliability step of accepting to be used to store the requirement of described data, and select subclass to comprise in response to desired reliability step select storage unit.Additionally or alternatively, accept data and comprise the desired maintenance phase that is used to store data of accepting, and select subclass to comprise select storage unit in response to the desired maintenance phase.Select subclass can comprise that selection has the storage unit of low distortion with respect to other storage unit.

In another embodiment, follow the trail of accessible memory capacity and comprise the previous programming and the storage operation that are applied to storage unit are followed the trail of, come select storage unit and select subclass to comprise in response to previous programming and erase operation.Select subclass can comprise and have the previous programming of less number of times and the storage unit of erase operation with respect to other storage unit in the described storage unit, a plurality of programmings and erase operation are evenly distributed in the described storage unit by being chosen in.The number of times of distribution programming and erase operation can comprise being chosen in the predetermined nearest time period carries out the previous programming of less number of times and the storage unit of erase operation with respect to other storage unit.

In disclosed embodiment, follow the trail of accessible memory capacity and comprise by accessible capacity summation to the storage unit that can be used for storing data, calculate the size of available storage space and report to described host computer system.

In another embodiment, storer is divided into a plurality of erase blocks, and each erase block is included in one group of storage unit of wiping in the single erase operation, and described method also comprises obliterated data item from described storer in the following way:

Identification stores one or more erase blocks of described data item;

When the erase block that stores described data item comprises the storage data of another data item, accessible capacity and another data item size based on the described storage unit of being followed the trail of, be identified in the other storage unit that stores described data item outside the described erase block, and the data of described another data item are copied to described other storage unit; And

Wipe the erase block that stores described data item.

In one embodiment, the data of accepting to be used to store comprise with the fixed capacity piece accepts data from host computer system, and based on the accessible capacity of the variable capacity group of being followed the trail of, with data storage in the variable capacity group of storage unit.In another embodiment, the storage data comprise two or more its capacity of identification less than the variable capacity group of the capacity of fixed capacity piece in the variable capacity group, and will be received in data storage in one or more fixed capacity pieces in two or more variable capacity groups of being discerned.

In yet another embodiment, the storage data comprise that with one or more variable capacity set of dispense be as exceeding the volume memory storage area in the variable capacity group, to be received in data storage in the fixed capacity piece in corresponding variable capacity group, and, when the accessible capacity of a variable capacity group during, in the data that are received in the corresponding fixed capacity piece some are stored in exceeding in the volume memory storage area of being distributed less than the capacity of described fixed capacity piece.In yet another embodiment, the storage data comprise that the data that will be received in the fixed capacity piece are stored in the storage unit sequentially in the variable capacity group, and and the border between the variable capacity group irrelevant.The storage data can comprise, initially will be received in data storage in each fixed capacity piece in corresponding variable capacity group, and subsequently to the data of initial storage reprogramming in proper order, and and the border between the described variable capacity group irrelevant.

In some embodiments, described method comprises from the variable capacity group takes out data, reconstruct fixed capacity piece, and use the fixed capacity piece to the host computer system output data.Described method can comprise by in the described data of buffer memory at least some, reduces the number of times of the memory access operations that is applied to described storer.Detect instantaneous storage incident in case at least some in the described data of buffer memory can comprise, just the data that are buffered are sent to storer.Instantaneous storage incident can comprise power fail on the horizon, overtime and acceptance at least one incident in the incident of the end of file (EOF) order of main frame system of being selected from.

According to an embodiment of the present invention, a kind of data storage device also is provided, comprising:

Interface, it is arranged to and the memory communication that comprises a plurality of analog memory cells; With

Memory signals processor (MSP), it is arranged to the corresponding accessible memory capacity of estimating described storage unit, based on estimated accessible capacity is that described storage unit distributes definition to treat to be stored in the corresponding stored configuration of the data volume in the described storage unit, according to the stored configuration of corresponding distribution with data storage in described storage unit, be installed in the host computer system and be used for after this host computer system storage data, reappraising the corresponding accessible memory capacity of analog memory cell at described storer, and revised described stored configuration in response to the accessible capacity that is reappraised.

According to one embodiment of the invention, a kind of data storage device also is provided, comprising:

Memory signals processor (MSP), it is arranged to the degree of distortion of estimation among corresponding analog memory cell, estimate the corresponding accessible memory capacity of described analog memory cell based on estimated degree of distortion, based on estimated accessible capacity is that described storage unit distributes definition to treat to be stored in the stored configuration of the data volume in the described storage unit, and according to the stored configuration of corresponding distribution with described data storage in described storage unit.

Memory signals processor (MSP), it is arranged to the corresponding accessible memory capacity of following the trail of described storage unit when described storer is in user mode in host computer system, acceptance is used for being stored in the data of described storer, be used to store the storage unit subclass of described data based on the accessible Capacity Selection one of being followed the trail of, and with data storage in the storage unit of described subclass.

Storer, it comprises a plurality of analog memory cells; With

Memory signals processor (MSP), it is connected to described storer and is arranged to the corresponding accessible memory capacity of estimating described storage unit, based on estimated accessible memory capacity is that described storage unit distributes definition to treat to be stored in the corresponding stored configuration of the data volume in the described storage unit, according to the stored configuration of corresponding distribution with data storage in described storage unit, be installed in the host computer system and be used for after this host computer system storage data, reappraising the corresponding accessible memory capacity of analog memory cell at described storer, and revised described stored configuration in response to the accessible capacity that is reappraised.

In some embodiments, memory bit is in first integrated circuit (IC), and MSP is arranged in the 2nd IC that is different from an IC.In a substituting embodiment, storer and MSP are integrated among the individual equipment.Also as an alternative, MSP is embodied in the processor of host computer system.In some embodiments, storage unit can comprise flash cell, dynamic random access memory (DRAM) unit, phase change memory (PCM) unit, the read-only storage of nitride (NROM) unit, MRAM storage (MRAM) unit or ferro-electric random access storage (FRAM) unit.

Storer, it comprises a plurality of analog memory cells; And

Memory signals processor (MSP), it is connected to described storer, and be arranged to when described storer is in use in host computer system, follow the trail of the corresponding accessible memory capacity of described storage unit, acceptance is used for being stored in the data of storer, select to be used to store the storage unit subclass of described data based on the accessible capacity that is tracked, and with described data storage in the storage unit of described subclass.

From following detailed description, and in conjunction with the following drawings, can understand the present invention more fully to embodiment.

Description of drawings

Fig. 1 is the block diagram that schematically shows according to the storage system of one embodiment of the invention;

Fig. 2 is the synoptic diagram that schematically shows according to the memory cell array of one embodiment of the invention;

Fig. 3 shows the curve map according to the voltage distribution in the multilayer memory cell array of one embodiment of the invention;

Fig. 4 shows the curve map according to the storage unit capacity distribution in memory cell array of one embodiment of the invention;

Fig. 5 shows according to the piece in memory cell array of one embodiment of the invention and the synoptic diagram of page structure;

Fig. 6 to 11 is the process flow diagrams of method that are used for revising adaptively memory device, stores density that schematically show according to embodiment of the present invention;

Figure 12 is a kind of process flow diagram that is used in variable-displacement memory device data storing method that schematically shows according to one embodiment of the invention;

Figure 13 schematically shows according to a kind of of one embodiment of the invention to be used for from the process flow diagram of the method for variable-displacement memory device obliterated data; And

Figure 14 to 17 is the synoptic diagram in the method for the data block of variable-displacement memory device storage fixed size of being used for that schematically show according to embodiment of the present invention.

Embodiment

General introduction

The accessible memory capacity of analog memory cell array such as flash memory changes as time goes by.In many cases since repeatedly programming with erase operation, wear out and other effects, the accessible capacity of memory cell array reduces as time goes by.The often difference to some extent for each different storage unit in the array of volume change degree.On the other hand, memory device is defined as in a certain reliability step usually a certain capacity is provided, and keeps interim these regulations that satisfies in a certain quantity data.

Some known memory device and the storage means that is associated are by crossing design or crossing the size of regulation memory cell array and the storage unit capacity that performance is dealt with variation.In this kind equipment, the quantity of storage unit and their performance are prescribed has nargin, and under the situation of the given expection degree of degeneration within the maintenance phase of expectation, big must being enough to of described nargin remains on described equipment within the regulation.This type of method for designing lacks efficient usually, has increased cost and complexity and has reduced the active volume of memory device.

Embodiment of the present invention provide the improved method and system that is used in memory device storage data by revising the density of data storage adaptively.

In some embodiments, in the memory device such as flash memory or DRAM equipment, this memory device comprises a plurality of analog memory cells to memory signals processor (MSP) with data storage.Described MSP estimates the accessible memory capacity of described storage unit constantly.Described MSP can estimate accessible capacity based on following factor, described factor for example the degree of distortion in the storage unit, at the reliability of data regulation and/or keep requiring, detected mistake and/or the elapsed previous programming of described storage unit and the history of erase operation in the data in being programmed in storage unit.

Based on estimated accessible capacity, described MSP distributes corresponding stored configuration for each storage unit.Every kind of stored configuration defines the data volume that can be stored in each storage unit.For example, described stored configuration can define a plurality of nominal voltage level and be used for Error Correction of Coding (ECC) scheme of data storage in storage unit.In some embodiments, described MSP selects suitable stored configuration from the finite aggregate of predetermined configurations.

Described MSP is according to the stored configuration of distributing to storage unit, with data storage in storage unit.In the whole serviceable life of memory device, As time goes on and adaptively described MSP revises stored configuration, so that the accessible capacity of the density of data storage in the storage unit and storage unit is complementary.

Known that storage density is carried out the memory device and the date storage method of priori regulation is different with some, method and system described herein, in the whole serviceable life of storage array, follow the trail of the accessible capacity of different storage unit, and constantly adapt to the density of data storage in view of the above.Therefore, the accessible capacity of memory device can be fully utilized owing to As time goes on it change, thereby has reduced size and cost.

MSP and Memory Controller or other main frames are mutual, also, accept the data be used to store from Memory Controller, and when the Memory Controller request, taking-up are stored in the data in the storer.In some embodiments, MSP is to the operation of Memory Controller imitation fixed capacity, although it with data storage in having a plurality of cell group of variable-displacement.For example, when MSP and old-fashioned Memory Controller are mutual, use this class methods, described old-fashioned Memory Controller is designed to have fixed capacity and fixed page size.Thereby by mediating between the adaptive capacity characteristic of operation of the fixed capacity of Memory Controller and storage means described herein, old-fashioned Memory Controller can use without modification.

System description

Fig. 1 is the block diagram that schematically shows according to the storage system 20 of one embodiment of the invention.System 20 can be used in the different host computer system and equipment, for example is used for computing equipment, cell phone or other communication terminals, removable memory module (for example " USB flash disk " equipment), digital camera, music and other media players and/or any other storage and takes out the system or equipment of data.In typical application, storage system 20 is mutual with Memory Controller 22, also, accept the data that are used to store from Memory Controller, and the data that will be stored in the storer outputs to Memory Controller when being requested.

System 20 comprises memory device 24, its with data storage in memory cell array 28.Storage array 28 comprises a plurality of analog memory cells 32.In the context of present patent application and in claims, term " analog memory cell " is used to describe the memory element arbitrarily of the continuous analog value of the physical parameter maintenance such as voltage or the electric charge.Array 28 can comprise the analog memory cell of any kind of, for example, for example, NAND and NOR flash cell, PCM, NROM, FRAM, MRAM and DRAM unit.The aanalogvoltage that is stored in the charge level in the storage unit and/or writes and read storage unit is collectively referred to as the analogue value in this article.

The data that are used for being stored in memory device 24 are provided for described equipment and are buffered in the data buffer 36.Described then data are converted into aanalogvoltage and use in read/write (R/W) unit 40 write storage units 32, and the function of this read/write cell 40 will make a more detailed description hereinafter.When sense data from array 28, unit 40 converts the aanalogvoltage of electric charge and storage unit thus 32 to numeral sample, and each numeral sample has the resolution of one or more bits.The sample that is produced by unit 40 is buffered in the impact damper 36.The operation of memory device 24 and sequential are by steering logic 48 management.

Memory signals processor (MSP) 52 is carried out data is deposited in memory device 24 and take out data from memory device 24.MSP 52 is between memory device 24 and Memory Controller 22 or other main frames.As hereinafter describing in more detail, MSP 52 uses novel method, is used for the accessible capacity of assessment of memory cell 32 adaptively, and is used for coming based on estimated storage unit capacity the storage and the taking-up of the data of managed storage array 28.MSP 52 revises the density of data storage in the array 28 adaptively, thereby provides best capacity in the length of life of described system.

MSP 52 can be according to the accessible capacity of storage unit, with different density with data write storage unit 32.In the context of present patent application and in claims, term " capacity " is used to describe the quantity of information (being that unit expresses with every cell bit number usually) that given storage unit or cell group can reliably keep.Term " density " is used for describing the quantity of information usually with every cell bit number calculated of actual storage in storage unit or cell group.Thereby, needing only not exceed capacity, just information can be stored in one group of storage unit reliably with different densities.Thereby tentation data is by reliable memory, and the storage density of a storage unit or one group of storage unit just is not more than its capacity according to definition so.

For example be used for quantity with the voltage level of data write storage unit 32 by change, MSP 52 can change the density of data storage in the storage unit 32.Use the voltage level of a greater number can make information density higher.In some embodiments, MSP 52 use error correcting codes (ECC) will be stored in the digital coding in the equipment 24.MSP 52 comprises encoder/decoder 64, and this encoder/decoder 64 will wait to want the digital coding of write device 24, and the data decode that slave unit 24 is read.In some implementations, MSP52 changes information density by the code check of selecting different sign indicating numbers or change ECC.

Signal processing unit 60 is handled the data of write device 24 and slave unit 24 taking-ups.Especially, 60 pairs of distortions that are present in the voltage of reading from storage unit 32 of signal processing unit are estimated.Estimated distortion is used for the accessible capacity of assessment of memory cell 32, and is used to determine expectation storage density to be used.MSP 52 comprises data buffer 72, and this data buffer 72 is used to store data by unit 60, and as the interface of communicating by letter with memory device 24.MSP 52 also comprises I/O (I/O) impact damper 56, the interface that this I/O (I/O) impact damper 56 is formed between described MSP and the Memory Controller.

Operation and the timing of Memory Management Unit 76 management MSP 52.Particularly, Memory Management Unit 76 is followed the trail of the estimated capacity and the state of each storage unit or cell group, so that MSP 52 density storage data to be complementary with its estimated capacity in each storage unit or in the cell group.Signal processing unit 60 and administrative unit 76 can realize with example, in hardware.Alternatively, unit 60 and/or unit 76 can comprise the microprocessor of the software that operation is fit to, the perhaps combination of hardware and software element.In some embodiments, encoder/decoder 64 or its part also can be realized with software.In some embodiments, the function of MSP52 can be carried out with the software realization and by other elements of suitable processor or host computer system sometimes.

The configuration of Fig. 1 is exemplary system configuration, and this diagram is used to make clear concept purely.Also can use other configurations that are fit to arbitrarily.For the purpose of clear, from accompanying drawing, omitted for understanding the non-essential element of principle of the present invention, for example various interface, addressing circuit, timing and sequencing circuit, data disorder circuit and debug circuit.

In some embodiments, memory device 24 and MSP 52 are implemented as two independent integrated circuit (IC).Yet, in an alternative embodiment, memory device and MSP can be integrated among the single IC or SOC (system on a chip) (SoC) in.In some implementations, single MSP 52 can be connected to a plurality of memory devices 24.The other framework aspect of some embodiment of realization system 20 is described in the U.S. Provisional Patent Application of above being quoted 60/867,399 in more detail.Alternatively, some functions or all functions of Memory Controller can realize in MSP52, as hereinafter being described in further detail.

In typical write operation, wait that wanting the data of write storage device 24 is to accept from Memory Controller 22, and be buffered in the I/O impact damper 56.Memory Management Unit 76 determines to treat to write the storage unit of data.Stored configuration to be used (for example, a plurality of voltage levels and code check) is determined also based on the estimated capacity of designated memory locations in unit 76.The described data of encoder/decoder 64 codings, and data encoded is sent to memory device 24 by data buffer 72.In equipment 24, described data are stored in the impact damper 36 provisionally.Read/write cell 40 becomes analog voltage with described data-switching, and data is write in the suitable storage unit 32 of array 28.

In typical read operation, read/write cell 40 is read analog voltage and is numeral sample with described voltage transitions from suitable storage unit 32.Described sample is buffered in the impact damper 36, and is sent to the impact damper 72 of MSP 52.Data block is sent to unit 60 from impact damper 72, and encoder/decoder 64 is with the ECC decoding of these data blocks.Decoded data are sent to Memory Controller 22 via I/O impact damper 56.

Memory Controller 22 can comprise known equipment sometimes, for example the PS8000 NAND flash controller equiment that is provided by PhisonElectronics Corp. (in Hsinchu County, Taiwan Province Zhu Dong town).This equipment is described in detail in " PS8000 ControllerSpecification (PS8000 controller specification) " the 1.2nd revised edition of issue on March 28th, 2007, includes this paper in to quote mode herein.Another kind of known Memory Controller is Databahn ^TMFlash controller IP, it is by Denali Software, and Inc. (the Palo Alto city in the California) provides.Details about this product see also www.denali.com/products/databahn_flash.html.Another example is by Datalight, the FlashFX Pro that Inc (the Bo Saier city in the State of Washington) provides

The flash medium manager.This equipment is described in " the FlashFXPro 3.1 HighPerformance Flash Manager for Rapid Development of ReliableProducts " that delivered on November 16th, 2006, and the document is included this paper at this in to quote mode.

When Memory Controller 22 comprised the legacy memory controller equiment, it had predetermined interface and the agreement that is used for memory device communication usually.These interfaces and agreement are designed to and the memory device communication with fixed storage capacity usually.In some embodiments, MSP 52 imitation is by Memory Controller 22 employed data structures, interface and agreement, thereby plays intermediation between the fixed capacity characteristic of the adaptive capacity characteristic of system 20 and Memory Controller 22.Among Figure 14 hereinafter-17, the method for various exemplary has been described.

In an alternative embodiment, in MSP 52, realize some memory management functions.In these embodiments, MSP accepts to be used for stored data items, and can and be stored in the variable-displacement page or leaf their subregions, and needn't imitate the fixed capacity operation.

Interface between MSP 52 and memory device 24, and/or the interface between MSP 52 and Memory Controller 22 can be followed known standard or agreement.For example, class in these interfaces or two classes can be followed open nand flash memory interface (ONFI) specification.The definition in " the Open NAND Flash Interface Specification " of in Dec, 2006 issue revises the 1.0th edition of ONFI specification, it includes this paper in to quote mode herein.

Memory array structure and distortion mechanism

Fig. 2 is the synoptic diagram that schematically shows according to the memory cell array 28 of one embodiment of the invention.Though Fig. 2 relates to the flash cell that is connected in the particular array configuration, principle of the present invention also can be applicable to storage unit and other array configurations of other types.In the list of references of in the part of background technology above, being quoted, some exemplary Storage Unit Type and array configurations have been described.

The storage unit 32 of array 28 is disposed in the grid with a plurality of row and a plurality of row.Each storage unit 32 comprises floating grid metal-oxide semiconductor (MOS) (MOS) transistor.By applying suitable voltage level, the electric charge (electronics or hole) of some can be stored in the particular storage to transistorized grid, source electrode and drain electrode.The value that is stored in the described storage unit can read by the threshold voltage of measuring described storage unit, and described threshold voltage is defined as making described transistor turns and the minimum voltage that need apply to described transistorized grid.The threshold voltage that is read is proportional with the electric charge that is stored in the described storage unit.

In the exemplary configuration of Fig. 2, the transistorized grid in each row is connected by word line 80.Transistorized source electrode in each row is connected by bit line 84.In some embodiments, for example in some NOR units, source electrode is directly connected to bit line.In an alternative embodiment, for example in some NAND units, bit line is connected to many string floating grids unit.

Usually, read/write cell 40, the grid that is applied to a particular memory location 32 by the voltage level that will change (also is, be applied to the word line that described storage unit is connected to), and whether the drain current of checking described storage unit has surpassed a certain thresholding, the whether conducting of described transistor), read the threshold voltage of this particular storage 32.Read/write cell 40 applies a series of different magnitude of voltage to the word line that described storage unit was connected to usually, and is defined as making drain current to surpass the minimum gate voltage values of described thresholding.Usually, unit 40 reads one group of storage unit simultaneously from certain delegation.

In some embodiments, read/write cell 40 is by measuring drain current with the bit-line pre-charge of described storage unit to a certain voltage level.In case grid voltage is set to expectation value, drain current just makes that bit-line voltage discharges through storage unit.After applying grid voltage several milliseconds, read/write cell 40 is measured bit-line voltages, and bit-line voltage and thresholding are compared.In some embodiments, each bit line 84 is connected to corresponding sensor amplifier, and this sensor amplifier amplifies bit line current and this current conversion is become voltage.Use comparer that described voltage and thresholding are compared.

Voltage reading access method as described above is a kind of illustrative methods.As an alternative, read/write cell 40 can use any other method that is fit to be used for the threshold voltage of reading cells 32.For example, read/write cell 40 can comprise one or more analog to digital converters (ADC), and this analog to digital converter converts bit-line voltage to numeral sample.

In some embodiments, whole page or leaf (OK) is by concurrent reading and concurrent writing.Wiping usually in comprising a plurality of pages piece of storage unit carried out.Typical memory device can comprise hundreds thousand of pages or leaves, and each page or leaf comprises thousands of storage unit (for example, every page 16K or 32K storage unit).Typical erase block is 128 pages the order of magnitude, although also can use other piece size.

Can comprise multiple distortion by read/write cell 40 digitized voltages, these distortions are caused by the different distortion mechanism in the array 28.Some distortion mechanism have influenced the actual electric charge that is stored in the storage unit, and the feasible voltage distortion of being read of other mechanism.For example, the threshold voltage in the particular memory location is revised in the electric coupling meeting between the consecutive storage unit in the array.This effect is called as interference noise.As another example, As time goes on electric charge can leak from the unit.The result of this aging effect is that As time goes on the threshold voltage of described storage unit incites somebody to action and the value drift from writing at first.

The distortion of another kind is commonly called turbulent noise, is to be caused by reading and writing on a certain storage unit in the array or erase operation, and this has caused wipes or programme other storage unit unexpected.As another example, by a kind of effect that is called background patterns correlativity (backpattern dependency), the source electrode-drain current of particular memory location can be influenced by the electric charge of (for example in same NAND unit strings) in the consecutive storage unit.

Distortion/capacity balance

Fig. 3 shows the curve map that distributes according to the voltage in the memory cell array 28 of one embodiment of the invention.Fig. 3 is used to demonstrate the distortion effect on the accessible capacity of storage unit.In Fig. 3, be illustrated the storage unit that its voltage distributes, the information that all is configured to use four nominal voltage level that are labeled as 90A to 90D to store two bits.

For two data bit of storage in a storage unit, read/write cell 40 writes this storage unit with one of four nominal voltage level.In current example, voltage level 90A is corresponding to place value " 11 ", and voltage level 90B to 90D is separately corresponding to place value " 01 ", " 00 " and " 10 ".

Though what read/write cell was write is specific nominal voltage level, because distortion mechanism is different, and the programming that storage unit is done and the accuracy of wiping are limited, and voltage level departs from this nominal level usually so the actual door of storage unit is rationed the power supply.Figure 92 A to 92D shows exemplary voltage and distributes.Figure 92 A shows the distribution of the voltage in the storage unit of storage " 11 " place value.Figure 92 B, 92C and 92D show the distribution of the voltage in the storage unit of storage " 01 ", " 00 " and " 10 " place value separately.Attention, because aging and other distortion mechanism, the voltage when reading distributes to be different from and writes fashionable voltage distribution.

By limiting three thresholding 94A to 94C, the total size of threshold voltage is divided into four interval 96A to 96D.When the threshold voltage level of reading cells, the voltage level that falls into interval 96A is assumed that corresponding to " 11 " place value.Similarly, the voltage level that falls into interval 96B to 96D is assumed to be separately corresponding to place value " 01 ", " 00 " and " 10 ".Therefore interval 96A to 96D is commonly called between decision area, and thresholding 94A to 94C is called as decision threshold.

When the voltage that writes according to a certain data bit value fell between wrong decision area, the data of reading from storage unit were different with the data that write, and cause read error.For given degree of distortion, the mistake of storage unit carry out and accessible capacity between have a kind of balance.When the quantity of nominal voltage level increased (also promptly, storage density increases), the size between decision area will become littler owing to distortion effect.Therefore, read voltage and more may drift about or fall between wrong decision area, and error probability increases.For given error probability, the accessible capacity of storage unit reduces along with the increase of degree of distortion.

The storage unit capacity of the change in the whole storage cell array

As mentioned above, the accessible capacity of storage unit (quantity of the information bit that can reliably be programmed in storage unit also promptly) depends on the degree of distortion of this particular memory location.Under many actual conditions, the variation of accessible capacity from a storage unit to another storage unit is quite big.

Different storage unit 32 in the array 28 has different distorted characteristics usually.For example, some storage unit for example are positioned at the storage unit on the outer boundary of erase block, have consecutive storage unit still less, therefore often have the lower cross coupling noise level from consecutive storage unit.As another example, because the storage unit of programming has caused interference, disturbance and background patterns correlativity mistake to the storage unit of previous programming, therefore the storage unit of programming is compared with the storage unit of programming early late, may suffer less error level.As another example, a certain sensor amplifier or ADC can introduce extra high noise level, and it causes comparing with other bit lines along the storage unit of specific bit line, has higher distortion.Other distorted characteristics can depend in particular memory location or the history of programming of carrying out in its environment and erase operation.Since these and other factors, the distortion in the storage unit 32, and accessible capacity in these storage unit therefore, marked change in the scope of whole array 28 usually.

Fig. 4 shows the curve map that distributes according to the exemplary storage unit capacity in the memory cell array of one embodiment of the invention.Diagram 100 shows the accessible capacity of different storage unit.In current example, accessible capacity changes between about every unit 4.2 to 7.3 bits.Diagram 104 shows the actual storage density that can be used for the storage unit programming, has supposed that a certain margin of safety is to guarantee the unfailing performance in the whole desired data maintenance phase.As seen in FIG., when according to diagram 104 to each storage unit individually memory allocated density the time, the average storage density that is reached is higher than every unit 5 bits.

If the storage unit of the array among Fig. 4 has been assigned with fixing storage density, then whole array will have to be defined as each storage unit and only have three bits, although most of storage unit can reach much higher memory capacity.In some known memory devices that used bad block management (BBM) method, array can be designated as the array of 4 bits/cell, and the storage unit of some of them group has been identified as flaw.The BBM method is for example by STMicroelectronics (Switzerland, Geneva) described among " the Bad Block Management in NAND Flash Memories " that delivers on the operational manual AN-1819 on November 29th, 2004, it includes this paper in to quote mode herein.

Method and system described herein is stored in data in each storage unit or the cell group with the density that is complementary with the accessible capacity of storage unit.The storage unit that has than low distortion is assigned with higher capacity, and suffers the storage unit of strong distortion to be assigned with lower capacity.In the whole serviceable life of array, method and system described herein is followed the trail of the change of distortion and capacity, and therefore is modified in the density of storage data in the different storage unit adaptively.

Can the assessment of memory cell capacity, also storage density can be assigned to independent storage unit or jointly be assigned to many group storage unit.Distributing independent density to less many groups storage unit, be that cost allows more critically storage density to be matched with accessible capacity with complicated more management, and vice versa.

Fig. 5 shows according to the piece in the memory cell array 110 of one embodiment of the invention and the synoptic diagram of page structure.Array 110 comprises a plurality of row 114.Storage page is defined as being write simultaneously one group of storage unit of (programming).In some cases, each page or leaf all comprises a full line storage unit.In other cases, each row can be divided into several pages or leaves.Come from array 110 obliterated datas by wiping many group pages or leaves (being called erase block 118) simultaneously.For example, a typical page can comprise 16,384 storage unit, and typical erase block can comprise 128 pages or leaves, but also can use other sizes.In some embodiments, each page or leaf can be divided into several sector (not shown)s.

In the explanation hereinafter, basic capacity and density distribution unit are pages or leaves.In other words, all storage unit in a specific page are all used the voltage level of equal number and are used identical ECC to programme.Can be undertaken adaptive, next by quantity and/or ECC to voltage level to the different different density of page or leaf distribution.In an alternative embodiment, capacity estimation and density distribution can use the many groups storage unit with any desired granularity to carry out, for example based on page by page, block-by-block, by the sector even by the granularity of storage unit.In some embodiments, capacity estimation and density distribution are together to carry out at the storage unit that is connected to specific bit line 84 or word line 80.

The density self-adapting distribution method

According to embodiment of the present invention, the several exemplary method has been described in the explanation hereinafter, be used to estimate the accessible capacity of many group storage unit 32 (being a plurality of pages or leaves), and be used for revising adaptively the storage density of memory device 24.

In some embodiments, the administrative unit 76 among the MSP 52 keeps a stored configuration table, and this stored configuration table is called as one group of parameter of stored configuration for each page maintenance.How the stored configuration of specific page has been determined data storage in page or leaf, and can comprise following parameter, for example be used for data storage in the value of the quantity of the voltage level of the storage unit of page or leaf, these voltage levels, be used at page or leaf the ECC of data coding and/or other parameters that are fit to arbitrarily.In some cases, for example when using Trellis-coded modulation (TCM) or other code modulating methods, made up selection to ECC and voltage level.Except stored configuration, the stored configuration table can also keep the parameter such as distortion estimator degree of this page and the accessible capacity of estimation.In some embodiments, the initial value of stored configuration can be stored in production process in the stored configuration table.

When a specific page writes data, the stored configuration of MSP 52 these pages of inquiry.Described MSP uses suitable ECC to encode, and coded data is mapped to the quantity of suitable voltage level, and is indicated as the stored configuration of this page.In some embodiments, when from the specific page reading of data, described MSP will become hard bit decision by the sample conversion that read/write cell 40 produces according to the quantity by the indicated level of the stored configuration of this page.Described then MSP becomes ECC indicated in the stored configuration with the ECC decoder configurations, with decoding ECC.As an alternative, for example, when described demoder comprises soft demoder, the sample that described MSP uses soft decoder decode to be produced by read/write cell 40, and do not generate hard decision.

Use the voltage level of varying number may the design of read/write cell 40 be impacted, for example the design to comparer, ADC, DAC, sensor amplifier and interlock circuit impacts.In some embodiments, the sensitivity of read/write cell and resolution are designed to mate the maximum quantity of employed voltage level.In an alternative embodiment, unit 40 can read a plurality of threshold voltages from a page or leaf in the iteration several times of the resolution that increases gradually (for example, by use different thresholdings in each iteration).Based on the quantity of the level that is used for storing in specific page, administrative unit 76 can be determined the expectation number of times of iteration, and consequent resolution.

Fig. 6 schematically shows the process flow diagram of method of revising the storage density of memory device 24 according to a kind of self-adaptation of one embodiment of the invention.In distortion estimating step 130, this method starts from 52 pairs of degree of distortion in storage unit 32 of MSP and estimates.MSP 52 can use the distinct methods of assessment of memory cell distortion.

For example, in order to estimate the distortion in the specific objective storage unit, MSP can read the voltage from consecutive storage unit, the cross-couplings ratio between estimating target storage unit and the consecutive storage unit, and calculate the accumulation coupled noise of contributing by consecutive storage unit.

In some embodiments, after the programming operation that certain page is applied, MSP can estimate the distortion in this page.Following Fig. 7 shows exemplary back (post-writing) method of estimation of writing.As an alternative, after the read operation that certain page is applied, MSP can estimate the distortion in this page.Following Fig. 8 illustrates exemplary back (post-reading) method of estimation of reading.Also can come estimated capacity by the reliability that changes programming data, for example the error correcting code by applying crescendo is up to realizing errorless storage.These class methods are hereinafter described in Fig. 9.

Be further used as alternatively, can come the distortion estimator degree based on programming and erase operation history that this page lived through.Programme and wipe history and can influence degree of distortion in many ways.Usually, it is believed that, older storage unit (also promptly, the current programming of more number of times and the storage unit of erase operation of having experienced) is compared with the newer storage unit of the programming of having experienced less number of times and erase operation, has higher leakage current level.Thereby distortion also is subjected to the influence of time of having been passed since previous programming and erase operation.Among Figure 11 below, described a kind of based on the illustrative methods of programming and erase operation history is come the assessment of memory cell capacity.

In stored configuration calculation procedure 134, MSP 52 estimates the page or leaf capacity and determines to treat will be in the employed stored configuration of each page.Described MSP can use any suitable method, is used for estimating accessible page or leaf capacity based on the distortion of estimating, and is used to select suitable stored configuration (for example, the quantity of voltage level and ECC).

Usually, described MSP leaves a certain margin of safety between the storage density of estimated capacity and its setting.Described margin of safety is also referred to as performance margin, is to be set the reliable operation that guarantees in the desired data maintenance phase.Hereinafter further describe the several exemplary method that is used for determining suitable stored configuration.The new stored configuration of calculating of unit 76 usefulness of MSP 52 is come the updated stored allocation list.Writing step 138, the stored configuration that MSP 52 usefulness are upgraded is write data subsequently the page or leaf of array 28.

P﹠amp; The V assist population distributes

Fig. 7 schematically shows programming and checking (P﹠amp according to another embodiment of the present invention; V) after the process, revise the process flow diagram of method of the storage density of memory device 24 adaptively.

P﹠amp; The V process is generally used for storage unit is programmed.At typical P﹠amp; In the V process, come the storage unit programming by applying a series of potential pulses, the voltage level of these potential pulses increases one by one pulsedly.The voltage level that is programmed is read (" checking ") after each pulse, iterative process is proceeded, up to reaching expectation voltage level or up to operation overtime.P﹠amp; " the A 117mm that the V process is for example delivered at IEEE solid-state circuit magazine (IEEEJournal of Solid State Circuits) 1575-1583 page or leaf (11:31) in November, 1996 by people such as Jung ²3.3V Only 128Mb Multilevel NAND Flash Memory forMass Storage Applications "; and be described in " the A MultipageCell Architecture for High-Speed Programming Multilevel NANDFlash Memories " that on the 1228-1238 page or leaf of IEEE solid-state circuit magazine (33:8), deliver in August, 1998 by people such as Takeuchi, these two pieces of documents are all included this paper in to quote mode.

The method of Fig. 7 can combine with the normal running of system 20.Under this operator scheme, after to the page or leaf of particular group (for example, single page or leaf or comprise the NAND storage block of several NAND strings) programming, its degree of distortion is estimated, and its stored configuration is upgraded so that use in next programming operation.At P﹠amp; V programming step 150, this method start from by MSP52 and use P﹠amp; The V process is to the page or leaf programming of particular group.At back P﹠amp; V calculation procedure 154 is at last once P﹠amp; After the V iteration, MSP calculated distortion statistics.Last P﹠amp; The V iteration relates to the program voltage level of the different storage unit that read in this page inherently.MSP can use these voltage levels that read to calculate degree of distortion in this page.

In some cases, the read-out resolution that is used for program verification is not enough to be used for reliable distortion and estimates.In these cases, described MSP can read the voltage level of the page or leaf of this group that is programmed under the resolution of the read-out resolution that is higher than verification operation.

At back P﹠amp; V step of updating 158, MSP 52 upgrades the accessible capacity of the estimation of page or leaf.Described MSP uses the degree of distortion of calculating to upgrade the stored configuration of this page, also, and suitable voltage level quantity and ECC.The data of described MSP storage update in the stored configuration table are so that use in next programming operation of this page.

In some embodiments, MSP 52 can attempt increasing page or leaf density after programming.In these embodiments, described MSP determine data programmed whether enough reliable (also promptly, the distortion statistics of calculating in step 154 show this nargin enough height to guarantee to hang down error probability).If there are enough performance margin, just by increasing voltage level quantity and/or code check, the stored configuration of revising this page is to reflect higher density for this MSP.

When in conjunction with P﹠amp; When the V process is determined the page or leaf stored configuration, can be at P﹠amp; Make different balances between the parameter of V process and the page or leaf stored configuration.At P﹠amp; In the V process, can be by changing at continuous P﹠amp; Voltage increment between the V iteration or voltage step size come to exchange degree of accuracy for program speed.Higher P﹠amp is set; The V step-length just can be that cost allows with less iterations page or leaf to be programmed with lower programming accuracy, and vice versa.Such balance is for example described in " A 3.3V 32Mb NAND Flash Memory with Incremental StepPulse Programming Scheme " that the 1149-1156 page or leaf of the 3rd volume o. 11th of IEEE solid-state circuit magazine is delivered November nineteen ninety-five by people such as Suh, and it includes this paper in to quote mode herein.

In some embodiments, MSP 52 is provided with concrete P﹠amp for each page; The V step value.P﹠amp; The V step-length is used as the part of the stored configuration of page or leaf in the stored configuration table and stores.When concrete page or leaf was programmed, described MSP inquired about the stored configuration of this page and uses Shi DangdeP ﹠amp; The V step-length.

Can be by selecting P﹠amp; The quantity of V step-length, voltage level provides different performance tradeoff with ECC.For example, bigger P﹠amp; The V step-length is that cost makes that programming can be faster with higher error probability.Again for example, the voltage level of reduction can be that cost makes that programming can be faster with higher error probability also, and can access lower disturbance level (disturblevel), interference level and wearing and tearing level.Can be by reducing voltage level quantity or, being that cost reduces error probability to reduce storage density by introducing stronger ECC.The selection of ECC can influence the complexity of MSP.Thereby, can sacrifice storage density and/or error-correcting performance exchanges program speed for.

The density distribution of decision-directed

Fig. 8 is the process flow diagram of method of storage density that is used for revising adaptively memory device 24 after read operation that schematically shows according to another embodiment of the present invention.

In page or leaf read step 170, this method starts from MSP 52 slave units 24 and reads concrete storage page.Reading back calculation procedure 174, described MSP calculates the degree of distortion in the page or leaf of supposing the inerrancy existence.Typically, MSP calculates poor between each soft sample and corresponding hard decision.Because suppose not exist decoding error, so this difference is owing to distortion.Note, can produce hard decision by the ECC demoder.Scalar function that can be by calculating the difference between soft sample and corresponding hard decision and (for example, Cha quadratic sum) come the distortion estimator degree.Also can come distortion estimator above the quantity of the storage unit of a certain thresholding by calculating wherein this difference.If these thresholdings are to read these storage unit employed threshold level when obtaining hard decision, then distortion estimates to comprise the quantity of the mistake of being proofreaied and correct by described ECC.

Reading back step of updating 178, described MSP upgrades the accessible capacity to this page estimation.Described MSP uses the degree of distortion of being calculated to be updated in the stored configuration of this page or leaf in the stored configuration table, to be used for next programming operation of this page.Method shown in Figure 8 can combine with the normal running of system 20.Under this operator scheme, after reading of data, a concrete page or leaf is programmed, estimate the degree of distortion of this page, and upgrade its storage density, to be used for next programming operation.

In some embodiments, described MSP can carry out distortion and estimate task in the time period of system's free time, in order to avoid slow down read operation.

In some embodiments, described MSP can carry out blind distortion estimator degree, also, does not make the hypothesis that hard decision does not contain mistake.For example, when the nominal voltage level of write storage unit was 1V and 3V, if relatively large read voltage around 2V, even if then data are not encoded, described MSP can conclude that also degree of distortion is high.

Based on the density self-adaptation of the reliability of programming data

In some embodiments, MSP 52 writes on the reliability of the data in the given page or leaf by assessment, estimates the accessible capacity of this page.In some cases, described MSP carries out adaptive to the stored configuration of page or leaf and does not wipe these storage unit.In these cases, can under the situation of not wiping already present page or leaf, in program cycles subsequently, in this page, write other data.Quantity and/or modification ECC by revising voltage level realize the change to density.

Fig. 9 is the process flow diagram that schematically shows according to the illustrative methods of the stored configuration of revising memory device 24 adaptively of one embodiment of the invention.In current example, using system ECC (also promptly, a kind of based on adding redundant digit and do not revise this not ECC of bits of coded in the noncoded information position) programmes to data.Revise storage density and error performance by adaptive redundant figure place.

At the programming step 190 of not encoding, this method starts from by MSP 52 and without coding one concrete page or leaf is programmed.Normally but optionally, the quantity of selecting voltage level is so that storage density slightly surpasses pre-determined characteristics nargin, and also, this page or leaf can comprise some mistakes.

In decoding step 194, MSP is from page or leaf reading of data and these data of decoding alternatively, and checks step 198 in degree of distortion, checks the degree of distortion in the storage unit.MSP can use diverse ways and criterion, to determine whether distortion is too high for the current stored configuration of distributing to described page or leaf, to cross and lowly still can accept.For example, MSP can check whether decoded page or leaf comprises the mistake of not proofreaied and correct by ECC.

Alternatively, described MSP can estimate at the distance metric that reads between effective code word of the voltage set of the storage unit of page or leaf and described ECC.Described MSP can make comparisons with the distance apart from other code words apart from the distance of correct code word (also promptly, in fact writing the code word of storage unit) reading voltage.For this purpose, can use any suitable distance metric, for example Hamming tolerance or Euclidean tolerance.

Described MSP comes to carry out adaptive to the stored configuration of distributing to page or leaf based on the distortion of assessing in step 198.If degree of distortion can be accepted, then stopping step 202, MSP keeps current stored configuration and this method stops.If degree of distortion is too high, then increase step 204 in redundance, described MSP increases the redundance (also promptly, increasing redundant digit) of ECC.Thereupon, the density of page or leaf reduces.In config update step 206, described MSP is the updated stored allocation list in view of the above.This method is circulated back to top step 194 then.If degree of distortion low excessively (also promptly, can increase storage density and performance can't be reduced with accepting) then reduces step 208 in redundance, described MSP reduces the redundance of ECC.In step 206, described MSP updated stored allocation list, and described method is circulated back to top step 194.Described iteration continues, and converges on the suitable redundant figure place that is complementary with current degree of distortion up to this method.

In the serviceable life of equipment 24, can for example use the method for top Fig. 8, carry out aperiodically the inspection of the reliability of programming data, if necessary, can carry out increase to redundant figure place.Because degree of distortion changes as time passes, thus can adaptive in view of the above stored configuration to keep the error performance of expectation.

In some embodiments, can storage unit not wiped with the adaptive stored configuration of the method for Fig. 9.For example, when ECC comprises systematic code, redundant digit can with bits of coded separate storage not.Can increase or reduce the quantity of redundant digit and do not wipe or reprogramming storing not the storage unit of bits of coded.

Be used to increase by one group of storage unit () storage density and eraseable memory unit or to a kind of substitute technology of other storage unit programming not relates to and carry out other programming operation on the storage unit of having programmed for example, a page or leaf.For example, consider a memory cell array, storage unit can be programmed to level 0 to (2n-1) therein, wherein corresponding to the level of charge stored of level i less than the charge level relevant with level i+1.

In some embodiments, initially m storage unit is programmed for the even-order level, also, is programmed for level 0,2 ... 2n-2.After the degree of distortion in the storage unit was estimated, described MSP used binary coder with other information bit coding, and described binary coder generates m bits of coded.The code check of described scrambler depends on the distortion of estimation.Described MSP bits of coded is the odd-order level for the storage unit reprogramming (without wiping) of " 1 ", also, level 1,3 ... 2n-1.For example, the level of new storage unit can be written as y (m)=x (m)+b (m), and wherein y (m) represents the new level of storage unit m, and x (m) represents the previous level of this storage unit, and the individual value of bits of coded (" 0 " or " 1 ") of b (m) expression m.This scheme can be thought according to the distortion of estimating and adaptive adaptation rate Trellis-coded modulation (TCM).The finite set of stored configuration

In some embodiments, MSP 52 is that each page selected suitable stored configuration (for example, the quantity of level and ECC scheme) from the predetermined set of stored configuration.Use to the finite set of stored configuration has reduced the complexity of MSP, and has especially simplified the stored configuration table in the unit 76.

Figure 10 schematically shows the finite set that uses stored configuration according to one embodiment of the invention a kind of process flow diagram with the method for the storage density of revising memory device 24 adaptively.In definition step 210, this method starts from one group of stored configuration of predefine.The concrete quantity of every kind of equal specified voltage level of stored configuration and concrete ECC scheme.Thereby every kind of stored configuration defines a certain storage density, also, and certain every cell bit value.

Notice every cell bit number and need not be integer, carry out rather than independent storage unit is carried out because (1) data bit can be united many groups storage unit to the mapping of voltage level, and the quantity of (2) voltage level can not be 2 power.Hereinafter further describe the illustrative methods of the storage density that realizes every unit decimal bit.Following table shows the set of ten exemplary stored configuration:

Stored configuration	Bits/cell	Level/unit
Stored configuration	Bits/cell	Level/unit	0	N/A	N/A
1	1	2	0	N/A	N/A
1	1	2	2	～1.5	3
3	2	4	2	～1.5	3
3	2	4	4	～2.5	6
5	3	8	4	～2.5	6
5	3	8	6	～3.5	12
7	4	16	6	～3.5	12
7	4	16	8	～4.25	20
9	～4.5	24	8	～4.25	20

The bad page or leaf of stored configuration 0 expression, it is not used.Configuration 1 to 9 provides 9 kinds of different density ratings, between 1 to 4.5 bits/cell.In an alternative embodiment, can use any other suitable stored configuration set.

Typically, the stored configuration table in the administrative unit 76 adopts and carries out initialization from certain default stored configuration of predetermined set.At page or leaf programming step 214, when writing a concrete page or leaf, MSP 52 uses specified ECC of the stored configuration of page or leaf thus and level quantity to come data are encoded and shone upon.

After the one-time programming operation or after a read operation, in nargin estimating step 218, described MSP estimates the performance margin of page or leaf.As mentioned above, the reliability of described MSP can be by measuring the voltage that reads from described page or leaf distortion or the data that read from described page or leaf by assessment is come estimated performance nargin.Described nargin can or use any other suitable tolerance to express with signal to noise ratio (snr).

Whether described MSP usability nargin is complementary with the current capacity of this page with the stored configuration that is defined as this page appointment, determines that perhaps storage density is to increase or reduce.For example, described MSP can will estimate that nargin and a thresholding compare.

If estimate that nargin shows that storage density should be modified, then in config update step 222, MSP selects different configurations from predetermined set.Described MSP upgrades the selection of configuration in the stored configuration table, so that the programming operation subsequently on this page or leaf can use the stored configuration of having upgraded.

In some embodiments, MSP 52 compressed the data that will be stored in the concrete page or leaf before the ECC coding.No matter any compression method well known in the art is low-loss or high loss, all can be used for this purpose.Compression can produce different storage densitys with the combination of ECC coding, also, and different every cell bit values.

In some embodiments, the total number of bits (being labeled as M) that is stored in each page keeps constant in different stored configuration, and clean information digit (being labeled as K) is variable.For example, suppose that one page comprises 4,224 storage unit, and use 16 voltage levels storage unit programme (4 bits of each cell stores also promptly).The total number of bits that is stored in the page or leaf is 4,224 * 4=16,896.Adopt 7/8 ECC code check, the clean information digit that can be stored in the page or leaf is 14,784.Adopt 13/16 low ECC code check, the clean information digit that can be stored in the page or leaf is 13,728.Yet second kind of stored configuration is but owing to stronger ECC has more robustness.

Alternatively, the quantity of the voltage level of each storage unit can change to another stored configuration to some extent from a stored configuration, and also, K and M all change.For example, the following three kinds of stored configuration in the array of 4,224 storage unit pages or leaves, using of having expressed:

The voltage level of each storage unit	The bit of each cell stores	The ECC code check	K	M	The clean information bit of each cell stores
The voltage level of each storage unit	The bit of each cell stores	The ECC code check	K	M	The clean information bit of each cell stores	16	4	7/8	14,784	16,896	3.5
12	3.5	13/14	13,728	14,784	3.25	16	4	7/8	14,784	16,896	3.5
12	3.5	13/14	13,728	14,784	3.25	12	3.5	6/7	12,672	14,784	3

In some embodiments, each page is divided into the sector with constant clean information digit.The quantity difference of the sector of each page.For example, the following three kinds of stored configuration in the array of 4,224 storage unit pages or leaves, using of having expressed.In current example, each sector comprises 1,412 clean information bit with 2/3 code check ECC coding, to produce 2,118 stored bits.

Every valve district	K	M	The level of each storage unit	The bit of each cell stores
Every valve district	K	M	The level of each storage unit	The bit of each cell stores	8	11,264	16,896	16	4
7	9,856	14,784	12	3.5	8	11,264	16,896	16	4
7	9,856	14,784	12	3.5	6	8,448	12,672	8	3

Use the capacity estimation of program/erase history

As mentioned above, the degree of distortion in a concrete storage unit 32 can be depending on the history of elapsed programming of this element and erase operation.Thereby MSP 52 will have the stored configuration of low storage density usually and distribute to older storage unit, and vice versa.

In some cases, distortion is that leakage current by storage unit is caused.Be described in " Recovery Effects in the DistributedCycling of Flash Memories " that the leakage current effect for example is to deliver on the IEEE Annual International Reliability Physics Symposium journal 29-35 page or leaf that the San Jose city holds in March, 2006 by people such as Mielke, it includes this paper in to quote mode herein.According to this paper, the timing period of dielectric breakdown between circulation that is caused by programming and erase cycles partly recovered.This paper has been described about the anti-effect of catching this type of delay of data maintenance mechanism of electric charge.Thereby the degree of distortion relevant with leakage current depended on elapsed time length since previous programming and erase operation.The distortion of other kinds also may be subjected to the influence of charge-trapping, thereby is subjected to the nearest programming and the influence of erase operation.For example, in the storage unit of the charge-trapping with comparatively high amts, the degree of disturbance mistake can increase.

Figure 11 is the process flow diagram that schematically shows according to the method for a kind of storage density of revising memory device 24 adaptively based on the programming and the history of erase operation of one embodiment of the invention.The method starts from 76 pairs of programmings of carrying out of administrative unit of MSP 52 on the different storage unit 32 of array 28 and the number of times of erase operation keeps a record.Described MSP can keep following the trail of the operation counter of current time, so that programming and erase operation are added time tag.Alternatively, in some cases, time tag is provided by Memory Controller 22.

Because programming operation is normally carried out page by page, and erase operation is to carry out on whole erase block, so MSP can write down the programming and the erasing times of each page.This information can be used as each page stored configuration a part and be stored in the stored configuration table.Can store the erasing times of every page or each erase block.

Leaking estimating step 234, MSP52 estimates the leakage current in a concrete page or leaf.Described MSP can use different estimators and standard to estimate leakage current based on the programming and the erasing times of record.For example, leakage current can be by following Function Estimation:

I_{Leakage} = a_{0} \cdot CurrentTime + Σ_{n = 1}^{K} a_{i} ProgramTime (n)

Wherein ProgramTime (n) is illustrated in the time of the n time programming operation that this page go up to carry out, such as top step 230 record.Residing time when CurrentTime represents the calculating of estimation quilt.α _0...KThe expression weighting coefficient, the programming operation that it typically is comparatively recently distributes higher weight.When for i〉1 and α _i=0 o'clock, then described estimation was only based on programming operation last time.

In an alternative embodiment, can estimate leakage current based on the number of times of the erase operation of carrying out in (for example, within the previous day, last hour or last minute) within certain time interval.In addition as an alternative, leakage current can be estimated iteratively, for example uses function

I _Leakage(n+1)＝(1-δ)·I _Leakage(n)+

δ·[ProgramTime(n+1)-ProgramTime(n)]

Wherein weighting coefficient or " forgetting factor " are represented in 0＜δ＜1.This type of iteration estimates to allow MSP52 only to write down the time and the previous value of estimating of twice programming operation, rather than the tabulation of storing a plurality of time tags.

Alternatively, described MSP can use any other method of estimation, so that estimate leakage current based on the log history of programming and erase operation.

In some embodiments, in additional distortion estimating step 238, described MSP is based on other factor assessment of memory cell distortions.Distortion is estimated can be based on to from the measurement of the cross-couplings ratio of consecutive storage unit or based on other suitable processes arbitrarily.

Described MSP will estimate and estimates carry out combination in the distortion that above-mentioned steps 238 is carried out, in capacity estimation step 242, estimate the capacity of page or leaf at the leakage current that above-mentioned steps 234 is carried out.For example, can use following Function Estimation capacity:

Capacity＝C ₀+β·I _Leakage+γ·DistortionEstimate

C wherein ₀Expression baseline capability value, and β and γ represent the relative weighting of expectation is distributed to the weighting coefficient that leakage current and distortion are estimated, in some embodiments, step 238 can be omitted, and described MSP can only estimate a page capacity based on leakage current, for example by setting γ=0.

MSP 52 adopts the page or leaf capability value that has upgraded to come the updated stored allocation list.Described MSP can use any suitable method, and method for example mentioned above is determined at page or leaf density of this page and suitable stored configuration (for example, ECC and voltage level quantity).

The density distribution that has every unit decimal bit value

In some embodiments, MSP 52 can define the stored configuration with every unit non-integer bit number.For example, can not that a plurality of voltage levels of 2 power increase storage density and approach the accessible capacity of storage unit by using in some cases.When every cell bit number was not integer, MSP 52 can use diverse ways so that data bit is mapped to voltage level.

If K represents to be used for the quantity with the voltage level of data storage in a concrete page or leaf.K is 2 power not necessarily, so storage density must not be an integer yet.The bit number of the maximum that can be represented by K level is by n _Opt=log ₂(K) provide, it is non integer value normally.In order to reach this best storage density, need in the storage unit of unlimited amount, store the data bit of unlimited amount, and this process will cause unlimited delay.Yet, under actual conditions, can exchange departing from for increasing processing delay (also promptly, being used to store the quantity of the storage unit of data) apart from best storage density.

If n _cExpression is used to store the quantity of the storage unit of data, and n _TbExpression is stored in this n _cThe sum of the bit in the individual storage unit.n _cAnd n _TbBe round values.Thereby storage density is by n _Bpc=n _Tb/ n _cProvide.n _TbAnd n _cShould be chosen and feasible by n _Gap=n _Bpc-n _OptWhat provide is non-negative and minimum apart from departing from of optimum density.Increase n _cMake n _BpcCan approach n _Opt, but can increase mapping complex degree and processing delay.

Select n _cAnd n _TbExpectation value after, MSP 52 is with every group of n _TbIndividual data bit is mapped to n _cIndividual voltage, then this n _cIndividual voltage is written into n _cIn the individual storage unit.This n _TbIn the individual voltage each all can adopt in K the possibility level.N herein _TbIndividual data bit is represented as b ₁...,

b_{n_{tb}} &Element; {0,1} .

In some embodiments, MSP 52 passes through n _TbIndividual bit binary number is expressed by the bit based on K, with this n _TbIndividual data bit is mapped to n _cIndividual voltage.That is to say that MSP 52 determines n _cIndividual coefficient k ₁...,

k_{n_{c}} &Element; {0, . . ., K - 1},

So that

b_{n_{tb}} \cdot 2^{n_{tb} - 1} + b_{n_{tb} - 1} \cdot 2^{n_{tb} - 2} + . . . + b_{2} \cdot 2 + b_{1} =

k_{n_{c}} \cdot K^{n_{c} - 1} + k_{n_{c} - 1} \cdot K^{n_{c} - 2} + . . . + k_{2} \cdot K + k_{1}

MSP 52 is with value k then ₁..., To this n _cIndividual storage unit is programmed.

For example, establish K=11.Best storage density n in the case _Opt=log ₂(11) ≈ 3.4594.Tentation data is written into n _cIn the group of=3 storage unit, then apart from departing from of optimum density be n _Gap≈ 0.1261 and n _Tb=10.Thereby the sequence of being made up of ten data positions is mapped to the group of being made up of three storage unit, and each group is used 11 voltage levels.For example, bit sequence " 1101100100 " is mapped to k ₁=7, k ₂=1 and k ₃=10.

Storage and obliterated data in the variable-displacement memory device

Figure 12 is a kind of process flow diagram that is used in variable-displacement memory device data storing method that schematically shows according to one embodiment of the invention.At input step 250, the method starts from MSP 52 and accepts to be used for stored data items from Memory Controller 22.

In some embodiments, Memory Controller is specified a certain reliability requirement at storing data item.Memory Controller can use any suitable method or form, to specify the memory reliability of being asked, for example by clearly specifying maximum to allow error probability or pass through to select a reliability step from a series of predetermined reliability steps.Normally but optionally, reliability requirement is to be associated with the fault tolerant degree of the application that generates described data item.For example, can under low relatively reliability step, store the file that comprises the audio or video medium.And on the other hand, be generally the file and the operating system data file that comprise program code and specify higher reliability step.

Additionally or alternatively, Memory Controller can be specified a certain maintenance requirement that is used for storing data item.The time period that described maintenance requires the expression data item to be supposed to store.For example, can specify low retention time section for interim operating system file.

Select step 254 at page or leaf, MSP 52 selects by the one or more page set of forming of wherein waiting to want storing data item in the array 28.Usually, administrative unit 76 is followed the trail of the state of each storage page.Each page or leaf can have " wiping " (also promptly, can be used for programming), " comprising information ", " flaw is arranged " or " preparation is wiped ".As mentioned above, unit 76 also remains on the stored configuration of using in each page (also being voltage level quantity and ECC), and its definition can be in the data volume of page or leaf stored.

The set of one or more " wiping " page or leaf is selected in unit 76, and its overall dimensions is enough to store described data item.In some embodiments, unit 76 P-SCANs " are wiped " page or leaf, and page or leaf selected, and are enough to storing data item up to the overall dimensions of page or leaf.Alternatively, unit 76 can be applied to different strategies or criterion the selection to page or leaf.

For example, the programming of less number of times and the page or leaf of erase cycles can be selected to have experienced in unit 76, so that realize better wear leveling in whole array 28.Again for example, unit 76 can be searched for its overall dimensions and provide to the page or leaf set of (also promptly, surpassing the data item size less) of the immediate coupling of described data item as far as possible, so that minimize the quantity of untapped storage unit.Again for example, unit 76 can provide preferably for the high power capacity page or leaf, so as between the page or leaf of minimum number partition data, and reduce programming time, loss and administration overhead.Alternatively, when the page or leaf selecting to be used to store, unit 76 can use other criterions that are fit to or criterion combination arbitrarily.

In some embodiments, unit 76 is based upon the reliability of data item appointment and/or keeps requirement, revises the stored configuration (and storage density thus) of page or leaf.For example, when data item has relatively low reliability and/or maintenance when requiring, unit 76 can come storing data item in having the storage unit of higher distortion and/or with density higher for the degree of distortion of storage unit with store data items.

At storing step 258, MSP 52 with store data items in selected page or leaf.The state of the page or leaf that unit 76 will be used to store is arranged to " comprising information ", and the stored configuration on the refresh page then if necessary.Unit 76 also writes down the sign of the page or leaf that is used for storing data item, so that when after this system 20 is requested to take out described data item, these pages or leaves can be addressed.

In some embodiments, can be by the available memory-size of Memory Controller 22 Request System, 20 reports.In these embodiments, unit 76 will be labeled as the capacity summation of the page or leaf of " wiping ", and this result is reported as existing memory-size.

Figure 13 is according to one embodiment of the invention, schematically shows a kind of being used for from the process flow diagram of the method for variable-displacement memory device obliterated data.In removal request step 270, described method starts from the request of from memory device 24 deleting a certain data item of MSP 52 acceptance from Memory Controller 22.In deletion step 274, administrative unit 76 identifications among the MSP 52 are used for the page or leaf of storing data item, and they are labeled as " preparation is wiped ".

The page or leaf of storing described data item can be positioned among one or more erase blocks.Before these pieces can be wiped free of, the page or leaf of (also promptly, having " comprising information " state) that uses any in these pieces should be relocated to other erase blocks.

In use check step 278, unit 76 checks whether the erase block that has comprised the page or leaf that above-mentioned steps 274 discerned comprises the page or leaf in the use.If erase block does not comprise the page or leaf in any use, then at erase step 282, unit 76 wipe described and with in these pieces the page or leaf state be updated to " wiping ".On the other hand, if the page or leaf that unit 76 detects in the piece that some plans wipe still is among the use, then it will be stored in data relocation other pages or leaves outside the piece of planning to wipe in these pages.(in some cases, for example when erase block comprised the single page or leaf that belongs to obliterated data item and every other page or leaf and all wiped, unit 76 can determine not wipe this piece.)

Select step 286 in reorientation, unit 76 is selected by the one or more pages of set of forming, and these pages are positioned at outside the piece of planning to wipe, and its overall dimensions is enough to store the data in the page or leaf that is using.Unit 76 can be according to any suitable strategy or criterion, the page or leaf of selecting data to be relocated to.For example, can from available page or leaf, select above-mentioned page or leaf according to sequencing.As an alternative, unit 76 can select described page or leaf promoting wear leveling or to reduce the quantity of untapped storage unit, selects described in the step 254 as the page or leaf of the method for above-mentioned Figure 12.Also as an alternative, unit 76 can use any other criterion that is fit to.

In reorientation step 290, the data that unit 76 will be stored in the page or leaf that is using copy at above-mentioned steps 286 selected pages or leaves.Notice that the reorientation operation must not keep the quantity of page or leaf or the subregion that data become page or leaf.Because the page or leaf in the equipment 24 has different capacity, the data of reorientation can be copied in the page or leaf of varying number and/or with the mode different with the initial storage mode by subregion between page or leaf.In case data are by reorientation, then at erase step 282, the piece that is identified in above-mentioned steps 274 promptly is wiped free of.

Data storage management in the variable-displacement memory device

As mentioned above, MSP 52 and Memory Controller 22 are mutual, also, accept data that are used for storing and the data that are stored in storer when being requested to described Memory Controller output from described Memory Controller.System 20 can adopt several means and Memory Controller is mutual or common and host computer system is mutual, and these modes differ from one another on the management function level of being carried out by described MSP.

Under a kind of extreme situation, system 20 and old-fashioned Memory Controller are mutual, and this old-fashioned Memory Controller is designed to control the memory device of fixed capacity.In the case, Memory Controller is kept the page table of a fixed capacity, and which fixed capacity page or leaf it indicates be used to store each data item.The page table of fixed capacity also can keep the state of each fixed capacity page or leaf or piece, and indicates certain erase block whether to be considered to bad piece.

In these embodiments, MSP 52 is by keeping two parallel index schemes, plays instrumentality between the fixed capacity characteristic of the adaptive capacity characteristic of system 20 and Memory Controller 22.Described MSP uses the index scheme of fixed capacity page or leaf to communicate by letter with Memory Controller, like this, and system 20 fixed capacity equipment seemingly for Memory Controller.In system 20 inside, MSP 52 efficiently with store data items in the variable-displacement page or leaf.Described MSP keeps the independent index scheme of variable-displacement page or leaf, and which variable-displacement page or leaf its indication uses store each data item.When write data and read data, described MSP can change between two kinds of index schemes.

In some cases, Memory Controller 22 is also carried out such as the ECC Code And Decode, is being read in the data of storer the function that detects mistake and/or the bad block management.Use technology described herein, known Memory Controller can be used to control store equipment 24 and needn't revise their data structure or agreement.

Under another extreme situation, the function of Memory Controller 22 self is realized by MSP 52 substantially.In these embodiments, described MSP accepts the data item of arbitrary dimension from host computer system (for example from computer CPU), and with described store data items in the variable-displacement page or leaf of array 28.Because by MSP execute store management function, thus there is no need to imitate the fixed capacity index, and described MSP only keeps an index scheme.

In addition as an alternative, MSP 52 can be supported in the division of any other memory management functions that is fit between system 20 and the host computer system.Single MSP equipment can be supported different interfaces and index scheme, so that mutual with dissimilar Memory Controller or main frame.

Figure 14-the 17th schematically shows the synoptic diagram that is used for storing at the variable-displacement memory device method of fixed size block of data according to embodiment of the present invention.

Figure 14 shows a kind of and the mutual method of Memory Controller, and it is designed to store data in the memory device of the erase block of the storage unit with fixed qty, and it carries out bad block management (BBM) function.In some known BBM methods, even if having only a page or leaf that flaw is arranged in certain erase block, this erase block also is classified as bad piece.These class methods very do not have efficient, because most storage unit is still available in bad piece.On the other hand, use the method for Figure 14, system 20 stores data efficiently in the storage available of the piece that is classified as bad piece.

In typical write operation, Memory Controller 22 is accepted data item 300 so that be stored in the storage array 304.Array 304 comprises a plurality of storage blocks 308.Memory Controller 22 is divided into the piece of one or more fixed measures with described data item, and these pieces are called as controller block 312.Each controller block 312 is designated as and is stored among certain storage availability piece 308.Controller block 312 is offered MSP 52 to Memory Controller 22 so that storage.

Owing to distortion effect, make flaw or other any reasons, some in the piece 308 have the capacity that reduces (also promptly, have less than controller block 312 sizes capacity).Use known BBM method, even if the overwhelming majority of the storage unit of such piece is still available, it still has been classified as bad piece, and keeps abandoning.

On the other hand, MSP 52 is considered as the variable-displacement piece with all storage blocks 308, and piece has not been divided into piece or bad piece.Extract data in the described MSP slave controller piece, and described data are rezoned into a plurality of fragments 316, these fragments can have same size or different size.Described MSP identifies the piece that the size of a plurality of its capacity and fragment 316 is complementary, and with each fragments store among corresponding storage block.In current example, described MSP is divided into three fragments with this data item, and with fragments store in the storage block that is labeled as #3, #6 and #10.

MSP 52 can use diverse ways and standard to determine the piece of each data item of storage.For example, described MSP can search for a pair of storage block of the capacity with reduction, and its total volume is enough to store the data of single controller piece.Described then MSP is mapped to described a pair of storage block with controller block.Again for example, described MSP can search for available storage block, and definite set of being made up of two or more pieces 308, the size optimum matching of its total volume and data item 300.

As an alternative, but described MSP can search for the set of the piece of the wherein storing data item with minimum number, so that reduce administration overhead.Be further used as alternatively, described MSP can select to experience the nearest programming of minimum number and the piece of erase cycles, so that improve wear leveling.Also can use other any suitable method or criterions.In some embodiments, single storage block 308 can be used to store the fragment that belongs to more than a data item.

With data item 300 subregions is fragment 316, and can independently carry out also can be in conjunction with the selection of storage block 308 is carried out.For example, described MSP can at first turn to the data item fragment fragment of fixed measure, no matter and how will finally store the quantity of storage block of these fragments and sign.Alternatively, described MSP can at first want the storage block of storing data item to discern to wherein waiting, according to the quantity and the size of these storage blocks data item is carried out fragmentation then.

In some embodiments, the storage of MSP 52 in described Memory Controller simulation fixed capacity piece so that the fragmentation of carrying out by described MSP for Memory Controller and BBM function thereof for transparent.For example, described MSP can keep two concordance lists, also, and the concordance list of the variable-displacement storage block of the concordance list of a fixed measure controller block and a correspondence.When data item is sent by described Memory Controller so that when being stored in certain set of controller block, which variable-displacement storage block described MSP indicates be used to store described data item.When described data item during by described Memory Controller request, described MSP takes out this data item from the variable-displacement storage block that stores this data item, and send in the described Memory Controller described, be stored among the controller block for the known fixed size of described controller as this.

Be appreciated that with respect to known BBM method, the method for Figure 14 has obviously increased the accessible capacity of memory device, reason is that its permission is being categorized as data storage in the storage block of bad piece by additive method.

Though the instructions of Figure 14 relates to the storage granularity of whole erase block, this method also can use meticulousr storage granularity to realize, for example, and the page or leaf granularity.In other words, described MSP can determine wherein a suitable set of variable-displacement storage page that can storing data item.Come fragmentation and storing data item based on page or leaf one by one, just permission is that cost realizes higher storage density with high relatively administration overhead.

In an exemplary realization, when being the P bit by the employed nominal page size of described Memory Controller, described MSP is categorized into capacity less than the storage page of the reduction capacity of P and the capacity nominal capacity storage page more than or equal to P with the storage page in the described memory device.The controller page or leaf that described then MSP can have each the P bit is stored in the nominal capacity storage page, perhaps is stored in the storage page of a pair of reduction capacity.Described MSP typically keeps a table, and this table is mapped to the corresponding nominal capacity storage page or the storage page of a pair of reduction capacity with each controller page or leaf.Thereby the storage page that its capacity is lower than the nominal size of storage page still can be used for storing data.

Figure 15 shows controller page or leaf according to the fixed measure that will have the P bit effectively of one embodiment of the invention and is stored in another kind of method in the variable-displacement storage page.Storage array 320 comprises a plurality of storage pages 324.Storage page is defined as one group of storage unit of being programmed simultaneously and reading.

Though the storage page of array 320 has the storage unit of equal number usually, their capacity (being their canned data amounts reliably) can change in time according to the page or leaf difference.Usually, the capacity of each storage page 324 can less than, be equal to or greater than P.MSP 52 is assigned as one or more storage pages as exceeding volume capacity page or leaf 328, and it is used to memory capacity and exceedes the volume bit less than other storage pages of P.In current example, array 320 comprises 32 storage pages, and one of them page or leaf is as exceeding volume capacity page or leaf.

The controller page or leaf of accepting to have P bit as described MSP is when storing, and the capacity that it assesses next available storage page 324 is labeled as Cn.If Cn〉P (also promptly the capacity of next available storage page is enough to store P bit of described controller page or leaf), so described MSP with a described P bit storage in storage page.If P the bit of the off-capacity of the storage page that next is available to store described controller page or leaf, also be, when Cn≤P, then described MSP with Cn bit storage in the described P bit among storage page, and with a remaining P-Cn bit storage among the untapped storage unit that exceedes volume capacity page or leaf 328.

Note, use said method may relate to write or read operation two pages or leaves to the write or read of a page or leaf.In some embodiments, described MSP can will exceed some or all of volume capacity page or leaf, and perhaps the part of these pages is buffered in RAM or other memory buffer.Exceed the volume page or leaf by buffer memory, described MSP can reduce two reading and the number of times of two write operations.

When from described memory device sense data, described MSP can read last time exceedes volume capacity bit buffer memory.When taking out a storage page, described MSP checks exceeding the volume bit and whether being present in the data in buffer of described page or leaf.If the volume bit that exceedes of expectation is buffered, then they can be affixed to the storage page that is taken out, and exceed volume capacity page or leaf and needn't physically read.When memory device writes data, described MSP can buffer memory exceedes volume capacity bit and they comparatively physically is not stored in the described memory device continually.

Data cached in order to prevent to lose under the situation of voltage failure, described MSP can comprise the identification electric voltage exception and the circuit of memory buffers data apace where necessary.The order that described Memory Controller also can use the end of file (EOF) attribute or other to be fit to, indicate described MSP with the data storage that is buffered in described memory device.Memory Controller uses this order usually before powered-down and/or in the write data end of file.Also as an alternative, described MSP also can be stored in data in buffer in the storer through after certain period.

Figure 16 shows a kind of method that substitutes of storing the controller page or leaf of fixed measure at the variable-displacement storage page effectively that is used for according to one embodiment of the invention.In the method for Figure 16, MSP 52 is stored in controller page or leaf (being labeled as controller page or leaf #1...#5) in the variable-displacement storage page 334 of storage array 330, and wherein each controller page or leaf all has P bit.The capacity of each storage page 334 can less than, be equal to or greater than P.

MSP 52 is the memory controller page or leaf one by one, and does not consider the border of storage page 334.Thereby a certain storage page can comprise the data that belong to one or more controller pages or leaves, and the data of a certain controller page or leaf can be stored in one or more storage pages.Described MSP for example by the starting and ending address of each controller page or leaf of storage, writes down each controller page or leaf position in array.This storage means is a cost with some administration overheads, thereby has utilized the entire capacity of storage page.

Above-mentioned storage means is transparent for Memory Controller usually.When a certain controller page or leaf of Memory Controller request, described MSP reads the controller page or leaf of being asked and described data is sent to described controller from suitable memory location.

In some cases, for example when storage larger data file or digital picture, described Memory Controller sends the sequence of successive control device page or leaf for storage.Under these circumstances, described MSP can reduce the number of times of the page or leaf programming operation of physics by the data of buffer memory from described Memory Controller acceptance.For example, when impact damper when full, when being subjected to Memory Controller and clearly indicating (for example in response to the EOF order), or when the Memory Controller transmission did not constitute the controller page or leaf of a part of described sequence, described MSP physically write described storage array with described data.Spendable for this purpose a kind of exemplary command is " caching of page programming (PageCache Program) " order, defines in its ONFI specification of quoting in the above.Described MSP also can take from the data of storer by cache read, thus reduce read the mass data that is stored in proper order in this storer required read page operations.

Figure 17 shows the method for storing the controller page or leaf of fixed measure according to the another kind of another embodiment of the invention in the variable-displacement storage page effectively.In the method for Figure 17, described MSP is the writing controller page or leaf in two stages, to accelerate program speed.

The storage page of storage array 340 is divided into temporary storage area 344 and permanent storage area 348.When described MSP when Memory Controller is accepted the controller page or leaf, it initially writes them the storage page that separates in the zone 344, so that each controller page or leaf is written in the single memory page or leaf.

At later time point, typically, when being idle with communicating by letter of Memory Controller, described MSP is reprogrammed to data in the permanent storage area 348.Data in the zone 348 are stored with the tight compression among top Figure 16, capacity high-efficiency method.The page or leaf that has been reprogrammed in the zone 344 is released, and can be used further to the interim storage of follow-up controller page or leaf.

Wear leveling is considered

Degree of distortion in concrete page or leaf depends on elapsed programming of this page and the number of times of wiping usually.Typically, Ye performance and capacity experience increasing programming and number of erase cycles along with it and worsen.Thereby, often advantageously, the programming of storage page is distributed, so that degenerating, programming in whole storage cell array, evenly distributes.This feature is called as wear leveling, and for example be described in by STMicroelectronics (being arranged in Geneva, Switzerland) " the Wear Leveling in SingleLevel Cell NAND Flash Memories " at Application note AN-1822 in February, 2007, this article is included this paper in to quote mode herein.

When MSP 52 selected wherein will to write a page or leaf of data or one group of page or leaf, described MSP can select one or one group to experience the programming of less relatively number of times and the page or leaf of erase cycles.Such wear leveling is considered to be used for above-mentioned any method.

In some cases, described MSP can be based on selecting page or leaf with the tolerance of wear leveling and distortion estimation combination, for example

Tolerance=γ writes erase cycles number+δ distortion and estimates

Wherein γ and δ represent weighting coefficient.The degree of distortion that expression is estimated is estimated in distortion.For example, the distortion estimation can be counted by the storage unit that voltage has significantly been descended and obtain.Can be added to and to another factor in the definition of above-mentioned tolerance be, elapsed time since the last time of this piece erase operation (is similar in the description of Figure 11 above and defines I _LeakageFormula).

Though embodiment described herein relates generally to by revising voltage level quantity and the ECC scheme storage density with the adaptive multi-layer storage unit, method and system described herein also can be used for the individual layer storage unit by only changing ECC.

Though embodiment described herein mainly pays attention to take out data from solid storage device, principle of the present invention also can be used for storage and taking-up data from hard disk drive (HDD) and other data storage mediums and equipment.In some memory devices such as HDD and numerical tape, before the storage data, storage medium is not divided into discrete storage unit in advance.On the contrary, data are stored in the zone of continuous medium, and the position of these zones in continuous medium is defined as himself a part of storing process.In the context of present patent application and in claims, this type of zone that defines during the storing process in being inferred as continuous medium also is regarded as " analog memory cell ".

Therefore should be appreciated that embodiment as described above is only carried out example and quoted, and an embodiment that the invention is not restricted to above institute and specifically illustrate and describe.In contrast, scope of the present invention comprises above-mentioned each combination of features and sub-portfolio, and the wherein not variation and the modification of disclosure in the prior art that can make after reading above-mentioned explanation of those skilled in the art.

Claims

1. method that is used for carrying out data storage at storer, this storer comprises a plurality of analog memory cells, described method comprises:

2. method according to claim 1, wherein storing data comprises and uses error correcting code (ECC) that described data are encoded, coded data is converted to the analogue value in the set that is selected from a nominal analogue value and the described analogue value write corresponding storage unit, and wherein each stored configuration is specified corresponding ECC code check and is used to store the size of set of the described nominal analogue value of described data.

3. method according to claim 1, wherein, for each analog memory cell, the storage data comprise data-switching is become to be selected from the analogue value in the set of a nominal analogue value and the described analogue value write described storage unit, and wherein each stored configuration is specified the nominal analogue value that is used in the described data of described analog memory cell storage.

4. method according to claim 1, wherein storing data comprises described data-switching is become the analogue value, and the described analogue value is write in the corresponding storage unit, and estimate wherein that accessible memory capacity comprises the corresponding degree of distortion of the analogue value that influences write storage unit is estimated, and determine accessible memory capacity in response to described degree of distortion.

5. according to each described method among the claim 1-4, wherein the distortion estimator degree comprises from described storage unit and reads the described analogue value, and estimates described degree of distortion based on the described analogue value that reads from described storage unit.

6. method according to claim 5, wherein the distortion estimator degree comprises from reading from the analogue value of described storage unit and comes the described data of reconstruct, and calculates described degree of distortion based on the data of institute's reconstruct.

7. method according to claim 5, wherein the calculated distortion degree comprises reading the scalar function summation from the analogue value of described storage unit.

8. method according to claim 7 wherein comprises in response to described data reading from the analogue value of described storage unit and being stored in square summation of the difference between the corresponding expectation value of the data in the described storage unit the summation of described scalar function.

9. method according to claim 6, wherein the calculated distortion degree comprises the quantity of following storage unit is counted, in this storage unit, read from the analogue value of described storage unit and the difference that is stored between the corresponding expectation value of the data in the described storage unit and surpass a predetermined value in response to described data.

10. method according to claim 4 is wherein stored data and is comprised the described analogue value is write described storage unit, and uses the programming and the checking (P﹠amp of iteration; V) process is verified the analogue value that has write, and wherein the distortion estimator degree comprises based on by described P﹠amp; The analogue value of V process verification is calculated described degree of distortion.

11. method according to claim 4 is wherein stored data and is comprised programming and the checking (P﹠amp that the described analogue value is write described storage unit and use iteration; V) analogue value that write of process verification, this process is by the programming step described analogue value of increment iteratively, and the definition of wherein said stored configuration is by the P﹠amp of described iteration; The size of the programming step that the V process is used.

12. according to each described method among the claim 1-4, wherein storing data comprises data error correcting code (ECC) coding for the treatment of to be stored in one group of storage unit, and coded data converts the analogue value to be used for being stored in the corresponding analog memory cell of this group storage unit, estimate wherein that accessible memory capacity comprises that storage unit from described group reads the described analogue value and to estimating, and wherein revise stored configuration and comprise stored configuration in response to adaptive this group storage unit of the distance metric of being estimated between the analogue value that is read and the distance metric that approaches most between the effective ECC code word of the described analogue value.

13. according to each described method among the claim 1-4, wherein reappraise accessible memory capacity and comprise and read the data that are stored in the described storage unit, and wherein revise stored configuration and comprise in response to the detection mistake in the data that read and come adaptive described stored configuration.

14. method according to claim 13 wherein stores data and comprise and use error correcting code (ECC) that data are encoded, and wherein adaptive described stored configuration comprises the code check of revising ECC.

15. according to each described method among the claim 1-4, wherein the accessible capacity of assessment of memory cell comprises the previous programming that is applied to corresponding storage unit and erase operation is followed the trail of and estimate described accessible capacity in response to previous programming of having followed the trail of and erase operation.

16. method according to claim 15 is estimated wherein that accessible capacity comprises in response to the length of the time period that has passed to calculate accessible capacity since previous programming and erase operation.

17. according to each described method among the claim 1-4, wherein store data and comprise that the initial part with described data converts the analogue value to and the described analogue value is write corresponding storage unit, and be written to the analogue value of described storage unit and do not wipe this storage unit by increase subsequently, and the other part of described data is stored among at least some of described storage unit.

18. according to each described method among the claim 1-4, wherein storing data comprises and uses the error correcting code (ECC) that increases redundant digit for described data that data are encoded, and described redundant digit is stored in some analog memory cells, and wherein revises stored configuration and comprise and revise a plurality of redundant digits that increase by described ECC and do not wipe described storage unit.

19. method according to claim 18, wherein the storage redundancy position comprises and the described redundant digit of described data separating ground storage.

20. according to each described method among the claim 1-4, wherein the memory allocated configuration comprises the set of a possible stored configuration of predefine, and wherein revises the stored configuration that stored configuration comprises that selection is upgraded from described predefined set.

21., wherein specify the non-integral bit number in every unit by the defined described data volume of at least one described stored configuration according to each described method among the claim 1-4.

22., wherein store data and be included in and data compressed before the data write storage unit, and the definition of wherein said stored configuration will be compressed the corresponding ratio of compression that is adopted to data according to each described method among the claim 1-4.

23. according to each described method among the claim 1-4, wherein the memory allocated configuration is included as the respective sets definition stored configuration of described storage unit.

24. according to each described method among the claim 1-4, wherein the storage data comprise the data item of accepting to be used for being stored in described storer in described storage unit, the select storage unit subclass to be storing described data item in response to the stored configuration of being distributed therein, and with described store data items in selected storage unit subclass.

25., wherein reappraise accessible memory capacity and be in the free time of described data not being stored and reading and carry out during the section according to each described method among the claim 1-4.

26., wherein distribute and revise stored configuration to comprise described stored configuration is stored in the allocation list according to each described method among the claim 1-4.

27. method according to claim 26, be included in be installed in storer in the host computer system before, in described stored configuration table the storage described stored configuration initial value.

28., wherein distribute and revise stored configuration to be included in the data volume that is stored in the described storage unit and to estimate to keep between the accessible capacity predetermined nargin accordingly according to each described method among the claim 1-4.

29. according to each described method among the claim 1-4, wherein at least some distortions are caused by the leakage current in the described analog memory cell, and wherein distortion estimator comprises the estimation leakage current.

30. a method that is used for carrying out at storer data storage, this storer comprises a plurality of analog memory cells, and described method comprises:

The degree of distortion of estimation among corresponding analog memory cell;

31. a method that is used for carrying out at storer data storage, this storer comprises a plurality of analog memory cells, and described method comprises:

Acceptance is used for being stored in the data of described storer;

With described data storage in the storage unit of described subclass.

32. method according to claim 31 wherein selects subclass to comprise the storage unit of the big or small optimum matching of the data of selecting its accessible total volume and being accepted.

33. method according to claim 31 is wherein accepted data and is comprised the reliability step of accepting to be used to store the requirement of described data, and wherein selects subclass to comprise in response to desired reliability step and select described storage unit.

34. method according to claim 31 is wherein accepted data and is comprised the desired maintenance phase that is used to store described data of acceptance, and wherein selects subclass to comprise in response to the desired maintenance phase and select described storage unit.

35. method according to claim 31 wherein selects subclass to comprise that selection has the storage unit of low distortion with respect to other storage unit.

36. method according to claim 31, wherein follow the trail of accessible memory capacity and comprise the previous programming and the storage operation that are applied to described storage unit are followed the trail of, and wherein select subclass to comprise and come select storage unit in response to previous programming and erase operation.

37. method according to claim 36, wherein select subclass to comprise and have the previous programming of less number of times and the storage unit of erase operation with respect to other storage unit in the described storer, a plurality of programmings and erase operation are evenly distributed in the described storage unit by being chosen in.

38. according to the described method of claim 37, the number of times of wherein distribute programming and erase operation comprises being chosen in the predetermined nearest time period carries out the previous programming of less number of times and the storage unit of erase operation with respect to other storage unit.

39. method according to claim 31 is wherein followed the trail of accessible memory capacity and is comprised by the accessible capacity summation to the storage unit that can be used for storing data, calculates the size of available storage space and reports to described host computer system.

40. method according to claim 31, wherein said storer is divided into a plurality of erase blocks, each erase block is included in one group of storage unit of wiping in the single erase operation, and described method also comprises obliterated data item from described storer in the following way:

Identification stores one or more erase blocks of described data item;

Wipe the erase block that stores described data item.

41. method according to claim 31, the data of wherein accepting to be used to store comprise with the data of fixed capacity piece acceptance from host computer system, and based on the accessible capacity of the variable capacity group of being followed the trail of, with described data storage in the variable capacity group of described storage unit.

42. according to the described method of claim 41, the storage data comprise two or more its capacity of identification less than the variable capacity group of the capacity of fixed capacity piece in the variable capacity group, and will be received in data storage in one or more fixed capacity pieces in two or more variable capacity groups of being discerned.

43. according to the described method of claim 41, wherein the storage data comprise that with one or more variable capacity set of dispense be as exceeding the volume memory storage area in the variable capacity group, to be received in data storage in the fixed capacity piece in corresponding variable capacity group, and, when the accessible capacity of a variable capacity group during, in the data that are received in the corresponding fixed capacity piece some are stored in exceeding in the volume memory storage area of being distributed less than the capacity of described fixed capacity piece.

44. according to the described method of claim 41, wherein the storage data comprise that the data that will be received in the fixed capacity piece are stored in the described storage unit sequentially in the variable capacity group, and and the border between the variable capacity group irrelevant.

45. according to the described method of claim 44, wherein storing data comprises, initially will be received in data storage in each fixed capacity piece in corresponding variable capacity group, and subsequently to the data of initial storage reprogramming in proper order, and and the border between the described variable capacity group irrelevant.

46. according to the described method of claim 41, also comprise and from described variable capacity group, take out described data, the described fixed capacity piece of reconstruct, and use described fixed capacity piece to described host computer system output data.

47. method according to claim 31 also comprises by in the described data of buffer memory at least some, reduces the number of times of the memory access operations that is applied to described storer.

48.,, just the data that are buffered are sent to described storer in case wherein at least some in the described data of buffer memory comprise and detect instantaneous storage incident according to the described method of claim 47.

49. according to the described method of claim 48, wherein said instantaneous storage incident comprises power fail on the horizon, overtime and acceptance at least one incident in the incident of the end of file (EOF) order of described host computer system of being selected from.

50. a data storage device comprises:

51. according to the described device of claim 50, wherein said MSP is arranged to and uses error correcting code (ECC) that described data are encoded, coded data is converted to the analogue value in the set that is selected from a nominal analogue value and the described analogue value write corresponding storage unit, and wherein each stored configuration is specified corresponding ECC code check and is used to store the size of set of the nominal analogue value of described data.

52. according to the described device of claim 50, wherein, for each analog memory cell, described MSP is arranged to by the analogue value in the set that data-switching is become to be selected from a nominal analogue value and the described analogue value is write described storage unit and stores described data, and wherein each stored configuration is specified the nominal analogue value that is used in the described data of described analog memory cell storage.

53. according to the described device of claim 50, wherein said MSP is arranged to described data-switching is become the analogue value, and the described analogue value is write corresponding storage unit, estimation influences the corresponding degree of distortion of the analogue value of write storage unit, and determines accessible memory capacity in response to described degree of distortion.

54. according to each described device among the claim 50-53, wherein said MSP is arranged to from described storage unit and reads the described analogue value, and estimates described degree of distortion based on the described analogue value that reads from described storage unit.

55. according to the described device of claim 54, wherein said MSP is arranged to from reading from the analogue value of described storage unit and comes the described data of reconstruct, and calculates described degree of distortion based on the data of institute's reconstruct.

56. according to the described device of claim 55, wherein said MSP is arranged to by calculating described degree of distortion to reading to sue for peace from the scalar function of the analogue value of described storage unit.

57. according to the described device of claim 56, wherein said MSP is arranged in response to described data reading from the analogue value of described storage unit and being stored in square summation of the difference between the corresponding expectation value of the data in the described storage unit.

58. according to the described device of claim 56, wherein said MSP is arranged to by the quantity of following storage unit is counted the calculated distortion degree, in this storage unit, read from the analogue value of described storage unit and the difference that is stored between the corresponding expectation value of the data in the described storage unit and surpass a predetermined value in response to described data.

59. according to the described device of claim 53, wherein said MSP is arranged to the described analogue value is write described storage unit, and uses the programming and the checking (P﹠amp of iteration; V) process is verified the analogue value that has write, and based on by described P﹠amp; The analogue value of V process verification is calculated described degree of distortion.

60. according to the described device of claim 53, wherein said MSP is arranged to programming and the checking (P﹠amp that the described analogue value is write described storage unit and use iteration; V) analogue value that write of process verification, this process is by the programming step described analogue value of increment iteratively, and the definition of wherein said stored configuration is by the P﹠amp of described iteration; The size of the programming step that the V process is used.

61. according to each described device among the claim 50-53, wherein said MSP is arranged to and uses error correcting code (ECC) to treat the data that will be stored in one group of storage unit to encode, and coded data converts the analogue value to be used for being stored in the corresponding analog memory cell of this group storage unit, storage unit from described group reads the described analogue value, to estimating between the analogue value that is read and the distance metric that approaches most between the effective ECC code word of the described analogue value, and in response to the stored configuration of adaptive this group storage unit of the distance metric of being estimated.

62. according to each described device among the claim 50-53, wherein said MSP is arranged to and reads the data that are stored in the described storage unit, and revises described stored configuration in response to the detection mistake in the data that read.

63. according to the described device of claim 62, wherein said MSP is arranged to and uses error correcting code (ECC) to the data coding, and revises described stored configuration by the code check of revising described ECC.

64. according to each described device among the claim 50-53, wherein said MSP is arranged to the previous programming and the erase operation that are applied to storage unit is followed the trail of, and estimates corresponding accessible capacity in response to previous programming of having followed the trail of and erase operation.

65. according to the described device of claim 64, wherein said MSP is arranged in response to the length of the time period that has passed since previous programming and erase operation and calculates accessible capacity.

66. according to each described device among the claim 50-53, the initial part that wherein said MSP is arranged to described data converts the analogue value to and the described analogue value is write corresponding storage unit, and be written to the analogue value of at least some described storage unit and do not wipe this storage unit by increase subsequently, and the other part of described data is stored in the described storage unit.

67. according to each described device among the claim 50-53, wherein said MSP is arranged to the error correcting code of using to described data increase redundant digit (ECC) data is encoded, and described redundant digit is stored in some analog memory cells, and does not wipe described storage unit and revise described stored configuration by revising a plurality of redundant digits that increase by described ECC.

68. according to the described device of claim 67, wherein said MSP is arranged to and the described redundant digit of described data separating ground storage.

69. according to each described device among the claim 50-53, wherein said MSP is arranged to by the stored configuration of selecting to upgrade from the predefined set of possible stored configuration, revises described stored configuration.

70., wherein specify the non-integral bit number in every unit by the defined described data volume of at least one described stored configuration according to each described device among the claim 50-53.

71. according to each described device among the claim 50-53, wherein said MSP is arranged in and with before the data write storage unit data is compressed, and the definition of wherein said stored configuration will be compressed the corresponding ratio of compression that is adopted to data.

72. according to each described device among the claim 50-53, wherein said MSP is arranged to the respective sets definition stored configuration at described storage unit.

73. according to each described device among the claim 50-53, wherein said MSP is arranged to the data item of accepting to be used for being stored in described storer, select wherein storage unit subclass in response to the stored configuration of being distributed with storing data item, and with described store data items in selected storage unit subclass.

74. according to each described device among the claim 50-53, wherein said MSP is arranged in not the free time that described data are stored and read and reappraises accessible memory capacity during the section.

75. according to each described device among the claim 50-53, wherein said MSP is arranged to described stored configuration is stored in the allocation list.

76. according to each described device among the claim 50-53, wherein said MSP is arranged in the data volume that is stored in the described storage unit and estimates to keep between the accessible capacity predetermined nargin accordingly.

77. according to each described device among the claim 50-53, wherein at least some distortions are caused by the leakage current in the described analog memory cell, and wherein said MSP is arranged to described leakage current is estimated.

78. a data storage device comprises:

Memory signals processor (MSP), it is arranged to the degree of distortion of estimation among corresponding analog memory cell, estimate the corresponding accessible memory capacity of described analog memory cell based on estimated degree of distortion, based on estimated accessible capacity is that described storage unit distributes definition to treat to be stored in the corresponding stored configuration of the data volume in the described storage unit, and according to the stored configuration of corresponding distribution with described data storage in described storage unit.

79. a data storage device comprises:

Memory signals processor (MSP), it is arranged to the corresponding accessible memory capacity of following the trail of described storage unit when described storer is in user mode in host computer system, acceptance is used for being stored in the data of described storer, be used to store the storage unit subclass of described data based on the accessible Capacity Selection one of being followed the trail of, and with described data storage in the storage unit of described subclass.

80. according to the described device of claim 79, wherein said MSP is arranged to the storage unit of the big or small optimum matching of the data of selecting its accessible total volume and being accepted.

81. according to the described device of claim 79, wherein said MSP is arranged to the reliability step of accepting to be used to store the requirement of described data, and selects described storage unit in response to desired reliability step.

82. according to the described device of claim 79, wherein said MSP is arranged to and accepts the desired maintenance phase that is used to store described data, and selects described storage unit in response to the desired maintenance phase.

83. according to the described device of claim 79, wherein said MSP is arranged to selection has low distortion with respect to other storage unit storage unit.

84. according to the described device of claim 79, wherein said MSP is arranged to the previous programming and the erase operation that are applied to described storage unit is followed the trail of, and comes select storage unit in response to previous programming and erase operation.

85. 4 described devices according to Claim 8, wherein said MSP is arranged to by being chosen in has the previous programming of less number of times and the storage unit of erase operation with respect to other storage unit in the described storer, and a plurality of programmings and erase operation are evenly distributed in the described storage unit.

86. being arranged to be chosen in the predetermined nearest time period, 5 described devices according to Claim 8, wherein said MSP have the previous programming of less number of times and the storage unit that erase operation is carried out with respect to other storage unit.

87. according to the described device of claim 79, wherein said MSP is arranged to by the accessible capacity summation to the storage unit that can be used for storing data, calculates the size of available storage space and reports to described host computer system.

88. according to the described device of claim 79, wherein said storer is divided into a plurality of erase blocks, each erase block is included in one group of storage unit of wiping in the single erase operation, and wherein said MSP is arranged to obliterated data item from described storer in the following way:

Identification stores one or more erase blocks of described data item;

Wipe the erase block that stores described data item.

89. according to the described device of claim 79, wherein said MSP is arranged to from described host computer system and accepts data with the fixed capacity piece, and based on the accessible capacity of the described variable capacity group of being followed the trail of, with described data storage in the variable capacity group of described storage unit.

90. 9 described devices according to Claim 8, wherein said MSP is arranged to two or more its capacity of identification less than the variable capacity group of the capacity of fixed capacity piece, and will be received in data storage in one or more fixed capacity pieces in two or more variable capacity groups of being discerned.

91. 9 described devices according to Claim 8, wherein said MSP is arranged to one or more variable capacity set of dispense is exceeded the volume memory storage area for being used as, to be received in data storage in the fixed capacity piece in corresponding variable capacity group, and, when the accessible capacity of a variable capacity group during, in the data that are received in the corresponding fixed capacity piece some are stored in exceeding in the volume memory storage area of being distributed less than the capacity of described fixed capacity piece.

92. 9 described devices according to Claim 8, wherein said MSP is arranged to the data that will be received in the fixed capacity piece and is stored in sequentially in the described storage unit, and and the border between the variable capacity group irrelevant.

93. according to the described device of claim 92, wherein said MSP is arranged to the data storage that initially will be received in each fixed capacity piece in corresponding variable capacity group, and subsequently to the data of initial storage reprogramming in proper order, and and the border between the described variable capacity group irrelevant.

94. 9 described devices according to Claim 8, wherein said MSP are arranged to and take out described data from the variable capacity groups, the described fixed capacity piece of reconstruct, and use described fixed capacity piece to described host computer system output data.

95. according to the described device of claim 79, wherein said MSP is arranged to by in the described data of buffer memory at least some, is applied to the number of times of the memory access operations of described storer with minimizing.

96. according to the described device of claim 95, detect instantaneous storage incident, just the data that are buffered be sent to described storer in case wherein said MSP is arranged to.

97. according to the described device of claim 96, wherein said instantaneous storage incident comprises power fail on the horizon, overtime and acceptance at least one incident in the incident of the end of file (EOF) order of described host computer system of being selected from.

98. a data storage device comprises:

Storer, it comprises a plurality of analog memory cells; With

99. according to the described device of claim 98, wherein said memory bit is in first integrated circuit (IC), and wherein said MSP is arranged in the 2nd IC that is different from a described IC.

100. according to the described device of claim 98, wherein said storer and described MSP are integrated in the individual equipment.

101. according to the described device of claim 98, wherein said MSP is embodied in the processor of described host computer system.

102. according to the described device of claim 98, wherein said storage unit comprises flash cell.

103. according to the described device of claim 98, wherein said storage unit comprises dynamic random access memory (DRAM) unit.

104. according to the described device of claim 98, wherein said storage unit comprises phase change memory (PCM) unit.

105. according to the described device of claim 98, wherein said storage unit comprises the read-only storage of nitride (NROM) unit.

106. according to the described device of claim 98, wherein said storage unit comprises MRAM storage (MRAM) unit.

107. according to the described device of claim 98, wherein said storage unit comprises ferro-electric random access storage (FRAM) unit.

108. a data storage device comprises:

Storer, it comprises a plurality of analog memory cells; And

Memory signals processor (MSP), it is connected to described storer, and be arranged to when described storer is in use in host computer system, follow the trail of the corresponding accessible memory capacity of described storage unit, acceptance is used for being stored in the data of storer, select to be used to store the storage unit subclass of described data based on the accessible capacity of being followed the trail of, and with described data storage in the storage unit of described subclass.

109. according to the described device of claim 108, wherein said memory bit is in first integrated circuit (IC), and wherein said MSP is arranged in the 2nd IC that is different from a described IC.

110. according to the described device of claim 108, wherein said storer and described MSP are integrated in the individual equipment.

111. according to the described device of claim 108, wherein said MSP is embodied in the processor of described host computer system.

112. according to the described device of claim 108, wherein said storage unit comprises flash cell.

113. according to the described device of claim 108, wherein said storage unit comprises dynamic random access memory (DRAM) unit.

114. according to the described device of claim 108, wherein said storage unit comprises phase change memory (PCM) unit.

115. according to the described device of claim 108, wherein said storage unit comprises the read-only storage of nitride (NROM) unit.

116. according to the described device of claim 108, wherein said storage unit comprises MRAM storage (MRAM) unit.

117. according to the described device of claim 108, wherein said storage unit comprises ferro-electric random access storage (FRAM) unit.