CN101567322B - Encapsulating structure and encapsulating method of chip - Google Patents

Encapsulating structure and encapsulating method of chip Download PDF

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Publication number
CN101567322B
CN101567322B CN2008100931915A CN200810093191A CN101567322B CN 101567322 B CN101567322 B CN 101567322B CN 2008100931915 A CN2008100931915 A CN 2008100931915A CN 200810093191 A CN200810093191 A CN 200810093191A CN 101567322 B CN101567322 B CN 101567322B
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chip
patterning
metal wire
wire sections
chips
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CN101567322A (en
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沈更新
陈煜仁
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The invention relates to an encapsulating structure of a chip, which comprises a chip holding shelf, the chip, an encapsulating body, a plurality of patterning metal line sections, a plurality of patterning protective layers, a plurality of patterning UBM layers and a plurality of conducting elements, wherein the chip holding shelf is provided with a chip holding area, the front face of the chip holding area is provided with an adhesion layer; the active face of the chip is provided with a plurality of weld pads, and the back face of the chip is formed on the adhesion layer of the chip holdingshelf; the encapsulating body is covered around the chip holding shelf provided with the chip and exposes the weld pads on the active face of the chip, and the height of the encapsulating body is lar ger than that of the chip; one end of the patterning metal line section is electrically connected with the weld pads, and the other end extends outside and is covered on one surface of the encapsulating body; the patterning protective layers are covered on the patterning metal line sections and expose the part of a surface of a fan-out structure formed in such a way that the patterning metal line sections extend outside the active face of the chip; the patterning UBM layers are respectively formed on the part of the surface of each fan-out structure and electrically connected with the patterning metal line sections; and the conducting elements are electrically connected with the patterning metal line sections by the UBM layers.

Description

The encapsulating structure of chip and method for packing thereof
Technical field
The method for packing that the relevant a kind of chip of the present invention reconfigures is particularly about utilizing the chip containing rack to carry out the method for packing that chip reconfigures.
Background technology
Semi-conductive technology has developed suitable rapidly, therefore microminiaturized semiconductor grain (Dice) is the demand that chip (chip) must have diversified function, make semiconductor chip must in very little zone, dispose more I/o pad (I/O pads), thereby make the density of metal pin (pins) also improve fast.Therefore, early stage leaded package technology has been not suitable for the high-density metal pin; So develop the encapsulation technology that a kind of ball array (Ball Grid Array:BGA), the ball array encapsulation is except having than the more highdensity advantage of leaded package, and its tin ball also relatively is not easy infringement and distortion.
Popular along with 3C Product, for example: mobile phone (Cell Phone), PDA(Personal Digital Assistant) or iPod etc., all the System on Chip/SoC of many complexity must be put into a very little space, therefore be this problem of solution, a kind of being called " wafer-class encapsulation (wafer level package; WLP) " encapsulation technology develops out, and it can become before many crystal grain is chip at cut crystal, just earlier wafer is encapsulated.United States Patent (USP) announces the 5th, 323, and No. 051 patent has promptly disclosed this " wafer-class encapsulation " technology.Yet, this " wafer-class encapsulation " technology is along with the increase of the weld pad on the chip active surface (pads) number, make that the spacing of weld pad (pads) is too small, except meeting causes the problem of signal coupling or signal interference, also can cause the problems such as reliability reduction of encapsulation because the weld pad spacing is too small.Therefore, after chip further dwindles again, make aforesaid encapsulation technology all can't satisfy.
For solving this problem, United States Patent (USP) announces the 7th, 196, disclosed a kind of wafer that will finish semiconductor technology for No. 408, after test and cutting, with test result is that good crystal grain (good die) or chip reapposes on another substrate, and then carry out packaging process, so, make these chip chambers that reapposed have the spacing of broad, so (fanout) technology that stretches out is for example used in distribution that can the weld pad on the chip is suitable, therefore can effectively solve because of spacing too small, the problem that causes signal coupling or signal to disturb except meeting.
Yet, for making semiconductor chip that less and thin encapsulating structure can be arranged, before carrying out the wafer cutting, can carry out thinning to wafer earlier and handle, for example wafer is thinned to 2～20mil, and then to cut into many crystal grain be chip in back of the body mill (backside lapping) mode.This chip through the thinning processing through reconfiguring on another substrate, forms a packaging body with injection molded with a plurality of chips again; Because chip is very thin, make that packaging body also is very thin, so after packaging body disengaging substrate, the stress of packaging body itself can make packaging body generation warpage increases follow-up difficulty of carrying out cutting action.
In addition, after the wafer cutting, reconfigure when another support plate, be of a size of greatly because the size of new support plate is more original, therefore plant in the ball operation follow-up, can can't aim at, its encapsulating structure reliability reduces.
In addition, in the process of whole encapsulation, also can produce when planting ball, manufacturing equipment can produce local excessive pressure to chip, and may damage the problem of chip; Simultaneously, also may because the material of planting ball causes and chip on weld pad between resistance value become big, and influence the problems such as performance of chip.
Summary of the invention
Because plant that ball is aimed at and the problem of packaging body warpage described in the background of invention, the invention provides encapsulating structure and method thereof that a kind of chip that utilizes the wafer aligned sign reconfigures, the method that a plurality of chips are configured again and encapsulate.
Another main purpose of the present invention is providing a kind of method for packing that reconfigures at chip, is that chip with different size size and function reconfigures the method for packing on a support plate.
In addition, the present invention also has a main purpose at the method for packing that provides a kind of chip to reconfigure, it can be reconfigured in the chip that wafer cut out on the chip containing rack at 12 o'clock, so can effectively use the sealed in unit that promptly has of 8 o'clock wafers, and need not to re-establish the sealed in unit of 12 o'clock wafers, can reduce the packaging cost of 12 o'clock wafers.
A main purpose more of the present invention makes that at the method for packing that provides a kind of chip to reconfigure the chip that encapsulates all is " known is normally functioning chip " (Known good die), can save encapsulating material, so also can reduce the cost of technology.
Another purpose of the present invention is to put chip again by the chip disposal area of chip containing rack, the accuracy in the time of can being improved chip by the relative position of chip disposal area and reconfigure.
According to the above, the present invention discloses a kind of method for packing of chip-packaging structure, comprising: a wafer is provided, has a upper surface and a back side, and dispose a plurality of chips on the wafer, and have a plurality of weld pads on each chips; Form the upper surface of one first protective layer, and cover a plurality of weld pads on each chips at wafer; Cut crystal is to obtain a plurality of chips; One chip containing rack is provided, and the front of chip containing rack disposes an adhesion coating; Picking and placeing each chips to the chip containing rack, is that the back side with each chips is attached on the chip containing rack front by adhesion coating down; Form a polymer material layer at the chip containing rack and have on a plurality of chips of first protective layer; Cover a die device,, make polymer material layer be filled in and have between a plurality of chips of first protective layer, and envelope each chips and chip containing rack in order to the planarization polymer material layer; Break away from die device, in order to the surface that exposes first protective layer on each chips to form a packaging body; Remove first protective layer to expose a plurality of weld pads on each chips, make the height of polymer material layer greater than the height of each chips; Form second patterned protection layer,, and expose a plurality of weld pads of a plurality of chips with the active surface that covers each chips and polymer material layer partly; Form the metal wire sections of the patterning of many fan-outs, and an end of the metal wire sections of the patterning of many fan-outs electrically connects with a plurality of weld pads that expose; Form the 3rd protective layer of patterning,, and expose the part surface of a fan-out structure of extending laterally of the metal wire sections of each bar patterning with the active surface that covers each chips and the metal wire sections of each bar patterning; The UBM layer that forms a plurality of patternings and electrically connects with patterning metal line sections on the part surface of the fan-out structure of extending laterally of the metal wire sections of each bar pattern; Forming a plurality of conducting elements, is that UBM layer and the patterning metal line sections of a plurality of conducting elements by a plurality of patternings electrically connected; And the cutting packaging body, to form a plurality of chips of independently finishing encapsulation separately.
According to above method for packing, the present invention also discloses a kind of encapsulating structure of chip, comprising: a chip containing rack has on the front of a chip disposal area and its chip disposal area and disposes an adhesion coating; One chip disposes a plurality of weld pads and a back side and is formed on the adhesion coating of chip containing rack on the one active surface; One packaging body, its ring be overlying on have chip the chip containing rack with a plurality of weld pads on the active surface that exposes chip, and the height of packaging body is greater than the height of chip; One end of patterning metal line sections and a plurality of weld pad electrically connect, and the other end extends with the outside and is covered on the surface of packaging body; A plurality of patterned protective layer, it is covered in patterning metal line sections and exposes the part surface of a fan-out structure of extending to the active surface of the chip outside of the metal wire sections of a plurality of patternings; Form a plurality of UBM layers on the part surface of the fan-out structure of extending laterally of the metal wire sections of each bar patterning, and electrically connect with patterning metal line sections; And a plurality of conducting elements, by the metal wire sections electric connection of UBM layer and a plurality of patternings.
Description of drawings
For making purpose of the present invention, structure, feature and function thereof there are further understanding, below conjunction with figs. are elaborated to preferred embodiment of the present invention, wherein:
Fig. 1 is disclosed technology according to the present invention, represents to dispose on the wafer schematic diagram of a plurality of chips;
Fig. 2 is disclosed technology according to the present invention, is illustrated in the schematic diagram that forms one first protective layer on the upper surface of wafer;
Fig. 3 A and Fig. 3 B are disclosed technology according to the present invention, the schematic diagram of expression chip containing rack;
Fig. 4 A and Fig. 4 B are disclosed technology according to the present invention, and expression wafer cutting obtains a plurality of chips and reassigns to schematic diagram on the chip containing rack;
Fig. 5 is the schematic cross-section of the chip containing rack with a plurality of chips of presentation graphs 4A or Fig. 4 B;
Fig. 6 is disclosed technology according to the present invention, is illustrated in the schematic diagram that forms polymer material layer on the chip;
Fig. 7 is disclosed technology according to the present invention, and expression is with the schematic diagram of polymer material layer planarization;
Fig. 8 is disclosed technology according to the present invention, and expression removes schematic diagram with the active surface that exposes each chips with first protective layer;
Fig. 9 is disclosed technology according to the present invention, and expression forms one second protective layer with the active surface that covers each chips and the schematic diagram of polymer material layer partly;
Figure 10 is disclosed technology according to the present invention, is illustrated in to form a plurality of openings on second protective layer to expose the schematic diagram at the weld pad of each chips to the open air;
Figure 11 is disclosed technology according to the present invention, and expression forms metal level with the schematic diagram on the weld pad that covers each chips;
Figure 12 is disclosed technology according to the present invention, the schematic diagram of the metal wire sections of the patterning of many fan-outs of expression formation;
Figure 13 is disclosed technology according to the present invention, and expression forms the schematic diagram of one the 3rd protective layer with the metal wire sections of the patterning that covers many fan-outs;
Figure 14 is disclosed technology according to the present invention, and expression forms the schematic diagram of a plurality of openings with the outward extending surface of the patterning metal line sections that exposes to the open air;
Figure 15 is disclosed technology according to the present invention, is illustrated in the schematic diagram that forms the UBM layer on the surface of the patterning metal line sections that exposes to the open air;
Figure 16 is disclosed technology according to the present invention, and expression forms a plurality of conducting elements schematic diagram with the encapsulating structure that forms multi-chip moduleization on the UBM of a plurality of patternings layer; And
Figure 17 is disclosed technology according to the present invention, the schematic diagram of the encapsulating structure of expression one chip.
Embodiment
The present invention is the method for packing that a kind of chip reconfigures in this direction of inquiring into, a plurality of chips is reconfigured on another substrate the method that encapsulates then.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, execution of the present invention does not limit the specific details that those skilled in the art were familiar with of being of mode that chip stacks.On the other hand, the detailed step of back segment operations such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet,, can be described in detail as follows for preferred embodiment of the present invention, yet except these are described in detail, the present invention can also be implemented among other the embodiment widely, and scope of the present invention do not limited, its with after the claim that claim was limited be as the criterion.
In the semiconductor packaging process in modern times, all be that a wafer (wafer) of having finished leading portion operation (Front End Process) is carried out thinning processing (Thinning Process) earlier, for example the thickness with chip is ground between 2～20mil; Then, the cutting (sawing process) of carrying out wafer is a chip 110 to form many crystal grain; Then, use fetching device (pick and place) that many chips are positioned on another substrate one by one.Clearly, the street zone on the substrate is bigger than chip, therefore, and can be so that these chip chambers that reapposed have the spacing of broad, so distribution that can the weld pad on the chip is suitable.
At first, as shown in Figure 1, be that expression one wafer 10 disposes the vertical view of a plurality of chips 110, and have a plurality of weld pads (not expression in the drawings) on each chips 110.Then, Fig. 2 is illustrated in a schematic cross-section that has protective layer on the wafer.As shown in Figure 2, be in the upper surface of the wafer 10 that disposes a plurality of chips 110, and on the active surface of each chips 110, form first protective layer 20 that photoresist (photoresist) layer for example is to cover the active surface of each chips 110.Next, Fig. 3 A and Fig. 3 B are the schematic diagrames of representing respectively in order to the chip containing rack that reconfigures chip.This chip containing rack 30 is a cancellated framework and chip disposal area 301 with a plurality of identical sizes, utilize a plurality of coil holders 314 to be connected to each other between each adjacent chip disposal area 301, its ways of connecting can be that four angles of chip disposal area 301 are connected with a plurality of coil holders 314 with four angles of contiguous other chip disposal areas 301, make adjacent chip disposal area 301 to be connected to each other, and between adjacent chip disposal area 301, a space is arranged, as Fig. 3 A or the represented rectangular apertures 312 of Fig. 3 B, its rectangular apertures 312 can be a rhombus, square etc., but do not have any restriction in an embodiment of the present invention.
Then, Fig. 4 A and Fig. 4 B represent the schematic diagram that has the chip configuration of first protective layer at the ccontaining block of chip with a plurality of respectively.Shown in Fig. 4 A and Fig. 4 B, be that first protective layer 20 is covered on the active surface of wafer 10; Then, the wafer 10 that will have first protective layer 20 cuts into many chips 110 with first protective layer, then each is had first protective layer 20 chip 110 active surface up; Then, use fetching device (in figure, not showing) each chips 110 to be picked up and is positioned on the chip disposal area 301 of chip containing rack 30 by active surface; Because, all dispose a plurality of weld pads 112 on the active surface of each chips 30, therefore, fetching device can Direct Recognition goes out weld pad 112 positions on each chips 110 its active surface; When fetching device will be positioned over chip 110 on the chip disposal area 301 of chip containing rack 30, can be again relative position by reference point on the chip disposal area 301 (in figure, not showing) and chip containing rack 30, each chips 110 accurately is positioned in a plurality of chips disposal area 301 on the chip containing rack 30.Therefore, when a plurality of chips 110 reconfigure on chip containing rack 30, just chip 110 can be positioned on the chip containing rack 30 exactly; In addition, put a plurality of chips 110 again, the accuracy in the time of chip can be improved by the relative position of chip disposal area 301 reconfiguring by chip disposal area 301.Then, as shown in Figure 5, be AA line segment according to Fig. 4 A and Fig. 4 B, a plurality of chips 110 that expression has first protective layer 20 are seated on the chip containing rack 30 down with the back side.
In addition, in the present embodiment, on chip containing rack 30, also comprise an adhesion coating (not expression in the drawings), its objective is when chip 110 is put on a plurality of chips disposal area 301 to chip containing rack 30, the back side of chip 110 is fixed on the chip disposal area 301, and the material of this adhesion coating is the rubber-like sticky material, and it can be selected in following group: silicon rubber (silicone rubber), silicones (silicone resin), elasticity PU, porous PU, acrylic rubber (acrylic rubber) and chip cutting glue.
Next, please refer to Fig. 6, it is coating one polymer material layer 40 on the active surface of chip containing rack 30 and partial chip 110, and use a die device 500 that polymer material layer 40 is flattened, so that polymer material layer 40 forms the surface of a planarization, make polymer material layer 40 coat each chips 110 and be filled between each chips 110 to form a packaging body.In the present embodiment, polymer material layer 40 can be silica gel, epoxy resin, acrylic acid (acrylic), reach benzocyclobutene materials such as (BCB).
Then, can be optionally the polymer material layer 40 of planarization be carried out a baking program, polymer material layer 40 is solidified.Follow again, carry out demoulding program, with die device 500 with solidify after polymer material layer 40 separate, to expose the surface of smooth polymer material layer 40, as shown in Figure 7.Then, can optionally use cutter (not expression in the drawings), form many Cutting Roads or cut 600 on the surface of polymer material layer 40, wherein the degree of depth of each bar Cutting Road 600 is 0.5～1 Mill (mil), and the width of Cutting Road 600 then is 5 to 25 microns.In a preferred embodiment, Cutting Road 600 can be mutual vertical interlaced, and the reference line when can be used as actual diced chip.
Then, please refer to Fig. 8, is to utilize semiconductor technology, for example, develops and etching, is to form a patterning photoresist layer (not expression in the drawings) on polymer material layer 40; Then, be etched with first protective layer 20 that removes on the active surface of each chips 110, make ring be overlying on the height of polymer material layer 40 of each chips 110 simultaneously greater than the height of each chips 110 to expose the active surface of each chips 110.
Then, please refer to Fig. 9, is to form a second patterned protection layer 50 with the active surface that covers each chips 110 and the surface of polymer material layer 40 partly, and exposes a plurality of weld pads 112 on the active surface of each chips 110; Its step comprises: be to utilize semiconductor technology, the photoresist layer (not expression in the drawings) that forms a patterning earlier is on second protective layer 50; Be etched with and remove partly second protective layer 50 forming a plurality of openings (opening), and expose a plurality of weld pads 112 on the active surface of each chips 110, as shown in figure 10.
And then, Figure 11 to Figure 12 is the schematic cross-section that is illustrated in the metal wire sections 60 of the patterning that forms many fan-outs on the packaging body.After the position of a plurality of weld pads 112 of determining each chips 110, can use the traditional technology that reroutes (Redistribution Layer; RDL) on a plurality of weld pads 112 that each chips 110 is exposed to the open air, form the metal wire sections 60 of the patterning of many fan-outs, wherein an end of the metal wire sections 60 of each bar patterning and weld pad 112 electrically connect, and partly the other end of patterning metal line sections 60 is to be formed on the polymer material layer 40 in the fan-out mode.At this, the formation step of metal wire sections 60 comprises: form earlier a metal level 60 on second protective layer 50 and fill up the weld pad 112 that is exposed to the open air; The photoresist layer (expression) in the drawings that forms a patterning is on metal level 60; Be etched with and remove partly metal level 60, with the metal wire sections 60 of the patterning that forms many fan-outs, as shown in figure 12; Wherein an end of the metal wire sections 60 of part patterning electrically connects a plurality of weld pads 112 of the active surface of a plurality of chips 110, and partly the other end of the metal wire sections 60 of a plurality of patternings is to be formed on the polymer material layer 40 in the fan-out mode.
Then, with reference to Figure 13, be to utilize semiconductor technology, on the metal wire sections 60 of the patterning of many fan-outs, form the 3rd protective layer 70 of a patterning, with the metal wire sections 60 of the patterning of the active surface that covers each chips 110 and each bar fan-out; Then, on the other end of each strip metal line segment 60, form the surface of a plurality of openings (opening), as shown in figure 14 with the other end of the metal wire sections 60 of the patterning that exposes each bar fan-out; Wherein, the step that forms the 3rd protective layer of patterning comprises: utilize semiconductor technology, form one the 3rd protective layer earlier, photoresist layer for example is to cover patterning metal line sections 60; Then, utilize little shadow and etching, the photoresist layer (not expression in the drawings) that forms a patterning is on the 3rd protective layer; Be etched with and remove partly the 3rd protective layer, forming the 3rd protective layer 70 of a patterning, and expose the surface of the other end of metal wire sections 60 of the patterning of each bar fan-out.
Then, with reference to Figure 15, be to be illustrated in the schematic diagram that forms many UBM metal levels on the surface of the other end of metal wire sections of patterning of each the bar fan-out that exposes.As shown in figure 15, be on the surface of the other end of the metal wire sections 60 of the patterning of each the bar fan-out that exposes, form a UBM layer in the mode of sputter (sputtering); Then, utilize semiconductor technology, for example develop and etching, it is the photoresist layer (not expression in the drawings) that on the UBM layer, forms a patterning, then, utilization is etched with and removes partly UBM layer,, and electrically connects with patterning metal line sections 60 on the surface of the metal wire sections 60 of the patterning of each the bar fan-out that exposes with the UBM layer 80 that forms the multiple bar chart caseization; The material of UBM layer in the present embodiment can be Ti/Ni.Then, utilize semiconductor technology again, for example little shadow (photolithography) and etching remove UBM layer 80 partly on the UBM layer 80 that only keeps with 60 electric connections of many strip metals line segment.
At last, on each UBM layer 80, form a plurality of conducting elements 90 again, so that as the chip 110 external contacts that electrically connect, wherein, this conducting element 90 can be metal coupling (metal bump) or tin ball (solder ball) and UBM layer 80 that can be by a plurality of patternings and the metal wire sections 60 of patterning electrically connects.Then, can carry out last cutting to packaging body.In the present embodiment, can then form the encapsulating structure of a multi-chip moduleization, as shown in figure 16 with a plurality of chips as the cutting unit; In addition, also can be with single chips as the cutting unit, to form many chips of finishing packaging process, as shown in figure 17.
Be stressed that at this metal wire sections 60 of above-mentioned formed fan-out structure is not only to be defined in traditional technology that reroutes, as long as it can form the method for fan-out structure by semiconductor technology, is embodiments of the present invention; Simultaneously, the method for using semiconductor technology to form the fan-out structure has been prior art, thus the present invention be not described in detail, to avoid producing unnecessary restriction.
And the mode that forms in the above-described embodiments, the polymer material layer 40 of planarization can select to use injection molded (molding process) to form.At this moment, a die device 500 is covered earlier to chip containing rack 30, at this moment, can make and keep a space between die device 500 and the chip 110, and then carry out the injection molding operation, and with polymer material layer 40, epoxy resin mould closure material (Epoxy Molding Compound for example; EMC) inject the space of die device 500 and chip 110, make polymer material layer 40 form the surface of a planarization, so that polymer material layer 40 coats each chips 110 and is filled between the chip 110 and envelopes chip containing rack 30.Because, use injection molded manufacture process afterwards identical, so no longer given unnecessary details with aforementioned manner.
Though the present invention discloses as above with aforesaid preferred embodiment; yet it is not in order to limit the present invention; any person skilled in the art person; without departing from the spirit and scope of the present invention; when can making all changes that is equal to or replacement, therefore scope of patent protection of the present invention must be looked being as the criterion that the appended the application's claim scope of this specification defined.

Claims (4)

1. the method for packing of a chip-packaging structure comprises:
One wafer is provided, has a upper surface and a back side, dispose a plurality of chips on this wafer, and have a plurality of weld pads on each this chip;
Form one first protective layer this upper surface, and cover these weld pads on each this chip at this wafer;
Cut this wafer, to obtain these chips;
One chip containing rack is provided, has a plurality of chips disposal area, between each this chip disposal area be with a plurality of coil holders be connected to each other and adjacent each this chip disposal area between have a space, and dispose an adhesion coating on the front of each this chip disposal area;
Picking and placeing each this chip to these chip disposal areas of this chip containing rack, is that this back side of each chip is attached on this front of these chip disposal areas of this chip containing rack by this adhesion coating down;
Form a polymer material layer on this chip containing rack and have on these chips of this first protective layer;
Cover a die device,, make this polymer material layer be filled in and have between these chips of this first protective layer, and envelope each this chip and this chip containing rack in order to this polymer material layer of planarization;
Break away from this die device, in order to the surface that exposes this first protective layer on each this chip to form a packaging body;
Remove this first protective layer to expose these weld pads on each this chip, make the height of this polymer material layer greater than the height of each this chip;
Form a second patterned protection layer at the active surface of each this chip that exposes to the open air and partly on this polymer material layer, and be etched with and remove partly this second patterned protection layer to form a plurality of openings and to expose these weld pads; Form the metal wire sections of the patterning of a plurality of fan-outs, the metal wire sections of the patterning of an end of the metal wire sections of the patterning of these fan-outs and the electric connection of these weld pads and these fan-outs of part is formed on this polymer material layer of part;
Form the 3rd protective layer of a patterning,, and expose the surface of the other end of metal wire sections of the patterning of each this fan-out with the metal wire sections of the patterning of this active surface of covering each this chip and each this fan-out;
The UBM layer that forms a plurality of patternings and electrically connects with the metal wire sections of these patternings on this surface of the fan-out structure of extending laterally of the metal wire sections of each this pattern;
Forming a plurality of conducting elements, is that these conducting elements are electrically connected by the UBM layer of these patternings and the metal wire sections of these patternings; And
Cut this packaging body, to form a plurality of chips of independently finishing encapsulation separately.
2. method for packing according to claim 1, the metal wire sections that it is characterized in that forming the patterning of these fan-outs comprises:
Form a metal level with on these weld pads of this active surface of covering this each this chip and on this polymer material layer;
The photoresist layer that forms a patterning is on this metal level; And
Remove partly this metal level, with this metal level on this active surface that removes these chips of part, to form the metal wire sections of these patternings, wherein partly an end of the metal wire sections of these patternings electrically connects these weld pads on this active surfaces of a plurality of chips, and partly the other end of the metal wire sections of these patternings is to be formed on this polymer material layer in the fan-out mode.
3. modular multicore sheet method for packing comprises:
One wafer is provided, has a upper surface and a back side, and dispose a plurality of chips on this wafer, and have a plurality of weld pads on each this chip;
Form one first protective layer at this upper surface of this wafer and cover these weld pads on each this chip;
Cut this wafer, to obtain these chips;
One chip containing rack is provided, has a plurality of chips disposal area, between each this chip disposal area be with a plurality of coil holders be connected to each other and adjacent each this chip disposal area between have a space, and dispose an adhesion coating on the front of each this chip disposal area;
Pick and place each this chip to these chip disposal areas of this chip containing rack, be with this back side of each chip down by this adhesion coating be attached to these chip disposal areas of this chip containing rack should the front on;
Form a polymer material layer on this chip containing rack and have on these chips of this first protective layer;
Cover a die device,, make this polymer material layer be filled in and have between these chips of this first protective layer, and coat each this chip and this chip containing rack in order to this polymer material layer of planarization;
Break away from this die device, in order to the surface that exposes this first protective layer on each this chip to form a packaging body;
Remove this first protective layer to expose these weld pads on each this chip, make the height of this polymer material layer greater than the height of each this chip;
Form a second patterned protection layer at the active surface of each this chip that exposes to the open air and partly on this polymer material layer, and be etched with and remove partly this second patterned protection layer to form a plurality of openings and to expose these weld pads;
Form the metal wire sections of the patterning of a plurality of fan-outs, the metal wire sections of the patterning of an end of the metal wire sections of the patterning of these fan-outs and the electric connection of these weld pads and these fan-outs of part is formed on this polymer material layer of part;
Form the 3rd protective layer of a patterning,, and expose the surface of the other end of metal wire sections of the patterning of each this fan-out with the metal wire sections of the patterning of this active surface of covering each this chip and each this fan-out;
The UBM layer that forms a plurality of patternings and electrically connects with the metal wire sections of these patternings on this surface of the fan-out structure of extending laterally of the metal wire sections of each this pattern;
Forming a plurality of conducting elements, is that these conducting elements are electrically connected by the UBM layer of these patternings and the metal wire sections of these patternings; And
Cut this packaging body, to form a plurality of modular multichip packaging structures.
4. method for packing according to claim 3 is characterized in that the metal wire sections that forms these fan-outs comprises:
Form a metal level with on these weld pads of this active surface of covering this each this chip and on this polymer material layer;
The photoresist layer that forms a patterning is on this metal level; And
Remove partly this metal level, with this metal level on this active surface that removes these chips of part, to form the metal wire sections of these patternings, wherein partly an end of the metal wire sections of these patternings electrically connects these weld pads on this active surfaces of a plurality of chips, and partly the other end of the metal wire sections of these patternings is to be formed on this polymer material layer in the fan-out mode.
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CN105575825A (en) * 2015-12-24 2016-05-11 合肥祖安投资合伙企业(有限合伙) Chip packaging method and packaging assembly
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