CN101567370B - Coupling capacitance forming circuit, integrated circuit using same and correlative method thereof - Google Patents
Coupling capacitance forming circuit, integrated circuit using same and correlative method thereof Download PDFInfo
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- CN101567370B CN101567370B CN2008100939353A CN200810093935A CN101567370B CN 101567370 B CN101567370 B CN 101567370B CN 2008100939353 A CN2008100939353 A CN 2008100939353A CN 200810093935 A CN200810093935 A CN 200810093935A CN 101567370 B CN101567370 B CN 101567370B
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Abstract
The invention relates to a coupling capacitance forming circuit, an integrated circuit using the same and a correlative method thereof. The integrated circuit comprises a core circuit and a plurality of input/output circuits coupled with the core circuit, wherein part of the lines of at least one specific input/output circuit in the input/output circuits is interrupted so as to form the coupling capacitance of the integrated circuit.
Description
Technical field
The present invention relates to coupling capacitance and form circuit, use this coupling capacitance to form integrated circuit of circuit and associated method, particularly circuit forms circuit to form coupling capacitance, uses this coupling capacitance to form integrated circuit of circuit and associated method relevant for interrupting partly.
Background technology
Generally speaking, (integrated circuit IC) can have a core circuit (core circuit) to integrated circuit, is connected with connection gasket (pad) and core circuit can pass through an imput output circuit (I/O circuit).Connection gasket can be connected (bonding) to be connected to other circuit.
Yet in the integrated circuit, not necessarily all connection gaskets are connected, and therefore the imput output circuit of connected connection gasket just is not used, and therefore can cause the waste of circuit resource.
Summary of the invention
Therefore, one of the object of the invention provides a kind of integrated circuit, and it utilizes the imput output circuit that is not used to form coupling capacitance, to reduce the signal noise in the integrated circuit.
Embodiments of the invention have disclosed a kind of integrated circuit, and look contains: a core circuit; And a plurality of imput output circuits, be coupled to this core circuit; The circuit of the some of at least one imput output circuit that is not used is interrupted to form the coupling capacitance of this integrated circuit in the wherein said imput output circuit.
Another embodiment of the present invention has disclosed a kind of coupling capacitance and has formed circuit, comprises at least one circuit module, and said circuit module comprises: one first P-type mos transistor, its drain electrode are coupled to one second predetermined voltage; One the one N type metal oxide semiconductor transistor, its drain electrode is coupled to this second predetermined voltage; One second P-type mos transistor; Its source electrode couples one first predetermined voltage and its drain electrode couples this first predetermined voltage and a connection gasket, and its grid is coupled to this second predetermined voltage, this first P-type mos transistor drain and a N type metal oxide semiconductor transistor drain; One the 3rd P-type mos transistor, its drain electrode are coupled to this first predetermined voltage; One the 2nd N type metal oxide semiconductor transistor, its drain electrode is coupled to this first predetermined voltage; And one the 3rd N type metal oxide semiconductor transistor, its drain electrode couples this second predetermined voltage and this connection gasket; And the circuit of at least one circuit module that is not used is interrupted in the said circuit module; Make in this circuit module that is not used: transistorized this grid of this second P-type mos does not couple this first a P-type mos transistor and a N type metal oxide semiconductor transistor; Also make transistorized this drain electrode of this second P-type mos not couple this connection gasket; Also make the transistorized grid of the 3rd N type metal oxide semiconductor not couple the 3rd P-type mos transistor and the 2nd N type metal oxide semiconductor transistor, form coupling capacitance by this.
Another embodiment of the present invention has disclosed a kind of coupling capacitance and has formed circuit; Comprise at least one circuit module; Said circuit module comprises: a metal oxide semiconductor transistor; Its drain electrode is coupled to one first predetermined voltage and one second predetermined voltage and its grid, and this grid of this metal oxide semiconductor transistor also is coupled to this first predetermined voltage and this second predetermined voltage, and the source electrode of this metal oxide semiconductor transistor couples this second predetermined voltage and this grid; And the circuit of at least one circuit module that is not used is interrupted in the said circuit module; Make in this circuit module that is not used: this drain electrode of this metal oxide semiconductor transistor is not coupled to this grid of this first predetermined voltage and this metal oxide semiconductor transistor, and makes this grid of this metal oxide semiconductor transistor not be coupled to this second predetermined voltage.
Another embodiment of the present invention has disclosed a kind of method that in an integrated circuit, forms coupling capacitance, a plurality of imput output circuits that this integrated circuit comprises a core circuit and is coupled to this core circuit, and this method comprises; (a) select at least one imput output circuit that is not used from said imput output circuit; And the circuit of some that (b) interrupts this imput output circuit that is not used is to form the coupling capacitance of this integrated circuit.
According to a first aspect of the invention, disclosed a kind of integrated circuit, comprised: a core circuit; A plurality of imput output circuits are coupled to this core circuit; And a plurality of connection gaskets, be coupled to said imput output circuit respectively.A part of connection in the wherein said connection gasket and another is not partly connected, and at least one imput output circuit that is not used is coupled to not connected connection gasket.Each imput output circuit comprises in the wherein said imput output circuit: one first P-type mos transistor, its drain electrode are coupled to one second predetermined voltage; One the one N type metal oxide semiconductor transistor, its drain electrode is coupled to this second predetermined voltage; One second P-type mos transistor; Its source electrode couples one first predetermined voltage and its drain electrode couples this first predetermined voltage and this connection gasket, and its grid is coupled to this second predetermined voltage, this first P-type mos transistor drain and a N type metal oxide semiconductor transistor drain; One the 3rd P-type mos transistor, its drain electrode are coupled to this first predetermined voltage; One the 2nd N type metal oxide semiconductor transistor, its drain electrode is coupled to this first predetermined voltage; And one the 3rd N type metal oxide semiconductor transistor, its drain electrode couples this second predetermined voltage and this connection gasket.Wherein, At least one imput output circuit uses as normal imput output circuit; Wherein interrupt the part circuit; Make: this first P-type mos transistor drain, a N type metal oxide semiconductor transistor drain and the transistorized grid of this second P-type mos all do not couple this second predetermined voltage; The 3rd P-type mos transistor drain, the 2nd N type metal oxide semiconductor transistor drain and the transistorized grid of the 3rd N type metal oxide semiconductor all do not couple this first predetermined voltage; This second P-type mos transistor drain does not couple this first predetermined voltage, and the 3rd N type metal oxide semiconductor transistor drain does not couple this second predetermined voltage.And the circuit of the imput output circuit that this is not used is interrupted; Make in this imput output circuit that is not used: transistorized this grid of this second P-type mos does not couple this first a P-type mos transistor and a N type metal oxide semiconductor transistor; Also make transistorized this drain electrode of this second P-type mos not couple this connection gasket; Also make transistorized this grid of the 3rd N type metal oxide semiconductor not couple the 3rd P-type mos transistor and the 2nd N type metal oxide semiconductor transistor, form coupling capacitance by this.
According to a second aspect of the invention, disclosed a kind of integrated circuit, comprised: a core circuit; A plurality of imput output circuits are coupled to this core circuit; And a plurality of connection gaskets, be coupled to said imput output circuit respectively.A part of connection in the wherein said connection gasket and another is not partly connected, and at least one imput output circuit that is not used is coupled to not connected connection gasket.Each imput output circuit comprises in the wherein said imput output circuit: a metal oxide semiconductor transistor; Its drain electrode is coupled to one first predetermined voltage and one second predetermined voltage and its grid; And this grid of this metal oxide semiconductor transistor also is coupled to this first predetermined voltage and this second predetermined voltage, and the source electrode of this metal oxide semiconductor transistor couples this second predetermined voltage and this grid.Wherein, At least one imput output circuit uses as normal imput output circuit; Wherein interrupt the part circuit; Make: the grid of this metal oxide semiconductor transistor is not coupled to the drain electrode of this first predetermined voltage and this metal oxide semiconductor transistor, and the drain electrode of this metal oxide semiconductor transistor is not coupled to this second predetermined voltage.Wherein the circuit of this imput output circuit that is not used is interrupted; Make in this imput output circuit that is not used: this drain electrode of this metal oxide semiconductor transistor is not coupled to this grid of this first predetermined voltage and this metal oxide semiconductor transistor, and makes this grid of this metal oxide semiconductor transistor not be coupled to this second predetermined voltage.
According to a third aspect of the invention we, disclosed a kind of method that in described according to a first aspect of the invention integrated circuit, forms coupling capacitance, this method comprises: select at least one imput output circuit that is not used from said imput output circuit; And the circuit that interrupts the part of this imput output circuit that is not used; Make in this imput output circuit that is not used: transistorized this grid of this second P-type mos does not couple this first a P-type mos transistor and a N type metal oxide semiconductor transistor; Also make transistorized this drain electrode of this second P-type mos not couple this connection gasket; Also make transistorized this grid of the 3rd N type metal oxide semiconductor not couple the 3rd P-type mos transistor and the 2nd N type metal oxide semiconductor transistor, form coupling capacitance by this.
According to a forth aspect of the invention, disclosed a kind of method that in described according to a second aspect of the invention integrated circuit, forms coupling capacitance, this method comprises: select at least one imput output circuit that is not used from said imput output circuit; And the circuit that interrupts the part of this imput output circuit that is not used; Make in this imput output circuit that is not used: this drain electrode of this metal oxide semiconductor transistor is not coupled to this grid of this first predetermined voltage and this metal oxide semiconductor transistor, and makes this grid of this metal oxide semiconductor transistor not be coupled to this second predetermined voltage.
By above-mentioned example, the imput output circuit that is not used capable of using forms the coupling capacitance of integrated circuit, to reduce the signal level of noise of integrated circuit.
Description of drawings
The coupling capacitance that Fig. 1 shows according to the first embodiment of the present invention forms circuit.
The coupling capacitance that Fig. 2 shows according to a second embodiment of the present invention forms circuit.
The reference numeral explanation
100,200 imput output circuits
101,105,107P type metal oxide semiconductor
103,109,111N type metal oxide semiconductor
113 connection gaskets
201 metal oxide semiconductor transistors
Embodiment
The coupling capacitance that Fig. 1 shows according to the first embodiment of the present invention forms circuit 100.As shown in Figure 1, it was the imput output circuit in the integrated circuit originally that coupling capacitance forms circuit 100, and it comprises one first scheduled voltage V
Dd, one second scheduled voltage GND, P-type mos 101,105 and 107, N type metal oxide semiconductor 103,109 and 111.The drain electrode of P-type mos transistor 101 is coupled to the second predetermined voltage GND.The drain electrode of N type metal oxide semiconductor transistor 103 also is coupled to the second predetermined voltage GND.The source electrode of P-type mos transistor 105 couples the first predetermined voltage Vdd and its drain electrode couples the first predetermined voltage Vdd and connection gasket 113, and its grid is coupled to the drain electrode of the second predetermined voltage GND, P-type mos transistor drain 101 and N type metal oxide semiconductor transistor 103.
The drain electrode of P-type mos transistor 107 is coupled to the first predetermined voltage Vdd.The drain electrode of N type metal oxide semiconductor transistor 109 is coupled to the first predetermined voltage Vdd.The drain electrode of N type metal oxide semiconductor transistor 111 couples the second predetermined voltage GND and connection gasket 113.
In structure shown in Figure 1, when using as normal imput output circuit, just interrupt X as if desire
1, X
2, X
3, and X
4The place.But, then must interrupt Y if will use as coupling capacitance
1, Y
2And Y
3The place; Make the grid of P-type mos transistor 105 not couple P-type mos transistor 101 and N type metal oxide semiconductor transistor 103; Also make the drain electrode of P-type mos transistor 105 not couple connection gasket 113; Also make the grid of N type metal oxide semiconductor transistor 111 not couple P-type mos transistor 107 and N type metal oxide semiconductor transistor 109, form coupling capacitance by this.
The coupling capacitance that Fig. 2 shows according to a second embodiment of the present invention forms circuit 200.Coupling capacitance formation circuit 200 is generally a part of of imput output circuit and uses as ESD protection circuit, and it comprises a metal oxide semiconductor transistor 201, and its drain electrode is coupled to the first predetermined voltage V
DdWith the second predetermined voltage GND and its grid, and the grid of metal oxide semiconductor transistor 201 also is coupled to the first predetermined voltage V
DdWith the second predetermined voltage GND, and the source electrode of metal oxide semiconductor transistor 201 couples second predetermined voltage GND and the grid.If desire to use, then interrupt X as ESD protection circuit
1And X
2The place.But, then interrupt Y if will form coupling capacitance
1And Y
2The place, so can make: the drain electrode of metal oxide semiconductor transistor 201 is not coupled to the first predetermined voltage V
DdWith the grid of metal oxide semiconductor transistor 201, and make the grid of metal oxide semiconductor transistor 201 not be coupled to the second predetermined voltage GND.In this example, switch module 201 is a N type metal oxide semiconductor, but can also replace by a P-type mos, and just the height of voltage configuration meeting is different with this embodiment.
It is noted that Fig. 1 imput output circuit shown in Figure 2 is only in order to for example, is not in order to limiting the present invention, and the imput output circuit of other structure also can use in the present invention.
Therefore, notion of the present invention can be sketched: a kind of method that in an integrated circuit, forms coupling capacitance, a plurality of imput output circuits that this integrated circuit comprises a core circuit and is coupled to this core circuit.The method comprises, and selects at least one specific imput output circuit from imput output circuit.The circuit of some that interrupts specific imput output circuit is to form the coupling capacitance of this integrated circuit.And in a preferred embodiment; Each imput output circuit comprises at least one switch module in the imput output circuit; And the circuit of specific imput output circuit is interrupted makes that a control end of switch module is coupled to one first predetermined voltage in the specific imput output circuit, and other end is coupled to one second predetermined voltage.
And interrupt the method for circuit, can when making integrated circuit, change the light shield design to realize interrupting the purpose of circuit.But also can not change the light shield design, after the circuit manufacturing is accomplished, otherwise interrupt circuit again.
By above-mentioned example, the imput output circuit that is not used capable of using forms the coupling capacitance of integrated circuit, to reduce the signal level of noise of integrated circuit.
The above is merely embodiments of the invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (10)
1. integrated circuit comprises:
One core circuit;
A plurality of imput output circuits are coupled to this core circuit; And
A plurality of connection gaskets are coupled to said imput output circuit respectively;
A part of connection in the wherein said connection gasket and another is not partly connected, and at least one imput output circuit that is not used is coupled to not connected connection gasket;
Each imput output circuit comprises in the wherein said imput output circuit:
One first P-type mos transistor, its drain electrode are coupled to one second predetermined voltage;
One the one N type metal oxide semiconductor transistor, its drain electrode is coupled to this second predetermined voltage;
One second P-type mos transistor; Its source electrode couples one first predetermined voltage and its drain electrode couples this first predetermined voltage and this connection gasket, and its grid is coupled to this second predetermined voltage, this first P-type mos transistor drain and a N type metal oxide semiconductor transistor drain;
One the 3rd P-type mos transistor, its drain electrode are coupled to this first predetermined voltage;
One the 2nd N type metal oxide semiconductor transistor, its drain electrode is coupled to this first predetermined voltage; And
One the 3rd N type metal oxide semiconductor transistor, its drain electrode couples this second predetermined voltage and this connection gasket;
Wherein, at least one imput output circuit uses as normal imput output circuit, wherein interrupts the part circuit, makes:
This first P-type mos transistor drain, a N type metal oxide semiconductor transistor drain and the transistorized grid of this second P-type mos all do not couple this second predetermined voltage; The 3rd P-type mos transistor drain, the 2nd N type metal oxide semiconductor transistor drain and the transistorized grid of the 3rd N type metal oxide semiconductor all do not couple this first predetermined voltage; This second P-type mos transistor drain does not couple this first predetermined voltage, and the 3rd N type metal oxide semiconductor transistor drain does not couple this second predetermined voltage;
And the circuit of the imput output circuit that this is not used is interrupted, and makes in this imput output circuit that is not used:
Transistorized this grid of this second P-type mos does not couple this first a P-type mos transistor and a N type metal oxide semiconductor transistor; Also make transistorized this drain electrode of this second P-type mos not couple this connection gasket; Also make transistorized this grid of the 3rd N type metal oxide semiconductor not couple the 3rd P-type mos transistor and the 2nd N type metal oxide semiconductor transistor, form coupling capacitance by this.
2. integrated circuit comprises:
One core circuit;
A plurality of imput output circuits are coupled to this core circuit; And
A plurality of connection gaskets are coupled to said imput output circuit respectively;
A part of connection in the wherein said connection gasket and another is not partly connected, and at least one imput output circuit that is not used is coupled to not connected connection gasket;
Each imput output circuit comprises in the wherein said imput output circuit:
One metal oxide semiconductor transistor; Its drain electrode is coupled to one first predetermined voltage and one second predetermined voltage and its grid; And this grid of this metal oxide semiconductor transistor also is coupled to this first predetermined voltage and this second predetermined voltage, and the source electrode of this metal oxide semiconductor transistor couples this second predetermined voltage and this grid;
Wherein, at least one imput output circuit uses as normal imput output circuit, wherein interrupts the part circuit, makes:
The grid of this metal oxide semiconductor transistor is not coupled to the drain electrode of this first predetermined voltage and this metal oxide semiconductor transistor, and the drain electrode of this metal oxide semiconductor transistor is not coupled to this second predetermined voltage;
Wherein the circuit of this imput output circuit that is not used is interrupted, and makes in this imput output circuit that is not used:
This drain electrode of this metal oxide semiconductor transistor is not coupled to this grid of this first predetermined voltage and this metal oxide semiconductor transistor, and makes this grid of this metal oxide semiconductor transistor not be coupled to this second predetermined voltage.
3. a coupling capacitance forms circuit, comprises at least one circuit module, and said circuit module comprises:
One first P-type mos transistor, its drain electrode are coupled to one second predetermined voltage;
One the one N type metal oxide semiconductor transistor, its drain electrode is coupled to this second predetermined voltage;
One second P-type mos transistor; Its source electrode couples one first predetermined voltage and its drain electrode couples this first predetermined voltage and a connection gasket, and its grid is coupled to this second predetermined voltage, this first P-type mos transistor drain and a N type metal oxide semiconductor transistor drain;
One the 3rd P-type mos transistor, its drain electrode are coupled to this first predetermined voltage;
One the 2nd N type metal oxide semiconductor transistor, its drain electrode is coupled to this first predetermined voltage; And
One the 3rd N type metal oxide semiconductor transistor, its drain electrode couples this second predetermined voltage and this connection gasket;
And the circuit of at least one circuit module that is not used is interrupted in the said circuit module, makes in this circuit module that is not used:
Transistorized this grid of this second P-type mos does not couple this first a P-type mos transistor and a N type metal oxide semiconductor transistor; Also make transistorized this drain electrode of this second P-type mos not couple this connection gasket; Also make the transistorized grid of the 3rd N type metal oxide semiconductor not couple the 3rd P-type mos transistor and the 2nd N type metal oxide semiconductor transistor, form coupling capacitance by this.
4. a coupling capacitance forms circuit, comprises at least one circuit module, and said circuit module comprises:
One metal oxide semiconductor transistor; Its drain electrode is coupled to one first predetermined voltage and one second predetermined voltage and its grid; And this grid of this metal oxide semiconductor transistor also is coupled to this first predetermined voltage and this second predetermined voltage, and the source electrode of this metal oxide semiconductor transistor couples this second predetermined voltage and this grid;
And the circuit of at least one circuit module that is not used is interrupted in the said circuit module, makes in this circuit module that is not used:
This drain electrode of this metal oxide semiconductor transistor is not coupled to this grid of this first predetermined voltage and this metal oxide semiconductor transistor, and makes this grid of this metal oxide semiconductor transistor not be coupled to this second predetermined voltage.
5. coupling capacitance as claimed in claim 4 forms circuit, and wherein this step that interrupts the circuit of this circuit module that is not used is implemented to change the light shield of making an integrated circuit, and wherein this coupling capacitance forms circuit and is contained in this integrated circuit.
6. coupling capacitance as claimed in claim 4 forms circuit, and wherein this step that interrupts the circuit of this circuit module that is not used is after an integrated circuit manufacturing is accomplished, to implement, and wherein this coupling capacitance forms circuit and is contained in this integrated circuit.
7. method that in integrated circuit as claimed in claim 1, forms coupling capacitance, this method comprises:
Select at least one imput output circuit that is not used from said imput output circuit; And
Interrupt the circuit of the part of this imput output circuit that is not used, make in this imput output circuit that is not used:
Transistorized this grid of this second P-type mos does not couple this first a P-type mos transistor and a N type metal oxide semiconductor transistor; Also make transistorized this drain electrode of this second P-type mos not couple this connection gasket; Also make transistorized this grid of the 3rd N type metal oxide semiconductor not couple the 3rd P-type mos transistor and the 2nd N type metal oxide semiconductor transistor, form coupling capacitance by this.
8. method that in integrated circuit as claimed in claim 2, forms coupling capacitance, this method comprises:
Select at least one imput output circuit that is not used from said imput output circuit; And
Interrupt the circuit of the part of this imput output circuit that is not used, make in this imput output circuit that is not used:
This drain electrode of this metal oxide semiconductor transistor is not coupled to this grid of this first predetermined voltage and this metal oxide semiconductor transistor, and makes this grid of this metal oxide semiconductor transistor not be coupled to this second predetermined voltage.
9. like claim 7 or 8 described methods, wherein this step of circuit that interrupts the some of this imput output circuit that is not used is implemented to change the light shield of making this integrated circuit.
10. like claim 7 or 8 described methods, wherein this step of circuit that interrupts the some of this imput output circuit that is not used is after this integrated circuit manufacturing is accomplished, to implement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100939353A CN101567370B (en) | 2008-04-23 | 2008-04-23 | Coupling capacitance forming circuit, integrated circuit using same and correlative method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100939353A CN101567370B (en) | 2008-04-23 | 2008-04-23 | Coupling capacitance forming circuit, integrated circuit using same and correlative method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN101567370A CN101567370A (en) | 2009-10-28 |
| CN101567370B true CN101567370B (en) | 2012-01-04 |
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| Application Number | Title | Priority Date | Filing Date |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5898205A (en) * | 1997-07-11 | 1999-04-27 | Taiwan Semiconductor Manufacturing Co. Ltd. | Enhanced ESD protection circuitry |
| US5923202A (en) * | 1997-03-03 | 1999-07-13 | National Semiconductor Corporation | Input/output overvoltage containment circuit for improved latchup protection |
-
2008
- 2008-04-23 CN CN2008100939353A patent/CN101567370B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5923202A (en) * | 1997-03-03 | 1999-07-13 | National Semiconductor Corporation | Input/output overvoltage containment circuit for improved latchup protection |
| US5898205A (en) * | 1997-07-11 | 1999-04-27 | Taiwan Semiconductor Manufacturing Co. Ltd. | Enhanced ESD protection circuitry |
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| Publication number | Publication date |
|---|---|
| CN101567370A (en) | 2009-10-28 |
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