CN101772841A - 具有穿透主体的传导通路的封装式集成电路装置及其制造方法 - Google Patents

具有穿透主体的传导通路的封装式集成电路装置及其制造方法 Download PDF

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CN101772841A
CN101772841A CN200880102233A CN200880102233A CN101772841A CN 101772841 A CN101772841 A CN 101772841A CN 200880102233 A CN200880102233 A CN 200880102233A CN 200880102233 A CN200880102233 A CN 200880102233A CN 101772841 A CN101772841 A CN 101772841A
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embedded
indivedual
embedded nude
nude film
conduction path
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CN101772841B (zh
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江东必
谢永富
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明揭示一种装置(400)，其包括：至少一个集成电路裸片(12)，其至少一部分定位于包封材料主体(20)中；以及至少一个传导通路(32、34)，其延伸穿过所述包封材料主体。

Description

具有穿透主体的传导通路的封装式集成电路装置及其制造方法
技术领域
本文所揭示的标的物大体上针对于封装集成电路装置的领域，且更明确地说，针对于具有穿透主体的传导通路的封装式集成电路装置及其各种制造方法。
背景技术
集成电路技术使用电装置(例如，晶体管、电阻器、电容器，等等)以配制大量功能电路阵列。这些电路的复杂性要求使用不断增加的数目的链接电装置，使得电路可执行其既定功能。随着晶体管数目增加，集成电路尺寸缩小。半导体工业中的一个挑战为开发用于电连接及封装在相同及/或不同晶片或芯片上所制造的电路装置的改进方法。一般来说，在半导体工业中需要构造在硅芯片/裸片上占据较小表面面积的晶体管。
在半导体装置组合件的制造中，最常见地将单个半导体裸片并入于每一密封式封装中。使用许多不同封装式样，包括双列直插式封装(dual inline package，DIP)、弯曲直插式封装(zig-zag inline package，ZIP)、小型J型弯管(small outline J-bend，SOJ)、薄小型封装(thin small outline package，TSOP)、塑料带引线芯片载体(plastic leaded chipcarrier，PLCC)、小型集成电路(small outline integrated circuit，SOIC)、塑料四方扁平封装(plastic quad flat pack，PQFP)及互相交叉引线框(interdigitated leadframe，IDF)。一些半导体装置组合件在包封之前连接到例如电路板等衬底。制造者经受恒定压力来减小封装式集成电路装置的尺寸且增加封装集成电路装置的封装密度。
在一些情况下，已将封装式集成电路装置堆叠于彼此的顶部上，以致力于节省结构空间。用于将堆叠式封装式集成电路装置传导地耦合到彼此的现有技术通常涉及形成焊球或导线接头以建立此连接。所需要的是用于将堆叠式封装式集成电路装置传导地耦合到彼此的新式且改进的技术。
附图说明
可通过参考以下结合附图所作的描述来理解本标的物，在附图中相同参考标号识别相同元件，且在附图中：
图1为如本文所描述的具有多个传导穿透主体通路的说明性封装式集成电路裸片的示意性描绘；
图2为如本文所描述的具有多个传导穿透主体通路的包含多个裸片的说明性封装式集成电路的示意性描绘；
图3为本文所揭示的说明性堆叠式封装式装置的示意性横截面图；
图4为本文所揭示的另一说明性堆叠式封装式装置的示意性横截面图；
图5为本文所揭示的又一说明性堆叠式封装式装置的示意性横截面图；
图6A到图6H示意性地描绘形成本文所揭示的堆叠式封装式装置的一种说明性方法；且
图7A到图7I示意性地描绘形成本文所揭示的堆叠式封装式装置的另一说明性方法。
尽管本文所揭示的标的物可容易做出各种修改及替代形式，但其特定实施例已在图式中借助于实例加以展示且在本文中加以详细地描述。然而，应理解，本文中对特定实施例的描述不希望将本发明限制于所揭示的特定形式，而是相反地，本发明将涵盖属于由所附权利要求书所界定的本发明的精神及范围内的所有修改、均等物及替代方案。
具体实施方式
下文描述本标的物的说明性实施例。为了清楚起见，本说明书中并未描述实际实施方案的所有特征。当然，将了解，在任何此类实际实施例的开发中，必须做出众多实施方案特定的决策以实现开发者的特定目标，例如遵从系统相关及商业相关的约束，所述约束将在每个实施方案之间有所变化。此外，将了解，此开发努力可能是复杂且耗时的，但对于得益于本发明的所属领域的技术人员来说将只是例行任务。
虽然将图式所示的各种区及结构描绘为具有非常精确的锐利配置及轮廓，但所属领域的技术人员认识到，实际上，这些区及结构并不如图式中所指示那样精确。另外，图式中所描绘的各种特征及掺杂区的相对尺寸与已制造装置上的那些特征或区的尺寸相比可被夸大或减小。然而，包括附图以描述且解释本文所揭示的标的物的说明性实例。
图1描绘如本文所描述的封装式集成电路装置100的一个说明性实施例。封装式集成电路装置100包含集成电路裸片12，其具有多个接合垫14、传导线路16(有时被称为再分配层(RDL))及延伸穿过包封材料(例如，模制化合物材料)主体20的至少一个传导互连18(有时被称为传导通路)。传导通路18界定穿过主体20的厚度(即，在主体20的前部13与后部15之间)的传导流动路径。可使用多种已知技术及结构而将传导通路18及集成电路裸片12传导地耦合到彼此。在所描绘实例中，传导线路16将传导通路18传导地耦合到集成电路裸片12。根据已知处理技术而将多个示意性地描绘的焊球24形成于封装式集成电路装置100上。可采用焊球24或其它类似连接以将封装式集成电路装置100传导地耦合到另一结构(例如，印刷电路板)。在图1中，裸片12嵌入包封材料主体20中。如本文中所使用，当陈述一个或一个以上裸片12嵌入包封材料主体中时，应理解，仅裸片12的主体的若干部分需要定位于包封材料中。并不要求包封材料环绕裸片12的主体的所有侧，但可视特定应用而在需要时采用所述配置。
图2描绘如本文所描述的封装式集成电路装置200的一个说明性实施例。封装式集成电路装置200包含嵌入单个包封材料(例如，模制化合物材料)主体20中的多个集成电路裸片12(展示两个)。在本文所描绘的说明性实例中，裸片12中的每一者具有相同物理尺寸。然而，如所属领域的技术人员在完成阅读本申请案之后将理解，既不要求裸片12为相同物理尺寸，也不要求其必须执行相同功能。图2所示的裸片12中的每一者具有多个接合垫14、传导线路16(有时被称为再分配层(RDL))及延伸穿过包封材料主体20的至少一个传导互连18(有时被称为传导通路)。由于装置200包含多个集成电路裸片12，所以其可被视作多芯片模块(MCM)。如在图1中，根据已知处理技术而将多个示意性地描绘的焊球24形成于封装式集成电路装置200上。可采用焊球24或其它类似连接以将封装式集成电路装置200传导地耦合到另一结构(例如，印刷电路板)。
在所描绘实施例中，图2中的传导通路18中的每一者延伸穿过主体12的厚度。可使用多种已知技术及结构中的任一者来建立传导通路18与嵌入式集成电路裸片12之间的传导耦合。在图2所示的实例中，传导通路18中的至少一者通过一个或一个以上线路16而传导地耦合到集成电路裸片12中的一者，而传导通路18中的另一者同样通过一个或一个以上线路16而传导地耦合到其它集成电路裸片12。
如所属领域的技术人员在完成阅读本申请案之后将认识到，本文所揭示的方法及技术可应用于几乎任何类型的可形成于裸片12上的集成电路装置。另外，示意性地描绘的接合垫14、传导线路16及穿透主体的传导互连18的配置及位置可视特定应用而变化。
图3到图5为多个堆叠式且封装式集成电路装置的示意性横截面图。在图3所描绘的说明性实例中，堆叠式封装300包含多个个别嵌入式裸片10A到10D。在图3所描绘的说明性实例中，仅描绘四个说明性个别嵌入式裸片10A到10D。如上文所阐述，应理解，在参考嵌入式裸片或个别嵌入式裸片时，结构仅需要包含至少一个集成电路裸片，其中裸片主体的一部分定位于包封材料主体20中。然而，如所属领域的技术人员在完成阅读本申请案之后将认识到，堆叠式封装300中的个别嵌入式裸片10的数目可视特定应用而变化，即，此堆叠300内的个别嵌入式裸片10的数目可多于或少于图3所描绘的说明性四个。
图3中的说明性个别嵌入式裸片10A到10D中的每一者包含集成电路裸片12、多个接合垫14、传导线路16(有时被称为再分配层(RDL))、延伸穿过包封材料主体20的多个传导互连18(有时被称为传导通路)。多个传导结构22提供于邻近个别嵌入式裸片10之间以在各种嵌入式裸片10A到10D之间提供导电路径。根据已知处理技术而将多个示意性地描绘的焊球24形成于封装式裸片10D上。可采用焊球24或其它类似连接以将堆叠式封装300传导地耦合到另一结构(例如，印刷电路板)。
如所属领域的技术人员在完成阅读本申请案之后将认识到，本文所揭示的方法及技术可应用于几乎任何类型的可形成于裸片12上且封装于堆叠式配置中的集成电路装置。另外，图3所示的示意性地描绘的接合垫14、传导互连18及传导结构22的配置及位置可视特定应用而变化。在图3所描绘的实施例中，所有封装式裸片被定向为嵌入式裸片10的前侧13面向邻近嵌入式裸片10的后侧15。
图4描绘堆叠式封装式装置400的另一说明性实施例。类似于图3所示的实施例，图4中的实施例包含四个说明性个别嵌入式裸片10A到10D。在图4中，个别嵌入式裸片10A到10D被组装为群组10E及10F，之后将这些群组组装成图4所示的结构。第一群组10E包含个别嵌入式裸片10A及10B，而第二群组10F包含个别嵌入式裸片10C及10D。多个传导互连或通路32延伸穿过包含第一群组10E的多个裸片10的主体20，而多个传导互连或通路34延伸穿过包含第二群组10F的多个裸片10的主体20。
多个传导结构22在所述两个群组10E与10F之间提供导电路径。每一群组内的个别嵌入式裸片10可使用粘合材料28固定到彼此。请注意，在图4所描绘的说明性实例中，邻近的嵌入式裸片10的后侧15被定位成面向彼此。如所属领域的技术人员在完全阅读本申请案之后将认识到，可如图4所描绘而堆叠的群组(例如，群组10E及10F)的数目可视特定应用而变化，即，比图4所描绘的说明性两个群组多或少的群组可被组装成最终堆叠式封装400。类似地，每一群组内的个别嵌入式裸片10的数目可大于图4中的群组10e及10F中所描绘的说明性两个。
可在需要时组合图3及图4所描绘的结构。举例来说，图5描绘说明性堆叠式封装式装置500，其中底部两个嵌入式裸片10A到10B被封装为群组10E，而上部两个嵌入式裸片10C到10D则如图3所描绘进行封装。因此，容易明白的是，本文所揭示的方法及装置提供极大灵活性，因为其涉及创建堆叠式封装式装置以进而减小结构空间消耗且改进封装密度。此外，在图3到图5中，个别嵌入式裸片10中的每一者被描绘为具有嵌入其中的单个集成电路裸片12。根据本发明的一个方面，类似于图2所描绘的多芯片实施例，个别嵌入式裸片10可包含多个个别集成电路裸片12。也就是说，本文所揭示的方法及装置可用于包含单个或多个集成电路裸片12的个别嵌入式裸片10。为了易于参考，以下描述将参考包含单个集成电路裸片12的个别嵌入式裸片10，但所述方法可容易地应用于在个别嵌入式裸片的单个包封材料主体20中嵌入多个集成电路裸片12。
图6A到图6H描绘形成本文所揭示的装置的一种说明性方法。在图6A中，将多个已知良好集成电路裸片12放置成前侧13向下位于说明性牺牲结构30上方。在一个说明性实例中，牺牲结构30可为膜框，其中分割带跨越膜框而定位。结构30在其稍后将被移除的意义上为牺牲的。在图6B中，将包封材料(例如，模制化合物)主体20形成于集成电路裸片12周围及结构30上方，即，将集成电路裸片12嵌入主体20中。可执行传统模制技术(例如，注射模制)以形成包封材料主体20。其后，如图6C所示，可移除牺牲结构30。在本文所描述的说明性实例中，归因于使用粘合带作为结构30的部分，结构30可简单地被剥离。
接下来，如图6D所示，根据传统技术而将传导线路16形成于集成电路裸片12及主体12的前侧13上方。当然，传导线路16可具有任何所要配置，且其可由任何所要材料制成。接着，如图6E所指示，如所指示而将多个开口或通路17形成穿过主体20。可通过多种已知技术(例如，激光钻孔、蚀刻等)来形成开口17。在一些应用中，可作为形成开口17的工艺的部分来形成遮蔽层(未图示)。开口17可具有任何所要形状或配置。请注意，在本文所描绘的说明性实例中，从嵌入式裸片10的主体20的后侧15朝向前侧13形成开口17。还请注意，在此特定实例中，开口17曝露但不延伸穿过形成于嵌入式裸片10的前侧13上的传导互连16。其后，如图6F所示，以传导材料(例如，铜、铝、银等)来填充开口17以形成传导互连18。视特定应用而定，可使用多种已知技术(例如，电镀、沉积等)中的任一者而在开口17中形成传导材料，且可采用多种不同传导材料。
在图6G中，使用已知技术在嵌入式裸片10A到10B上形成多个传导结构22。在一些情况下，可作为形成传导互连18的工艺的部分来形成传导结构22。接着，如图6H所示，沿切割线37执行分割或单一化工艺以产生说明性个别嵌入式裸片10A及10B。
接下来，使个别嵌入式裸片10A到10B经受多种测试以确认其针对于其既定应用的可接受性。一旦嵌入式裸片10A到10B已成功地通过所述测试，其便准备好运送到顾客。在其它应用中，经测试的嵌入式裸片10A到10B可被组装成如本文所描绘的堆叠式封装式装置300、400、500。在图3所描绘的实例中，如图3所描绘而定位多个个别嵌入式裸片10，且执行回焊工艺以在个别嵌入式裸片(例如，裸片10A)上的传导结构22与邻近的嵌入式裸片(例如，裸片10B)上的传导互连18之间建立电连接。可使用传统技术在说明性裸片10上形成说明性焊球24。可在工艺流程期间在任何所要点处形成焊球24。举例来说，可在如图3所描绘那样组装所有嵌入式裸片10A到10D之后形成焊球24。或者，可在如图3所描绘那样将个别嵌入式裸片10D与其它个别嵌入式裸片进行组装之前在个别嵌入式裸片10D上方形成焊球24。
图7A到图7I描绘形成本文所揭示的装置的另一说明性方法。图7A到图7D所描绘的步骤与先前相对于图6A到图6D所描述的步骤相同。因此，将不重复对图7A到图7D的详细论述。在图7E中，使用粘合材料28将图7D所描绘的多个结构固定到彼此。其后，在图7F中，将多个开口或通路31形成穿过图7E所描绘的经组合结构的主体20。可通过多种已知技术(例如，激光钻孔、蚀刻等)来形成开口31。在一些应用中，可作为形成开口31的工艺的部分来形成遮蔽层(未图示)。开口31可具有任何所要形状或配置。请注意，在本文所描绘的说明性实例中，开口31延伸穿过形成于个别结构中的每一者的前侧13上的传导互连16。其后，如图7G所示，以传导材料(例如，铜、铝、银等)来填充开口31以形成穿透主体的传导通路32。视特定应用而定，可使用多种已知技术(例如，电镀、沉积等)中的任一者在开口31中形成传导材料，且可采用多种不同的传导材料。
在图7H中，使用已知技术而在图7G所描绘的结构上形成多个传导结构22。在一些情况下，可作为形成传导互连32的工艺的部分来形成传导结构22。接下来，如图7I所示，沿切割线37而执行分割或单一化工艺以产生个别嵌入式裸片的说明性群组10E及10F。
接下来，使嵌入式裸片群组10E到10F经受多种测试以确认其对于其既定应用的可接受性。一旦群组10E到10F已成功地通过所述测试，其便准备好运送到顾客。在一些应用中，可如本文所描述而将嵌入式裸片群组10E到10F组装成堆叠式封装式装置。在图4所描绘的实例中，如图4所描绘而定位嵌入式裸片群组10E及10F，且执行回焊工艺以在第一群组10E上的传导结构22与邻近群组10F上的传导通路32之间建立电连接。可使用传统技术而在群组10F中的说明性个别嵌入式裸片上形成说明性焊球24。可在工艺流程期间在任何所要点处形成焊球24。举例来说，可在如图4所描绘而组装两个说明性群组10E到10F之后形成焊球24。或者，可在如图4所描绘而将两个群组组装于一起之前在群组10F中的个别嵌入式裸片中的一者上方形成焊球24。
如所属领域的技术人员在完成阅读本申请案之后将认识到，本发明可提供用于封装个别裸片且提供堆叠式封装式集成电路装置的非常有效的方式。可在多个裸片上单次执行本文所执行的许多处理，这与在个别裸片上一次一个地执行所述操作相反。举例来说，尽管图6A到图6H及图7A到图7I中描绘两个说明性裸片12，但视所采用的处理工具的处理能力而定，可在任何所要数目的裸片上执行本文所描述的处理步骤。简单地说，可采用晶片级处理技术来增加封装操作的效率，即，可在多个裸片上同时执行处理操作。

Claims (53)

1.一种装置，其包含：
至少一个集成电路裸片，其至少一部分定位于包封材料主体中；及
至少一个传导通路，其延伸穿过所述包封材料主体。
2.根据权利要求1所述的装置，其中所述装置包含多个个别集成电路裸片，其每一者具有定位于所述包封材料主体中的一部分。
3.根据权利要求2所述的装置，其中所述装置包含延伸穿过所述包封材料主体的多个所述传导通路，且其中所述传导通路中的至少一者传导地耦合到所述多个集成电路裸片中的一者且所述传导通路中的另一者传导地耦合到所述多个集成电路裸片中的另一者。
4.根据权利要求1所述的装置，其中所述至少一个传导通路通过传导线路而传导地耦合到所述至少一个集成电路裸片。
5.根据权利要求1所述的装置，其中所述至少一个传导通路延伸穿过所述包封材料主体的厚度。
6.根据权利要求1所述的装置，其中所述至少一个传导通路在所述包封材料主体的前侧与后侧之间界定传导流动路径。
7.一种装置，其包含：
多个集成电路裸片，其每一者嵌入单个包封材料主体中；及
多个传导通路，其延伸穿过所述包封材料主体。
8.根据权利要求7所述的装置，其中所述传导通路中的至少一者传导地耦合到所述多个集成电路裸片中的一者且所述传导通路中的另一者传导地耦合到所述多个集成电路裸片中的另一者。
9.根据权利要求8所述的装置，其中所述传导通路通过传导线路而传导地耦合到所述相应集成电路裸片。
10.根据权利要求7所述的装置，其中所述多个传导通路延伸穿过所述单个包封材料主体的厚度。
11.根据权利要求7所述的装置，其中所述多个传导通路在所述单个包封材料主体的前侧与后侧之间界定多个传导流动路径。
12.根据权利要求7所述的装置，其中所述多个裸片中的每一者具有相同物理尺寸。
13.一种装置，其包含：
多个个别嵌入式裸片，所述个别嵌入式裸片中的每一者包含包封材料主体及延伸穿过所述包封材料主体的至少一个传导通路，所述多个嵌入式裸片被定位成邻近彼此；及
至少一个传导结构，其定位于邻近的个别嵌入式裸片之间，所述传导结构在邻近的个别嵌入式裸片中的传导通路之间提供导电路径。
14.根据权利要求13所述的装置，其中所述传导通路延伸穿过所述包封材料主体的厚度。
15.根据权利要求13所述的装置，其中所述多个个别嵌入式裸片中的至少一者包含单个集成电路裸片。
16.根据权利要求13所述的装置，其中所述多个个别嵌入式裸片中的至少一者包含多个集成电路裸片。
17.根据权利要求13所述的装置，其中所述多个个别嵌入式裸片垂直地堆叠于彼此上方。
18.根据权利要求17所述的装置，其中所述多个个别嵌入式裸片经定位以使得所述个别嵌入式裸片中的一者的前侧面向邻近的个别嵌入式裸片的后侧。
19.一种装置，其包含：
第一及第二嵌入式裸片，所述第一及第二嵌入式裸片中的每一者包含包封材料主体，所述第一及第二嵌入式裸片中的每一者的后侧被定位成面向彼此；及
传导通路，其延伸穿过所述第一及第二嵌入式裸片两者的所述包封材料主体。
20.根据权利要求19所述的装置，其中所述传导通路从所述第一嵌入式裸片的前侧延伸到所述第二嵌入式裸片的前侧。
21.根据权利要求19所述的装置，其进一步包含定位于所述第一及第二嵌入式裸片的所述后侧之间的用于将所述第一及第二嵌入式裸片固定到彼此的粘合材料。
22.根据权利要求21所述的装置，其中所述第一及第二嵌入式裸片垂直地堆叠于彼此上方。
23.一种装置，其包含：
第一嵌入式裸片群组及第二嵌入式裸片群组，所述第一及第二嵌入式裸片群组中的每一者包含多个个别嵌入式裸片，所述个别嵌入式裸片中的每一者包含包封材料主体；
至少一个第一传导通路，其延伸穿过所述第一嵌入式裸片群组；
至少一个第二传导通路，其延伸穿过所述第二嵌入式裸片群组；及
至少一个传导结构，其定位于所述第一与第二嵌入式裸片群组之间，所述至少一个传导结构在所述第一与第二传导通路之间提供导电流动路径。
24.根据权利要求23所述的装置，其中所述第一及第二嵌入式裸片群组中的每一者中的所述个别嵌入式裸片中的每一者的后侧被定位成面向彼此。
25.根据权利要求24所述的装置，其中所述第一传导通路从所述第一嵌入式裸片群组中的一个别嵌入式裸片的前侧延伸到所述第一嵌入式裸片群组中的另一个别嵌入式裸片的前侧。
26.根据权利要求24所述的装置，其进一步包含定位于所述个别嵌入式裸片的所述面向后侧之间的粘合材料。
27.根据权利要求23所述的装置，其中所述第一传导通路经形成穿过所述第一嵌入式裸片群组中的所有所述个别嵌入式裸片的所述包封材料主体。
28.根据权利要求27所述的装置，其中所述第二传导通路经形成穿过所述第二嵌入式裸片群组中的所有所述个别嵌入式裸片的所述包封材料主体。
29.根据权利要求23所述的装置，其中所述个别嵌入式裸片中的每一者包含单个集成电路裸片。
30.根据权利要求23所述的装置，其中所述个别嵌入式裸片中的每一者包含多个集成电路裸片。
31.根据权利要求23所述的装置，其中所述第一及第二嵌入式裸片群组垂直地堆叠于彼此上方。
32.一种方法，其包含：
在至少一个集成电路裸片的至少一部分周围形成包封材料主体；
形成延伸穿过所述包封材料主体的至少一个传导通路；及
将所述至少一个传导通路传导地耦合到所述至少一个集成电路裸片。
33.根据权利要求32所述的方法，其中形成所述传导通路包含在所述包封材料主体中形成开口及以传导材料来填充所述开口。
34.根据权利要求32所述的方法，其中将所述至少一个传导通路传导地耦合到所述至少一个集成电路裸片包含形成连接到所述至少一个传导通路及所述至少一个集成电路的至少一个传导线路。
35.根据权利要求32所述的方法，其中形成所述包封材料主体包含执行注射模制工艺以形成所述包封材料主体。
36.根据权利要求32所述的方法，其中形成所述包封材料主体包含在多个个别集成电路裸片周围形成所述包封材料主体。
37.根据权利要求36所述的方法，其进一步包含执行单一化工艺以界定多个个别嵌入式裸片，所述裸片中的每一者包含单个集成电路裸片。
38.根据权利要求37所述的方法，其进一步包含：
将多个所述个别嵌入式裸片定位成邻近彼此；及
将所述个别嵌入式裸片中的第一者上的所述传导通路传导地耦合到所述个别嵌入式裸片中的第二者上的所述传导通路。
39.根据权利要求38所述的方法，其中定位所述多个所述个别嵌入式裸片以使得第一个别嵌入式裸片的前表面面向邻近个别嵌入式裸片的后侧。
40.根据权利要求38所述的方法，其中传导地耦合所述第一及第二个别嵌入式裸片上的所述传导通路包含在所述第一与第二个别嵌入式裸片之间形成传导结构。
41.根据权利要求39所述的方法，其进一步包含将所述第二个别嵌入式裸片堆叠于所述第一个别嵌入式裸片上方。
42.根据权利要求36所述的方法，其进一步包含执行单一化工艺以界定多个个别嵌入式裸片，所述裸片中的每一者包含多个集成电路裸片。
43.根据权利要求42所述的方法，其进一步包含：
将多个所述个别嵌入式裸片定位成邻近彼此；及
将所述个别嵌入式裸片中的第一者上的所述传导通路传导地耦合到所述个别嵌入式裸片中的第二者上的所述传导通路。
44.根据权利要求43所述的方法，其中定位所述多个个别嵌入式裸片以使得第一个别嵌入式裸片的第一表面面向邻近个别嵌入式裸片的后侧。
45.根据权利要求43所述的方法，其中传导地耦合所述第一及第二个别嵌入式裸片上的所述传导通路包含在所述第一与第二个别嵌入式裸片之间形成传导结构。
46.根据权利要求45所述的方法，其进一步包含将所述第二个别嵌入式裸片堆叠于所述第一个别嵌入式裸片上方。
47.一种方法，其包含：
将第一个别嵌入式裸片定位成邻近第二个别嵌入式裸片，所述第一及第二个别嵌入式裸片中的每一者包含包封材料主体；及
形成延伸穿过所述第一及第二个别嵌入式裸片两者的所述包封材料主体的至少一个传导通路。
48.根据权利要求47所述的方法，其进一步包含将所述至少一个传导通路传导地耦合到所述第一及第二个别嵌入式裸片中的一者中的至少一个集成电路裸片。
49.根据权利要求47所述的方法，其中所述第一及第二个别嵌入式裸片中的至少一者包含单个集成电路裸片。
50.根据权利要求47所述的方法，其中所述第一及第二个别嵌入式裸片中的至少一者包含多个集成电路裸片。
51.根据权利要求47所述的方法，其进一步包含在形成所述至少一个传导通路之前将所述第一及第二个别嵌入式裸片固定到彼此。
52.根据权利要求51所述的方法，其中将所述第一及第二个别嵌入式裸片固定到彼此包含将粘合材料施加到所述第一及第二个别嵌入式裸片中的至少一者。
53.根据权利要求47所述的方法，其中定位所述第一及第二个别嵌入式裸片以使得所述第一个别嵌入式裸片的后侧面向所述第二个别嵌入式裸片的后侧。
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US20200279834A1 (en) 2020-09-03
US11594525B2 (en) 2023-02-28
CN101772841B (zh) 2014-06-18
US20230197690A1 (en) 2023-06-22
KR101722264B1 (ko) 2017-03-31
WO2009045626A1 (en) 2009-04-09
US11398457B2 (en) 2022-07-26
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US9099571B2 (en) 2015-08-04
US10593653B2 (en) 2020-03-17
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US20100320585A1 (en) 2010-12-23
US7781877B2 (en) 2010-08-24
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US8723307B2 (en) 2014-05-13
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TW200915525A (en) 2009-04-01
US20150325554A1 (en) 2015-11-12

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