CN101777517B

CN101777517B - Method for manufacturing memory

Info

Publication number: CN101777517B
Application number: CN2009100452455A
Authority: CN
Inventors: 李俊; 庄晓辉; 王三坡; 兰国华
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2009-01-13
Filing date: 2009-01-13
Publication date: 2012-01-25
Anticipated expiration: 2029-01-13
Also published as: CN101777517A

Abstract

The invention discloses a method for manufacturing a memory, which comprises the following steps: forming a common source area, a common drain area and a bottom dielectric layer on a semiconductor substrate; sequentially stacking a floating gate, an insulating layer and a control gate on the bottom dielectric layer; depositing a nitride on the upper surface and lateral surfaces of the gate structure formed by stacking the floating gate, the insulating layer and the control gate; depositing an oxide on the surface of the nitride to fill up the gap formed in the gate structure above the common source area; removing part of the oxide; and removing the nitride above the common drain area. In the method, the layer of oxide is deposited after the nitride is deposited, a function of delaying etching is realized in the nitride removing process and Co ions are prevented from entering the bottom dielectric layer above the common source area in a subsequent Co ion injection process, so the charges in the floating gate is prevented from escaping to the bottom dielectric layer above the common source area, the holding capacity of the data stored in the floating gate is improved, and the memory data storage time is improved.

Description

Memory manufacturing

Technical field

The present invention relates to the semiconductor making method field, specifically, relate to a kind of memory manufacturing.

Background technology

Memory is used to store a large amount of digital informations, shows that according to investigation in the recent period worldwide, the memory chip trading volume accounts for 30% of semiconductor chip trading volume.For many years; The progress of technology and the increase of the market demand expedite the emergence of out a lot of highdensity various types of memory chips, like random asccess memory (RAM), dynamic random access memory (DRAM), read-only memory (ROM), Erasable Programmable Read Only Memory EPROM (EPROM), flash memory (FLASH) and ferroelectric memory (FRAM) etc.

At present the memory technology forward direction that improves integrated level and dwindle component size develops.When the user uses memory, remove and to require memory to possess high storage capacity, outside low-power consumption and the high reliability, the time data memory of memory has also been proposed high request, for example requiring time data memory is more than 10 years.

The time data memory of memory adopts data holding ability test (data retation testing) scheme to measure usually, and this scheme is generally:

In temperature baking 24 hours in 250 ℃ the environment at first with memory; The threshold voltage of testing memory stored unit (Vt) is worth then; If Vt, means that the data holding ability of this memory is lower less than predetermined value, its time data memory is also just shorter.

Existing memory manufacturing comprises step:

The first step: consult Figure 1A; In semiconductor substrate 1, form common source district 3 and be total to drain region 2; Form end dielectric layer 4 at semiconductor substrate 1 upper surface then; The presumptive area of dielectric layer 4 upper surfaces forms floating boom 5, insulating barrier 6 and control gate 7 formation grid structures successively the end of at again, and the zone in the matrix 1 that said grid structure covers is in common source district 3 and altogether between the drain region 2;

Second step: consult Figure 1B, the unlapped zone of the dielectric layer 4 upper surface grid structures end of at, and the upper surface of said grid structure and side, depositing nitride 8;

The 3rd step: consult Fig. 1 C, remove the nitride 8 on the unlapped zone of dielectric layer 4 upper surface grid structures, the end.

The 4th step: consult Fig. 1 D, adopt ion implantation technology, on the end dielectric layer 4 that exposes, inject cobalt (Co) ion and carry out, carry out chemical reaction then, make and on the said end dielectric layer 4 that is injecting Co ion zone, contain cobalt disilicide 10 (CoSi2).Because cobalt disilicide 10 is low-resistance phase materials; Its resistance ratio is lower; Therefore connect drain line in the drain surface that contains cobalt disilicide 10; The line impedance that makes drain line and drain surface form will reduce greatly, thereby can make circuit through drain line the speed of the memory cell reading of data of above-mentioned manufacturing greatly improved.

When the floating boom 5 of the memory that above-mentioned manufacturing process is processed carries out the data holding ability test; Fraction defective is more than 6%; The defective of above-mentioned memory manufacturing process is: in the 3rd step manufacture process; When in removing end dielectric layer 4, covering the nitride 8 of the region upper surface in drain region 2 altogether, the nitride 8 that covers the region upper surface in common source district 3 in the end dielectric layer 4 also can be removed, when causing follow-up injection Co ion; In the end dielectric layer 4 of 3 positions, common source district, also have the Co ion and inject, follow-up chemical reaction step makes the end dielectric layer 4 in 3 positions, common source district also contain cobalt disilicide 10.

So carrying out in the data holding ability test process to floating boom 5; After memory toasted through 24 hours; The electric charge that the tester finds to be stored in the floating boom 5 will be escaped in common source district 3, containing in the end dielectric layer 4 of cobalt disilicide 10; And then the memory data hold facility that causes testing out is relatively poor, and promptly the time data memory of memory reduces.

Summary of the invention

The technical problem that the present invention will solve provides a kind of memory manufacturing, to improve data holding ability.

For solving the problems of the technologies described above, memory manufacturing provided by the invention comprises the steps:

Form common source district and common drain region, end dielectric layer on the semiconductor substrate and on dielectric layer of the said end, stacking gradually formation floating boom, insulating barrier and control gate;

Pile up the grid structure upper surface and the side precipitated nitride of formation at said floating boom, insulating barrier and control gate;

Precipitated oxides on said nitride surface, to fill up the gap that said grid structure forms above the common source district, wherein, said grid structure is being total to the gap that forms above the drain region in the gap that forms above the common source district less than it;

Remove partial oxide, simultaneously, the gap above the common source district is the retention part sub-oxide also;

The nitride of removal above said drain region altogether.

Further, inject cobalt ions in the end dielectric layer on said drain region altogether;

The cobalt ions reaction of injecting is formed cobalt compounds;

On the end dielectric layer that forms cobalt compounds, form metal connecting line.

Further, said nitride is a silicon nitride.

Further, said cobalt compounds is a cobalt disilicide.

Further, said insulating barrier is the dielectric structure that comprises oxide-nitride thing-oxide or comprise the oxide-nitride thing.

Further, said insulating barrier is composition, oxide or the nitride of oxide and nitride.

Further, said floating boom and control gate are polysilicon.

Compare with existing memory manufacturing, the present invention precipitates one deck oxide again after forming nitride, piles up the gap above the common source district between the grid structure of formation to fill up a plurality of said floating booms, insulating barrier and control gate; For removing in the process of oxide in subsequent etching; Removal is after being total to the oxide that forms above the drain region, and the gap of top, common source district is the retention part sub-oxide also, removes in the nitride process in etching and plays the etched effect that delays; Make when etching is removed nitride; The gap of common source district top is the residual fraction nitride also, stops that the Co ion enters into the end dielectric layer in the common source district in the follow-up Co ion implantation process, thereby has avoided electric charge in the floating boom to escape into the end dielectric layer in common source district; Improve the data holding ability be stored in the floating boom, and then improve memory data memory time.

Description of drawings

Below in conjunction with accompanying drawing and embodiment manufacturing method of chip of the present invention is done further to specify.

Figure 1A-Fig. 1 D is the schematic cross-section of the memory manufacturing of prior art;

Fig. 2 A-Fig. 2 F is the memory manufacturing schematic cross-section of the embodiment of the invention.

Embodiment

See also Figure 1A; On semiconductor substrate 1, form common source district 3 and drain region 2 altogether, end dielectric layer 4 and the presumptive area of dielectric layer 4 upper surfaces stacks gradually and forms floating boom 5, insulating barrier 6 and control gate 7 and constitute the grid structures at the said end, the zone in the matrix 1 that said grid structure covers is in common source district 3 and altogether between the drain region 2.

Said floating boom 5 is polysilicon with control gate 6.Said insulating barrier 6 can be composition, oxide or the nitride of oxide and nitride; Such as the dielectric structure of ONO (oxide-nitride thing-oxide) or the dielectric structure of ON (oxide-nitride thing); In the present embodiment, said insulating barrier 6 is the dielectric structure of ONO stack.

See also Fig. 2 A, the grid structure upper surface and the side deposition that stack gradually formation at said floating boom 5, insulating barrier 6 and control gate 7 form the uniform nitride 8 of thickness, and said nitride 8 is a silicon nitride.

See also Fig. 2 B, deposition one deck oxide 9 on nitride 8 surfaces that above-mentioned deposition forms;

The grid structure that said floating boom 5, insulating barrier 6 and control gate 7 pile up formation in the gap that forms above the common source district 3 less than its gap that above drain region 2 altogether, forms; The gap of 3 tops, common source district is narrow; Broad is compared in the gap of 2 tops, drain region altogether; Therefore precipitate when forming said oxide 9; The oxide 9 that piles up the grid structure both sides deposition of formation from said floating boom 5, insulating barrier 6 and control gate 7 will fill up in the gap above the common source district 3 soon, above the common drain region 2 of broad, just form layer of even oxide 9.

See also Fig. 2 C; Adopt lithographic method to remove and cover the oxide 9 on the said nitride 8; Because the gap of 3 tops, common source district is narrow; The height that fills up the oxide 9 of formation in the gap above the common source district 3 is higher than the height of the oxide 9 that above drain region 2 altogether, forms far away, therefore is etched removal when finishing when the oxide 9 of 2 tops, drain region altogether, and 3 tops, common source district also have the residual oxide of part 9.

Further; Consult Fig. 2 D; Etching is removed the nitride 8 above drain region altogether, owing to remove in oxide layer 9 processes in above-mentioned etching, on the nitride above the common source district 38, also has part residual oxide 9; Therefore the thickness of the insulation system of common source district 3 top residual oxides 9 and nitride 8 stack formation is considerably beyond the thickness of the nitride 8 above common drain region 2; So common source district 3 and the nitride of 2 tops, drain region are altogether carried out etching when removing, above common source district 3, need first etching remove the residual oxide 9 in 3 tops, common source district again etching remove nitride 8.Therefore, residual oxide 9 plays the buffer delay corrasion, and nitride 8 etchings when said altogether 2 tops, drain region finish, the nitride 8 of 3 tops, common source district also not etching finish, thereby kept the residual nitride 8 of part.

See also Fig. 2 E and Fig. 2 F, accomplished last etching technics after, the end dielectric layer 4 on the said altogether drain region 2 comes out, and on dielectric layer of the said end 4, injects cobalt ions.Carry out chemical reaction then; In the present embodiment; Said cobalt ions carries out forming cobalt disilicide 10 (CoSi2) behind the chemical reaction, and cobalt disilicide 10 its resistance ratios are lower, connect drain line 11 on the surface of containing cobalt disilicide 10; Make drain line 11 and the line impedance that drain surface forms to reduce greatly, thereby can make circuit the speed of the memory cell reading of data of above-mentioned manufacturing greatly improved through drain line.

Because in the embodiment of the invention, the residual nitride of part 8 is contained in 3 tops in said common source district, therefore after injecting the Co ion; Because residual nitride 8 is isolated, the Co ion can't get into the end dielectric layer 4 in the common source district 3, carries out in the chemical reaction process follow-up; Can't form cobalt disilicide 10, avoid being stored in electric charge in the floating boom 5 and escape in the end dielectric layer 4 to the common source district 3, reduce the problem of floating boom 5 data holding abilities; Thereby improved the data holding ability of floating boom 5 greatly; In carrying out the data holding ability test process, adopt the memory manufacturing in the present embodiment to obtain satisfied effect, its yield is 99.3%.

At last; See also Fig. 2 F, on the end dielectric layer 4 that injects cobalt ions, forming metal connecting line is drain line 11, and external circuit can carry out reading of data through 11 pairs of said floating booms 5 of drain line; Owing to form metal connecting line technology for existing maturation process, be not described in detail in this.

More than show and described basic principle of the present invention, principal character and advantage of the present invention.The technical staff of the industry should understand; The present invention is not restricted to the described embodiments; That describes in the foregoing description and the specification just explains principle of the present invention; The present invention also has various changes and modifications under the prerequisite that does not break away from spirit and scope of the invention, and these variations and improvement all fall in the scope of the invention that requires protection.The present invention requires protection range to be defined by appending claims and equivalent thereof.

Claims

1. a memory manufacturing is characterized in that, comprises the steps:

The nitride of removal above said drain region altogether.

2. memory manufacturing as claimed in claim 1 is characterized in that, also comprises the steps:

Inject cobalt ions in the end dielectric layer on said drain region altogether;

The cobalt ions reaction of injecting is formed cobalt compounds;

3. memory manufacturing as claimed in claim 1 is characterized in that: said nitride is a silicon nitride.

4. memory manufacturing as claimed in claim 2 is characterized in that: said cobalt compounds is a cobalt disilicide.

5. memory manufacturing as claimed in claim 1 is characterized in that: said insulating barrier is the dielectric structure that comprises oxide-nitride thing-oxide or comprise the oxide-nitride thing.

6. memory manufacturing as claimed in claim 1 is characterized in that: said insulating barrier is composition, oxide or the nitride of oxide and nitride.

7. memory manufacturing as claimed in claim 1 is characterized in that: said floating boom and control gate are polysilicon.