CN101826462B - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- CN101826462B CN101826462B CN2009100468966A CN200910046896A CN101826462B CN 101826462 B CN101826462 B CN 101826462B CN 2009100468966 A CN2009100468966 A CN 2009100468966A CN 200910046896 A CN200910046896 A CN 200910046896A CN 101826462 B CN101826462 B CN 101826462B
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Abstract
The invention relates to a manufacturing method of a semiconductor device, comprising the following step of annealing after N-shaped ions are implanted to form an N-shaped light doping region, wherein the annealing comprises combined application of peak annealing and immersed-type annealing. The phenomenon of the residual of the implanted ions is improved through the combined application of the peak annealing and the immersed-type annealing.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly method, semi-conductor device manufacturing method.
Background technology
Along with the continuous development of semiconductor fabrication process, size of devices is also constantly dwindled.For example for metal-oxide-semiconductor field effect transistor, its grid size constantly dwindles, and correspondingly, channel length also constantly shortens and produces short-channel effect, makes that for example the threshold voltage of metal-oxide-semiconductor field effect transistor reduces.In order to improve device performance, the ultra shallow junction technology of existing generally employing suppresses short-channel effect, promptly through reducing the junction depth in said metal-oxide-semiconductor field effect transistor source/drain region, to reduce the electric capacity between source/drain region and the substrate, suppresses short-channel effect.
Prior art generally is after formation source/leakage light doping section injects, and carries out rapid thermal annealing.That is, after light dope injects in the substrate of grid both sides, carry out rapid thermal annealing with the said light doping section of crystalization again.A kind of method, semi-conductor device manufacturing method part process of prior art is exemplified below:
Shown in Fig. 1 a, on substrate 10, form gate oxide 20 and grid 21 successively.Form gate oxide 20 and the grid 21 general methods that adopt chemical vapour deposition (CVD).Gate oxide 20 generally adopts for example material such as silica.
Shown in Fig. 1 b, substrate 10 is carried out N type ion inject, in the substrate of gate oxide 20 and grid 21 both sides, form the more shallow N type extension area 30,31 of the degree of depth.For the 90nm of present employing and following technology, after forming N type extension area, also can carry out halo and inject (HaloImplantation).Halo is injected to the ion implantation technology of wide-angle, mainly is to prevent that the source leakage from communicating, and reduces the extension area junction depth and shortens channel length.
Shown in Fig. 1 c, form side wall 26 in gate oxide 20 and grid 21 both sides, and carry out N type ion once more and inject, to form N type light doping section 40,41.
Forming N type light doping section 40, after 41, said light doping section annealed.The general spike annealing (spike-annealing) that adopts.
Then, carry out again and the similar P type of above-mentioned steps light doping section technology and corresponding annealing process, and follow-up source, drain electrode form technology.
For example can also find more information relevant among U.S. Pat 7091097 B1 with foregoing.
Yet, in present fabrication of semiconductor device, find, after ion injects, there is more injection ion residues in the substrate, possibly produce junction leakage phenomenons such as (junction leakage), influence formed performance of semiconductor device.
Summary of the invention
The present invention solves is after ion in the prior art fabrication of semiconductor device injects, to have more injection ion residues in the substrate, and influence the problem of formed performance of semiconductor device.
For addressing the above problem, the present invention provides a kind of method, semi-conductor device manufacturing method, comprises that N type ion injects the annealing afterwards of formation N type light doping section, and wherein said annealing comprises spike annealing and immersion annealing (soak-annealing).
Compared with prior art, the above-mentioned semiconductor device manufacturing approach has the following advantages: the combination through spike annealing and immersion annealing is used, and makes the phenomenon of injecting ion residues be improved.
Description of drawings
Fig. 1 a to 1c is a kind of method, semi-conductor device manufacturing method part process sketch map of prior art;
Fig. 2 a is that N type ion injects a kind of execution mode flow chart that forms the annealing afterwards of N type light doping section in the method, semi-conductor device manufacturing method of the present invention;
Fig. 2 b is that N type ion injects the another kind of execution mode flow chart that forms the annealing afterwards of N type light doping section in the method, semi-conductor device manufacturing method of the present invention;
Fig. 3 is the various annealing example schematic in the method, semi-conductor device manufacturing method of the present invention;
Fig. 4 be according to an embodiment of the present to N type light doping section annealing and prior art to the annealing of N type light doping section after, the depth correlation table of the N type light doping section that measures;
Fig. 5 is after according to an embodiment of the present the annealing of N type light doping section, the annealing of P type light doping section and prior art being annealed to the annealing of N type light doping section, P type light doping section, the depth correlation table of the N type light doping section that measures;
Fig. 6 be another kind of embodiment according to the present invention to the annealing of N type light doping section and prior art to the annealing of N type light doping section after, the depth correlation table of the N type light doping section that measures;
Fig. 7 is after another kind of embodiment according to the present invention anneals to the annealing of N type light doping section, P type light doping section to the annealing of N type light doping section, the annealing of P type light doping section and prior art, the depth correlation table of the N type light doping section that measures.
Embodiment
Shown in Fig. 2 a, a kind of execution mode of method, semi-conductor device manufacturing method according to the present invention injects the annealing process after forming N type light doping section at N type ion; The execution in step s1 of elder generation; Carry out spike annealing, and follow execution in step s2, carry out immersion annealing.
Below instance through a concrete semiconductor device manufacturing above-mentioned execution mode method is further specified.
Continuation forms gate oxide 20 and grid 21 successively with reference to shown in Fig. 1 a on substrate 10.Form gate oxide 20 and the grid 21 general methods that adopt chemical vapour deposition (CVD).Gate oxide 20 generally adopts for example material such as silica.
Continuation is carried out N type ion to substrate 10 and is injected with reference to shown in Fig. 1 b, in the substrate of gate oxide 20 and grid 21 both sides, forms the more shallow N type extension area 30,31 of the degree of depth.After forming N type extension area, also can carry out halo and inject.
Shown in Fig. 1 c, form side wall 26 in gate oxide 20 and grid 21 both sides, and carry out N type ion once more and inject, to form N type light doping section 40,41.The N type ion of wherein said injection can be arsenic ion, and the energy of said arsenic ion can be 1KeV, and dosage can be 8 * 10
14Cm
-2
Form N type light doping section 40, after 41, said N type light doping section 40,41 carried out spike annealing earlier, then carrying out immersion annealing again.Said spike annealing and immersion annealing are all carried out in same boiler tube.
For example, with reference to shown in Figure 3, corresponding curve 100, the substrate 10 that will have N type light doping section 40,41 places boiler tube, is warming up to 1050 ℃ earlier and carries out spike annealing.Wherein said intensification comprises that two-part heats up, and for example is warming up to 500～650 ℃ earlier, continues to be warming up to 1050 ℃ again and carries out spike annealing.
After spike annealing, then carry out 800 ℃ immersion annealing, the time of said immersion annealing is 10 seconds.Its process comprises: gas cooled is carried out in any one or the combination that in boiler tube, feed in neon, the helium, makes that the temperature in the boiler tube drops to 800 ℃ from 1050 ℃.Continuing that subsequently substrate 10 is heated the temperature of keeping 800 ℃ anneals to carry out immersion.The time that the time of said immersion annealing is promptly kept 800 ℃ temperature, for example 10 seconds.
Again for example, continue with reference to shown in Figure 3, corresponding curve 200 is warming up to 1050 ℃ earlier to the substrate 10 with N type light doping section 40,41 and carries out spike annealing.Wherein said intensification comprises that two-part heats up, and for example is warming up to 500～650 ℃ earlier, continues to be warming up to 1050 ℃ again and carries out spike annealing.Then carry out 900 ℃ immersion annealing again, the time of said immersion annealing is 10 seconds.Said annealing process can be with reference to above-mentioned associated description.
The temperature and time of above-mentioned immersion annealing is merely for example, and the temperature of said immersion annealing can be 600～900 ℃, and the time can be 5～30 seconds.
Above-mentioned N type light doping section is carried out immersion annealing after, carry out the similar P type of technical process light doping section technology and corresponding annealing process again.
Wherein, the annealing after forming P type light doping section can be adopted the method for twice spike annealing.For example after forming P type light doping section, carry out 950 ℃ spike annealing earlier, carry out 1070 ℃ spike annealing again.
Above-mentioned P type light doping section is carried out annealing after, carry out follow-up source, drain electrode forms technology.
With reference to shown in Figure 4, after #1, #2, #3 are illustrated respectively in and form N type light doping section, adopt the sample wafer of two kinds of method for annealing and the method for annealing that adopts prior art of the invention described above embodiment.After annealing; Measurement result for said N type light doping section junction depth can be seen; N type light doping section is only adopted the technology of 1050 ℃ spike annealing with respect to prior art; What above-mentioned instance adopted carries out 1050 ℃ spike annealing earlier to N type light doping section, carries out the immersion annealing process of 800 ℃ or 900 ℃ again, and said N type light doping section junction depth remains unchanged basically.It is 16.6nm that prior art only adopts the N type light doping section junction depth behind 1050 ℃ the spike annealing; Carry out 1050 ℃ spike annealing earlier and above-mentioned instance adopts, the N type light doping section junction depth that carries out again after the immersion annealing of 800 ℃ or 900 ℃ is respectively 16.7nm and 17.2nm.
Shown in Figure 5 is that #1, #2, these three sample wafer of #3 are after above-mentioned N type light doping section annealing, again through the N type light doping section junction depth after the annealing of P type light doping section.
After twice annealing; Measurement result for said N type light doping section junction depth can be seen; With respect to prior art N type light doping section is only adopted 1050 ℃ spike annealing; P type light doping section is adopted the technology of twice spike annealing (950 ℃+1070 ℃), and what above-mentioned instance adopted carries out 1050 ℃ spike annealing earlier to N type light doping section, carries out the immersion annealing process of 800 ℃ or 900 ℃ again; Through after the said P type light doping section annealing, said N type light doping section junction depth remains unchanged basically subsequently.After prior art N type light doping section, the annealing of P type light doping section; Said N type light doping section junction depth is 21.8nm; And 1050 ℃ spike annealing is carried out in above-mentioned instance employing earlier to N type light doping section; Carry out the immersion annealing of 800 ℃ or 900 ℃ again, and after the annealing of said P type light doping section, said N type light doping section junction depth is respectively 21.8nm and 22.7nm.
Find that the injection ion residues of #1, #2 has obvious improvement with respect to the injection ion residues of #3 and detect the back in injection ion residues situation to #1, #2, #3.
Shown in Fig. 2 b, the another kind of execution mode of method, semi-conductor device manufacturing method according to the present invention injects the annealing process after forming N type light doping section at N type ion; The execution in step s10 of elder generation; Carry out immersion annealing, and follow execution in step s20, carry out spike annealing.
Below instance through a concrete semiconductor device manufacturing above-mentioned execution mode method is further specified.
Continuation forms gate oxide 20 and grid 21 successively with reference to shown in Fig. 1 a on substrate 10.Form gate oxide 20 and the grid 21 general methods that adopt chemical vapour deposition (CVD).Gate oxide 20 generally adopts for example material such as silica.
Continuation is carried out N type ion to substrate 10 and is injected with reference to shown in Fig. 1 b, in the substrate of gate oxide 20 and grid 21 both sides, forms the more shallow N type extension area 30,31 of the degree of depth.After forming N type extension area, also can carry out halo and inject.
Shown in Fig. 1 c, form side wall 26 in gate oxide 20 and grid 21 both sides, and carry out N type ion once more and inject, to form N type light doping section 40,41.The N type ion of wherein said injection can be arsenic ion, and the energy of said arsenic ion can be 1KeV, and dosage can be 8 * 10
14Cm
-2
Forming N type light doping section 40, after 41, said N type light doping section 40,41 being carried out immersion annealing earlier, then carry out spike annealing again.Said immersion annealing and spike annealing all carry out in same boiler tube.
For example, continue with reference to shown in Figure 3 corresponding curve 300; The substrate 10 that will have N type light doping section 40,41 places boiler tube; Be warming up to 900 ℃ earlier and carry out immersion annealing, the time of said immersion annealing is 10 seconds, then continues to be warming up to 1050 ℃ again and carries out spike annealing.
Again for example, the substrate 10 with N type light doping section 40,41 is warming up to 800 ℃ earlier carries out immersion annealing, the time of said immersion annealing is 10 seconds, then continues to be warming up to 1050 ℃ again and carries out spike annealing.
The temperature and time of above-mentioned immersion annealing is merely for example, and the temperature of said immersion annealing can be 600～900 ℃, and the time can be 5～30 seconds.
Above-mentioned N type light doping section is carried out spike annealing after, carry out the similar P type of technology light doping section technology and corresponding annealing process again.
Wherein, the annealing after forming P type light doping section can be adopted the method for twice spike annealing.For example after forming P type light doping section, carry out 950 ℃ spike annealing earlier, carry out 1070 ℃ spike annealing again.
Above-mentioned P type light doping section is carried out spike annealing after, carry out follow-up source, drain electrode forms technology.
With reference to shown in Figure 6, after #4, #5 are illustrated respectively in and form N type light doping section, adopt the sample wafer of method for annealing with the method for annealing that adopts prior art of the invention described above embodiment.After annealing; Measurement result for said N type light doping section junction depth can be seen; N type light doping section is only adopted the technology of 1050 ℃ spike annealing with respect to prior art; What above-mentioned instance adopted carries out 900 ℃ immersion annealing earlier to N type light doping section, carries out 1050 ℃ spike annealing technology again, and said N type light doping section junction depth remains unchanged basically.It is 16.6nm that prior art only adopts the N type light doping section junction depth behind 1050 ℃ the spike annealing, carries out 900 ℃ immersion annealing earlier and above-mentioned instance adopts, and the N type light doping section junction depth that carries out again behind 1050 ℃ the spike annealing is 16.7nm.
Shown in Figure 7 is that #4, these two sample wafer of #5 are after above-mentioned N type light doping section annealing, again through the N type light doping section junction depth after the annealing of P type light doping section.
After twice annealing; Measurement result for said N type light doping section junction depth can be seen, with respect to prior art N type light doping section is only adopted 1050 ℃ spike annealing, P type light doping section is adopted the technology of twice spike annealing (950 ℃+1070 ℃); What above-mentioned instance adopted carries out 900 ℃ immersion annealing earlier to N type light doping section; Carry out 1050 ℃ spike annealing technology again, through after the said P type light doping section annealing, said N type light doping section junction depth remains unchanged basically subsequently.After prior art N type light doping section, the annealing of P type light doping section; Said N type light doping section junction depth is 21.8nm; And above-mentioned instance adopts N type light doping section is carried out 900 ℃ immersion annealing earlier; Carry out 1050 ℃ spike annealing again, and after the annealing of said P type light doping section, said N type light doping section junction depth is 21.6nm.
Find that the injection ion residues of #4 has obvious improvement with respect to the injection ion residues of #5 and detect the back in injection ion residues situation to #4, #5.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (7)
1. a method, semi-conductor device manufacturing method comprises that N type ion injects the annealing afterwards of formation N type light doping section, it is characterized in that said annealing comprises spike annealing and the immersion annealing of carrying out continuously.
2. method, semi-conductor device manufacturing method as claimed in claim 1 is characterized in that, said annealing comprises carries out spike annealing earlier, and then carries out immersion annealing.
3. method, semi-conductor device manufacturing method as claimed in claim 2 is characterized in that, the temperature of said spike annealing is 1050 ℃.
4. method, semi-conductor device manufacturing method as claimed in claim 2 is characterized in that, the temperature of said immersion annealing is 600～900 ℃, and the time is 5～30 seconds.
5. method, semi-conductor device manufacturing method as claimed in claim 1 is characterized in that, said annealing comprises carries out immersion annealing earlier, and then carries out spike annealing.
6. method, semi-conductor device manufacturing method as claimed in claim 5 is characterized in that, the temperature of said immersion annealing is 600～900 ℃, and the time is 5～30 seconds.
7. method, semi-conductor device manufacturing method as claimed in claim 5 is characterized in that, the temperature of said spike annealing is 1050 ℃.
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| US7091097B1 (en) * | 2004-09-03 | 2006-08-15 | Advanced Micro Devices, Inc. | End-of-range defect minimization in semiconductor device |
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| US7091097B1 (en) * | 2004-09-03 | 2006-08-15 | Advanced Micro Devices, Inc. | End-of-range defect minimization in semiconductor device |
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