CN101882583A - 沟栅场效应晶体管及其形成方法 - Google Patents

沟栅场效应晶体管及其形成方法 Download PDF

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CN101882583A
CN101882583A CN2010102182330A CN201010218233A CN101882583A CN 101882583 A CN101882583 A CN 101882583A CN 2010102182330 A CN2010102182330 A CN 2010102182330A CN 201010218233 A CN201010218233 A CN 201010218233A CN 101882583 A CN101882583 A CN 101882583A
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grid
dielectric
gate trench
gate
forms
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克里斯多佛·博古斯洛·科库
史蒂文·P·萨普
保尔·托鲁普
帝恩·E·普罗布斯特
罗伯特·赫里克
贝姬·洛斯伊
哈姆扎·耶尔马兹
克里斯托弗·劳伦斯·雷克塞尔
丹尼尔·卡拉菲特
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

本发明公开了一种沟栅场效应晶体管及其形成方法。一种单片集成场效应晶体管和肖特基二极管，包括延伸到半导体区内的栅极沟槽。具有基本三角形的源极区位于栅极沟槽的每一侧的侧面。接触开口延伸到相邻栅极沟槽之间的半导体区中。导体层填充接触开口以：(a)沿每一源极区的倾斜侧壁的至少一部分电接触源极区，以及(b)沿接触开口的底部电接触半导体区，其中，导体层与半导体区形成肖特基接触。

Description

沟栅场效应晶体管及其形成方法
本申请是申请日为2006年4月4日、发明名称为“沟栅场效应晶体管及其形成方法”的第200680018774.0号中国专利申请的分案申请。
相关申请的参考
本申请要求于2005年4月6日提交的美国临时申请第60/669，063号的优先权，将其全部内容结合于此作为参考。下列专利申请的全部内容结合于此作为参考：于2004年7月15日提交的第60/588，845号美国临时申请；于2004年12月29日提交的第11/026，276号美国申请；以及于2001年4月27日提交的第09/844,347号美国申请(公开号US2002/0008284)。
技术领域
本发明总体涉及功率半导体技术，并且尤其是涉及积累型和增强型沟栅(trenched-gate)场效应晶体管(FET)及其制造方法。
背景技术
功率电子应用中的关键部件是固态开关。从汽车应用中的点火控制到电池驱动的电子消费品、再到工业应用中的功率转换器，都需要一种最佳地适合具体应用要求的电源开关。固态开关，例如包括功率金属氧化物半导体场效应晶体管(功率MOSFET)、绝缘栅双极晶体管(IGBT)和各种类型的半导体闸流管，已经持续发展以满足这种要求。在功率MOSFET的情况下，已经开发出很多技术，其中包括例如，具有横向沟道(channel)的双扩散结构(DMOS)(例如，Blanchard等人的美国专利第4,682,405号)、沟栅结构(例如，Mo等人的美国专利第6,429,481号)以及用于晶体管漂移区的电荷平衡的各种技术(例如，Temple的美国专利第4,941,026号；Chen的美国专利第5,216,275号；以及Neilson的美国专利第6,081,009号)，以满足不同的并且经常是有竞争性的性能要求。
电源开关的一些规定的性能特性是它的导通电阻(on-resistance)、击穿电压(breakdown voltage)和开关速度(转换速度，switching speed)。根据具体应用的需要，不同的重点放在各性能指标(性能标准)上。例如，对于大于约300-400伏特的电源应用来说，与功率MOSFET相比，IGBT显示出了固有的较低导通电阻，但是由于其缓慢的关闭特性(turn off characteristic)它的开关速度较低。因此，对于需要低导通电阻的具有低开关频率的大于400伏特的应用来说，IGBT是优选的开关，而功率MOSFET经常是对于较高频率应用的精选器件。如果给定应用的频率要求规定了所使用的开关类型，那么电压要求就决定了具体开关的结构组成。例如，在功率MOSFET的情况下，由于漏极-源极导通电阻RDSon和击穿电压之间的比例关系，在保持低RDSon的同时提高晶体管的电压特性是具有挑战性的。已经开发出了晶体管漂移区的各种电荷平衡结构，以不同程度成功地战胜了这种挑战。
两种不同的场效应晶体管是积累型FET和增强型FET。在传统的积累型FET中，由于没有形成反型沟道(反向沟道，inversionchannel)，因而沟道电阻消除了，从而改善了晶体管功率处理能力及其效率。而且，由于没有pn本体二极管(体二极管，body diode)，减少了同步整流电路中由pn二极管引起的损失。传统积累型晶体管的缺点在于漂移区需要是低掺杂(轻掺杂，lightly doped)的以支持足够高的反偏压。然而，低掺杂的漂移区导致了较高的导通电阻和较低的效率。类似地，在增强型FET中，提高晶体管的击穿电压经常是以较高导通电阻为代价的，反之亦然。
器件性能参数也受制造工艺的影响。已经通过开发各种改进的处理技术，来进行各种尝试，以解决部分这些挑战。无论是在超轻便的消费电子器件(consumer electronic device)中，还是在通信系统的路由器和集线器中，电源开关的各种应用随着电子工业的发展而增长。电源开关因此属于具有高开发潜力的半导体器件。
发明内容
本发明针对功率器件以及它们的制造方法提供了各种具体实施方式。概括地，根据本发明的一个方面，肖特基(Schottky)二极管优选地与积累型FET或增强型FET集成于单个单元(singlecell)内。根据本发明的其它方面，提供了制造具有自对准特征以及其它优点和特征的各种功率晶体管结构的方法。
根据本发明的一种具体实施方式，单片集成(monolithicallyintegrated)场效应晶体管和肖特基二极管包括延伸到半导体区内的栅极沟槽。具有基本三角形形状的源极区位于栅极沟槽的每一侧的侧面。接触开口延伸到相邻栅极沟槽之间的半导体区域中。导体层填充接触开口以：(a)沿每一源极区倾斜侧壁的至少一部分电接触源极区，以及(b)沿接触开口的底部电接触半导体区，其中，导体层与半导体区形成肖特基接触。
根据本发明的另一具体实施方式，单片集成沟槽(monolithicallyintegrated trench)FET和肖特基二极管包括延伸到外延层内且终止于此的栅极沟槽，所述外延层在基板上延伸。每个栅极沟槽内具有凹入式栅极(recessed gate)，在凹入式栅极顶上有电介质材料。外延层的传导类型(导电类型，conductivity type)与基板(衬底，substrate)相同，但是掺杂浓度比基板低。源极区位于栅极沟槽的每一侧的侧面，且每一源极区的顶面低于电介质材料的顶面。接触开口延伸到相邻栅极沟槽之间的外延层内。导体层填充接触开口以电接触源极区和外延层，并且与半导体区形成肖特基接触。外延层和源极区包括碳化硅、氮化镓、以及砷化镓中的一种。
根据本发明的又一具体实施方式，单片集成沟槽FET和肖特基二极管包括延伸到第一传导型半导体区中的栅极沟槽，每一栅极沟槽内具有凹入式栅极，并在凹入式栅极的顶上有电介质材料。第一传导型源极区位于栅极沟槽的每一侧的侧面。每一源极区具有上表面，其相对于电介质材料的上表面是凹入的，所述电介质材料在相应的凹入式栅极的顶上。第二传导型的本体区(body region)沿每一栅极沟槽的侧壁在相应的源极区与半导体区之间延伸。接触开口延伸到相邻栅极沟槽之间的半导体区内。导体层填充接触开口并电接触源极区、本体区和半导体区，并且导体层与半导体区形成肖特基接触。
根据本发明的另一具体实施方式，单片集成沟槽FET和肖特基二极管包括延伸到半导体区内的栅极沟槽，每一栅极沟槽内具有栅极，且在栅极的顶上有电介质材料。半导体源极间隔体(sourcespacer)位于栅极沟槽的每一侧的侧面，以使位于每两个相邻栅极沟槽之间的每一对相邻的半导体源极间隔体之间形成接触开口。导体层填充接触开口并且接触半导体源极间隔体和半导体区，而且与半导体区形成肖特基接触。
根据本发明的另一具体实施方式，单片集成沟槽FET和肖特基二极管包括延伸到第一传导型半导体区内的栅极沟槽。第一传导型的源极区位于栅极沟槽的每一侧的侧面。屏蔽电极沿每一栅极沟槽的底部放置，并且通过屏蔽电介质层与半导体区绝缘。栅极位于每一沟槽中的屏蔽电极上方，并且栅极和屏蔽电极之间具有电介质层。电介质帽(电介质盖，dielectric cap)位于栅极上方。导体层接触源极区和半导体区，使得导体层与半导体区形成肖特基接触。
以下结合附图，对本发明的这些和其它方面进行更详细地描述。
附图说明
图1是根据本发明示例性具体实施方式的具有集成的肖特基的沟栅积累(accumulation)FET的简化横截面视图；
图2A-2I是根据本发明示例性具体实施方式的简化横截面视图，其示出了用于形成图1中的集成的FET肖特基二极管结构的各工艺步骤；
图3A-3E是根据本发明另一示例性具体实施方式的简化横截面视图，其示出了图2G-2I所示工艺步骤中的后一部分的步骤的替代工艺步骤；
图3EE是替代具体实施方式的简化横截面视图，其中，图3A-3E工艺步骤中的电介质间隔体在形成顶侧导体层之前被移除了；
图4是图3EE中结构的变型的简化横截面图，其中，屏蔽电极在栅极的下方形成；
图5是图3E中结构的变型的简化横截面图，其中，接触开口延伸至与栅极沟槽大约相同的深度；
图6是图5中积累FET-肖特基二极管结构的增强型变型的简化横截面视图；
图7A示出了模拟(仿真)结果，其中，示出了两个SiC基积累FET的电场线，一个比另一个具有较深的肖特基接触凹入(接触凹陷，contact recess)；
图7B是关于较深和较浅肖特基接触凹入的两种情况的漏极电流与漏极电压的模拟曲线图；
图8是根据本发明示例性具体实施方式的具有多晶硅源极间隔体的沟栅积累FET的简化横截面视图；
图9A-9H、图9I-1、以及图9J-1是根据本发明示例性具体实施方式的简化横截面视图，示出了用于形成图8中的FET-肖特基二极管结构的各工艺步骤；
图9I-2和图9J-2是简化横截面视图，示出了对应于图9I-1和图9J-1的步骤的替代工艺步骤，其产生了图8中FET-肖特基二极管结构的变型；
图10和图11是简化横截面视图，分别示出了图9J-1和图9J-2中FET-肖特基结构的变型，其中，屏蔽电极在栅极的下面形成；
图12是根据本发明另一具体实施方式的具有屏蔽电极位于栅极之下的沟栅积累FET-肖特基结构的简化横截面视图；
图13是简化横截面视图，其示出了图11具体实施方式的变型，其中，改变了相邻沟槽之间的肖特基区以形成MPS结构；
图14示出了图1中FET-肖特基结构的漏极电流-漏极电压特性图(左图)和栅极电压-栅极电荷(右图)图；
图15A-15H是根据本发明另一具体实施方式的简化横截面视图，示出了用于形成具有自对准特性的沟栅FET的各个工艺步骤；
图16示出了根据本发明另一具体实施方式的具有非平面顶面(在顶部金属形成之前)的p-沟道沟栅FET的等比例视图；
图17A、图17B-1和图17B-2是用于形成图16中FET的两个简化工艺步骤的横截面视图；
图18是根据本发明具体实施方式的横截面视图，示出了用于形成自对准源极和重本体区(重体区，heavy body region)的技术；
图18A-18I是根据本发明示例性具体实施方式的用于形成图18中所示的沟栅FET的不同工艺步骤的横截面视图；
图19A-19H是根据本发明另一示例性具体实施方式的工艺步骤中不同工艺步骤的横截面视图，其中，形成了非表面多晶硅，并且与图18A-18I的工艺相比，掩模的数量减少了；
图20A-20G是根据本发明又一示例性具体实施方式的横截面视图，其示出了另一工艺步骤，其中，与图18A-18I中的相比，掩模的数量减少了；
图21A-21H是根据本发明示例性具体实施方式的横截面视图，其示出了用于形成沟栅FET(该沟栅FET类似于由图18A-18I得到的，除了肖特基二极管与FET集成之外)的工艺步骤；
图22A-22F是根据本发明另一具体实施方式的横截面视图，其示出了用于以减少的掩模数量来形成沟栅FET的又一工艺步骤；
图23A-23I是根据本发明又一具体实施方式的用于形成具有自对准特征的沟栅FET的不同工艺步骤的横截面视图；以及
图24A-24I示出了根据本发明又一具体实施方式的用于形成具有自对准特征的沟栅FET的不同工艺步骤的横截面视图。
具体实施方式
电源开关可以由功率MOSFET、IGBT、各类型的半导体闸流管等中任一种来实现。为了说明的目的，在此所呈现的许多新技术以功率MOSFET的情形进行描述。然而应该理解，在此描述的本发明的各具体实施方式并不限于功率MOSFET且可以应用于许多其它类型的电源开关技术，例如包括IGBT和其它类型的双极性开关。而且，为了说明的目的，所示出的本发明的具体实施方式包括特定的p型区和n型区。本领域技术人员应当理解，此处的教导可等价应用于各区传导性相反的器件。
图1示出了根据本发明示例性具体实施方式的优选与肖特基二极管集成于单个单元的沟栅积累场效应晶体管(FET)的简化横截面视图。低掺杂的n型外延层104在高度掺杂的n型基板102上延伸且与之接触。栅极沟槽106延伸到外延层104中且终止于此。每一栅极沟槽106沿其侧壁和底部衬(排列，line)有电介质层108，且包括凹入式栅极(recessed gate)110以及在凹入式栅极110顶上的绝缘材料112。n型传导性的三角形源极区114位于沟槽106每一侧的侧面。源极区114沿垂直方向交叠多晶硅栅极110。在作为高电压FET的这种应用中，该交叠不是必须的，其中，缺少交叠会对晶体管导通电阻Rdson产生极小的影响。缺少栅极-源极交叠大大影响低电压晶体管中的Rdson，因而在这样的晶体管中它的出现是有利的。
外延层104的凹入部分和源极区114一起形成具有圆形底部的V形接触开口118。肖特基势垒金属(barrier metal)120在结构上延伸且填充接触开口118以沿源极区114的倾斜侧壁与源极区114接触，且在其凹入部分与外延层104相接触。由于源极区114是高掺杂的并且外延层104是低掺杂的，从而顶侧导体层120与源极区114形成欧姆接触且与外延层104形成肖特基接触。在一个具体实施方式中，肖特基势垒金属120包括钛。背侧导体层122，例如包括铝(或钛)，接触基板102。
与增强型晶体管不同，图1结构100中的积累型晶体管不包括其中形成有传导沟道(conduction channel)的本体区或阻断阱(闭塞阱，blocking well)(在本实例中是p型)。替代的是，当积累层在外延层104中沿沟槽侧壁形成时，形成导电通道。根据沟道区的掺杂浓度和栅极110的掺杂类型，结构100中的晶体管正常地打开(导通)或关闭(截止)。当沟道区完全耗尽且稍微反向时，晶体管关闭。同样，由于没形成反型沟道(反向沟道，inversion channel)，因此消除了沟道电阻，从而提高了晶体管功率处理能力及其效率。而且，由于没有pn体二极管，所以消除了由pn二极管在同步整流电路中引起的损失。
在图1的具体实施方式中，结构100中的FET是垂直沟栅积累MOSFET，其具有形成源极导体的顶侧导体层120和形成漏极导体的底侧导体层120。在另一具体实施方式中，基板102是p型的，从而形成积累IGBT。
图2A-2I是根据本发明示例性具体实施方式的简化横截面视图，示出了用于形成图1中的集成的FET-肖特基二极管结构100的各工艺步骤。在图2A中，使用传统方法，下外延层204和上外延层205在n型基板202上顺序形成。可替换地，可以使用包括外延层204、205的初始晶片材料(wafer material)。上n型外延层205比下n型外延层204具有更高的掺杂浓度。在图2B中，利用已知技术，使用掩模(未示出)来限定和蚀刻硅以形成沟槽206，该沟槽206穿过上外延层205且终止于下外延层204。在形成沟槽的过程中可以使用传统的干或湿蚀刻。在图2C中，在结构上生长或沉积例如包括氧化物的电介质层208，从而沟槽206的侧壁和底部衬有电介质层208。
在图2D中，随后使用传统技术沉积多晶硅层209以填充沟槽206。多晶硅层209可以原位掺杂来获得所需的栅极掺杂类型和浓度。在图2E中，使用传统的技术，深刻蚀(回蚀刻，etch back)多晶硅层209且凹入沟槽206中以形成栅极210。凹入式栅极210(recessed gate)沿垂直方向交叠上外延层205。如上所述，根据应用目标和设计目的，凹入式栅极210无需交叠上外延层205(即，工艺步骤和最终结构不必受到该交叠的限制)。在其它具体实施方式中，栅极210包括多晶碳化硅(多晶硅碳化物，polysilicon carbide)或金属。
在图2F中，在结构上形成例如由氧化物形成的电介质层211并且随后使用传统的技术进行平坦化。在图2G中，至少在器件的有源区(active area)上实施平坦化的电介质层211(在有源区(activeregion))的毯式蚀刻(毡式蚀刻，blanket etch)，以暴露上外延层205的表面区域，同时电介质层211的部分212保留在凹入式栅极210中。在图2H中，利用传统的技术，至少在有源区中实施毯式倾斜(blanket angled)硅蚀刻(例如，在有源区的干蚀刻)，以形成具有圆底的V形接触开口218。接触开口218延伸完全通过上外延层205，从而在每两个相邻的沟槽之间形成两个源极区214。接触开口218伸入且终止于下外延层204的上半部分。
在图2I中，顶侧导体层220使用传统技术形成。顶侧导体层220包括肖特基势垒金属。如图所示，顶侧导体层220填充接触开口218，以便沿着源极区214的倾斜侧壁与源极区214接触，并且沿着接触开口218的底部与下外延层204接触。由于源极区214是高掺杂的且下外延层204是低掺杂的，因此顶侧导体层220与源极区214形成欧姆接触，且与下外延层204形成肖特基接触。如可以看到的，源极区214和肖特基接触对于(关于)沟槽206是自对准的。
图3A-3E是根据本发明另一示例性具体实施方式的简化横截面图，示出了由图2G-2I所示的工艺步骤的后一部分工艺步骤的替代工艺步骤。因此，在本具体实施方式中，实施由图2A-2G所示的相同的工艺步骤，并转到由图3B所示的步骤(图3A所示的步骤与图2G所示的步骤相同)。在图3B中，上外延层305被深蚀刻，以足够地暴露电介质材料312的上侧壁，用于容纳随后形成的电介质间隔体316。在一种具体实施方式中，第二外延层305被深蚀刻0.05-0.5μm范围的量。在图3C中，使用传统技术，间隔体316邻近于已暴露的电介质材料312的上侧壁而形成。间隔体316是用不同于电介质材料312的电介质材料制成的。例如，如果电介质材料312是由氧化物制成的，则间隔体316可以由氮化物制成。
在图3D中，上外延层305的已暴露表面区凹入并完全通过外延层305，从而形成伸入下外延层304的接触开口318。通过凹入并完全通过上外延层305，仅上外延层305的直接位于间隔体316之下的部分314保留了。部分314形成晶体管的源极区。如可以看到的，接触开口318以及如此形成的源极区314对于沟槽306是自对准的。在图3E中，顶侧导体层320和底侧导体层322使用传统技术形成。导体层320包括肖特基势垒金属。如图所示，顶侧导体层320填充接触开口318，以便沿源极区314的侧壁与源极区314接触，并且与下外延层304的凹入部分接触。由于源极区314是高掺杂的而下外延层304是低掺杂的，因此顶侧导体层320与源极区314形成欧姆接触，并且与下外延层304形成肖特基接触。
在图3EE所示的替代具体实施方式中，在形成顶侧导体层之前，电介质间隔体316被移除了，从而暴露源极区314的顶面。顶侧导体层321由此沿源极区314的顶面和侧壁进行接触。从而减小了源极接触电阻。在上述各具体实施方式的可替换变型中，使用了已知技术以在形成栅极之前沿各沟槽的底部形成厚底电介质(thickbottom dielectric)。厚底部电介质降低了米勒电容(millercapacitance)。
从此处所述的各具体实施方式中可以看出，肖特基二极管优选地与FET集成于单个单元，在这样的单元的阵列中多次重复此操作。同样，肖特基接触和源极区对于沟槽是自对准的。另外，肖特基接触导致了低导通电阻Rdson，从而导致了低导通损失，并且还改善了晶体管的反向恢复特性。在不需要密集单元间距的情况下，还获得了良好的阻断能力(阻塞能力，blocking capability)。
在图2A-2I和图3A-3E所示的示例性工艺步骤中，没有使用扩散或注入(植入，implantation)。虽然可以用传统的晶体硅材料来进行这些工艺步骤，但是它们尤其适合于使用另一类型的材料，诸如碳化硅(SiC)、氮化镓(GaN)、以及砷化镓(GaAs)，其中，扩散、注入和掺杂剂活化工艺是很难完成和控制的。在这样的具体实施方式中，基板、下外延层和上外延层、以及晶体管的其它区可以包含SiC、GaN、以及GaAs中的一种。另外，在传统的碳化硅基增强型FET中，反型沟道对导通电阻的贡献尤其大。相反，对于图2I和图3E中的积累晶体管的碳化硅具体实施方式中的积累沟道的导通电阻贡献相当小。
图4示出了本发明另一具体实施方式的横截面视图。在图4中，屏蔽电极424在栅极410之下形成。屏蔽电极424通过屏蔽电介质425与下外延层404绝缘，且通过电极间电介质(iner-electrodedielectric)427与交叠的栅极410绝缘。屏蔽电极424有助于使米勒电容减小至可以忽略的量，从而剧烈地减小晶体管的开关损耗。尽管没有在图4中示出，但屏蔽电极424还电连接至源极区414，或者连接至地电位，或者根据设计和性能需求规定而电连接至其它电位。如果需要的话，可以在各栅极410之下形成偏压于相同或不同电位的一个以上的屏蔽电极。用于形成这样的屏蔽电极的一种或多种方法披露在上面所提及的普通转让(commonly assigned)申请第11/026,276中。而且，在申请第11/026,276号中所披露的其它电荷平衡结构也可以与在此所披露的各具体实施方式相结合，以进一步改善器件的性能特性。
某些传统的碳化硅基沟栅晶体管的缺点是栅极氧化物击穿电压低。根据本发明，通过将肖特基接触凹入更深地延伸至，例如，大于栅极沟槽深度一半的深度来解决该问题。图5示出了示例性具体实施方式，其中，肖特基接触凹入延伸至与栅极沟槽506近似相同的深度。深肖特基接触用来将栅极氧化物508与高电场屏蔽，从而改善栅极氧化物的击穿。这可以从图7A中看出，该图示出了两个SiC基积累FET的模拟结果，其中之一具有较深的肖特基接触凹入。沿带有较浅的肖特基接触凹入的晶体管(右图)的沟槽的底部出现的电场线在带有较深的肖特基接触凹入情况的晶体管(左图)中消除了。右图中栅极沟槽之下的电场线反应(反射，reflect)了从底部到顶部增加的电场。即，最低的电场线对应于最高的电场而最高的电场线对应于最低的电场。
深肖特基接触凹入的另一优点是：在阻断状态下的晶体管泄漏减少了。这在图7B的模拟结果中更清楚地示出，其中针对较深的肖特基接触凹入和较浅的肖特基接触凹入，绘出了漏极电流对漏极电压的曲线。正如可以看到的，当漏极电压从0V增加到200V时，在较浅的肖特基接触凹入的情况下，漏极电流连续上升，而对于较深的肖特基接触凹入来说，漏极电流保持平稳。因此，通过将肖特基接触深深地凹入到外延层504中，晶体管泄漏获得了实质性减小并且获得了较高的栅极氧化物击穿。
深凹入的肖特基接触结构(例如，图5中的)尤其适合于碳化硅基晶体管，这是因为栅极沟槽在外延层中延伸的深度无需像硅基晶体管的一样。这允许较浅的肖特基接触凹入(其较易于限定和蚀刻)。然而，对于使用其它类型材料(如SiC、GaN、以及GaAs)的类似结构，可以获得栅极氧化物击穿和晶体管泄漏方面的类似改善。
图6示出了图5结构中积累FET的增强型FET变型。在图6中，p型本体区613沿每一沟槽侧壁在相应源极区614的正下方延伸。如图所示，深接触开口618在本体区613的底面之下延伸，以使在顶侧导体层620与N-外延层604之间形成肖特基接触。与传统的MOSFET一样，当图6中的MOSFET在导通状态时，电流流过沿本体区613的每一沟槽侧壁延伸的沟道。在图6具体实施方式的变型中，移除了间隔体616，从而顶侧导体层620沿其顶面与源极区614相接触。
图8示出了根据本发明另一示例性具体实施方式的带有间隔体源极区的积累型FET的横截面视图，该间隔体源极区优选地与肖特基二极管集成为单个单元。n型外延层1104在n型基板1102上延伸并与之接触。栅极沟槽1106伸入外延层1104且终止于此。每一栅极沟槽1106沿其侧壁和底面衬有电介质层1108，且包括栅极1110以及在栅极1110顶部上的绝缘材料1112。n型材料(例如n型多晶硅)的间隔体源极区1114在外延层1104之上且位于沟槽1106的每一侧的侧面。
间隔体源极区1114形成接触开口1118，穿过该开口，顶侧导体层1120同时电接触外延层1104和源极区1114。顶侧导体层1120包括肖特基势垒金属。由于外延层1104低掺杂，因此顶侧导体层1120与外延层1104形成肖特基接触。
如前述具体实施方式中的一样，结构1100中的积累型晶体管不包括其中形成有传导沟道(conduction channel)的本体区或阻断阱(在此实例中为p型)。替代地，当积累层沿沟槽侧壁形成在外延层1104中时，形成了导电沟道。结构1100中的FET的正常打开(导通)或关闭(截止)取决于沟道区的掺杂浓度和栅极1110的掺杂类型。当沟道区完全耗尽且稍微反相时，其关闭。同样，由于没有形成反型沟道，因此沟道电阻消除了，从而提高了晶体管的功率处理能力及其效率。另外，由于不是pn本体二极管，因此由pn二极管在同步整流电路中引起的损耗被消除了。
在图8的具体实施方式中，结构1100中的FET是垂直的沟-栅积累MOSFET，其中，顶侧导体层1120形成源极导体并且底侧导体层(未示出)形成漏极导体。在另一具体实施方式中，基板1102可以是p型以形成积累IGBT。
图9A至图9H、图9I-1以及图9J-1示出了根据本发明具体实施方式的不同工艺步骤的横截面视图，该工艺步骤用于形成图8中集成的FET/肖特基二极管结构1100。在图9A中，n型外延层1204在n型基板1202上使用传统技术形成。可替换地，可以使用包括外延层1204的初始晶片。在图9B中，使用传统技术，掩模(未示出)用于限定和蚀刻硅以形成沟槽。在形成沟槽的过程中，可以使用传统的干蚀刻或湿蚀刻。沟槽1206伸入外延层1204且终止于此。在图9C中，在结构上生长或沉积电介质层1208(例如包含氧化物)，以使沟槽1206的侧壁和底部衬有电介质层1208。
在图9D中，使用传统技术沉积多晶硅层1209以填充沟槽1206。多晶硅层1209可以原位掺杂以获得期望的栅极掺杂型和浓度。在图9E中，使用传统技术深蚀刻多晶硅层1209并且在沟槽1206内凹入以形成凹入式栅极1210。
在图9F中，电介质层1211(例如包含氧化物)在结构上形成并且随后使用传统技术平坦化。在图9G中，在平坦化的电介质层1211(至少在有源区)上实施毯式蚀刻，以暴露外延层1204的表面区，同时电介质层1211的部分1212在栅极1210上保留下来。在图9H中，外延层1204被深蚀刻，足够地露出电介质材料1212的侧壁以容纳随后形成的源极间隔体1214。在图9I-1中，沉积了导电层(例如多晶硅)且随后使其被深蚀刻以邻接电介质材料1212的露出侧壁形成高掺杂源极间隔体1214。在多晶硅用于形成源极间隔体1214的情况下，多晶硅可以原位掺杂以获得高掺杂源极间隔体。在图9J-1中，顶侧导体层1220用传统技术形成。导体层1220包括肖特基势垒金属。在一种具体实施方式中，导体层1220包括钛。如图所示，源极间隔体1214形成接触开口1218，通过该开口，顶侧导体层1220接触外延层1204。导体层1220也接触源极间隔体1214。由于源极间隔体1214是高掺杂的且外延层1204是低掺杂的，因此顶侧导体层1220与源极间隔体1214形成欧姆接触且与外延层1204形成肖特基接触。
图9I-2和图9J-2是横截面视图，示出了图9I-1和图9J-1所示步骤的替代工艺步骤，其产生了图8中结构的变型。与图9I-1的步骤相反(其中多晶硅蚀刻在外延层1204的表面露出时被停止)，在图9I-2所示的步骤中，多晶硅蚀刻连续以凹入源极间隔体之间的露出的外延层区。如可以看到的，由于该额外的蚀刻，图9I-2中的源极间隔体1215小于图9I-1中的源极间隔体1214。在图9J-2中，顶侧导体层1221在结构之上用传统技术形成。顶侧导体层1221与源极间隔体1215形成欧姆接触，并且与外延层1204在区1219中形成肖特基接触。
可以看出，肖特基接触和源极间隔体关于沟槽1406是自对准的。另外，肖特基接触产生较低的导通电阻Rdson，从而是较低的导通状态损失，并且还改善了晶体管的反向恢复特性。并且，在无需紧凑单元间距的情况下获得了良好的阻断能力。而且，如结合图7曲线图所描述的一样，图9I-2、图9J-2具体实施方式的凹入肖特基接触的进一步优点是：阻断状态(阻塞状态，blocking state)的晶体管泄漏减小了。而且，多晶硅源极间隔体占用的面积小于传统扩散源极区。该优点产生了更大的肖特基接触面积。
图10示出了图8具体实施方式的变型的横截面视图，其中屏蔽电极1324在栅极1310之下形成。屏蔽电极1324有助于将米勒电容减小至可以忽略的量，从而剧烈地减小晶体管的开关损耗。可以使屏蔽电极1324电偏压于与源极间隔体相同的电位，或电偏压于地电位、或者电偏压于按设计和性能要求所规定的其它电位。如果需要的话，偏压于相同或不同电位的一个以上屏蔽电极可以在各栅极1310之下形成。用于形成这样的屏蔽电极的一种或多种方法披露在上面所引用的普通转让申请第11/026,276号中。
使用凹入肖特基接触中的以及使用屏蔽电极中的优点可以通过在单个结构组合它们来实现，如图11和图12的两实例所示的那样。图11示出了在带有多晶硅源极间隔体1415的积累型FET中使用凹入肖特基接触和屏蔽电极。图12示出了在带有源极区1517的积累型FET中使用凹入肖特基和屏蔽电极，其中，该源极区是使用传统的扩散方法形成的。图13示出了图11具体实施方式的变型，其中，改变肖特基区使其合并p型区1623。P型区1623可通过在形成顶侧导体层1620之前在肖特基区中注入p型掺杂物来形成。这样，熟知的合并P-i-N肖特基(Merged P-i-N Schottky)(MPS)结构在相邻沟槽之间的区域中形成了。事实上，阻挡结引入到积累晶体管(accumulation transistor)中。如本领域所公知的，MPS结构在阻断状态时减小晶体管的泄漏。
图14示出了使用图1中的结构的模拟结果。使用了MEDICI器件模拟器。图14包括左图(其中绘出了漏极电流对漏极电压的曲线)和右图(其中绘出了栅极电压对栅极电荷的曲线)。如左图所示，获得了1×10-14A/μm的低泄漏电流和高于35V的BVDSS，以及如右图所示，屏蔽电极有助于消除米勒电容。
在图9A-9H、图9I-1、图9J-1、图9I-2、以及图9J-2所示的示例性工艺步骤中以及在图10和图11的示例性晶体管结构中，没有使用扩散处理或注入处理。虽然可以用传统的晶体硅材料来使用这些工艺步骤和结构，但是尤其适合于使用其它类型的材料，诸如碳化硅(SiC)、氮化镓(GaN)、砷化镓(GaAs)，在此，扩散、注入和掺杂剂活化处理是难以实现和控制的。在这样的具体实施方式中，基板、基板上的外延层、源极区、以及晶体管的其它区可以由SiC、GaN和GaAs中的一种制成。而且，在传统的碳化硅基增强型FET中，反型沟道对导通电阻的贡献尤其大。相反地，对于图9J-1、图9J-2、图10以及图11中的积累晶体管的碳化硅具体实施方式中的累积沟道(积累沟道，accumulated channel)的导通电阻的贡献基本很低。
虽然主要利用积累型FET来描述上述具体实施方式，但是在增强型FET中也可实现许多上述特征和优点。例如，图2A-2I和图3A-3E中的工艺步骤可以改变为在形成上外延层205之前在下外延层204中形成p型阱区。图9A-9H、图9I-1、图9J-1和图9A-9H、图9I-2以及9J-2中的工艺步骤也可改变为在形成源极间隔体1214和1215之前在外延层1204中形成p型阱区。为了获得与肖特基二极管集成在一起的增强型FET而改变上述结构和工艺步骤具体实施方式的许多其它方式在阅览本披露内容的情况下对于本领域技术人员而言是显而易见的。
图15A-15H是根据本发明另一具体实施方式的用于形成沟-栅FET的不同工艺步骤的简化横截面视图。在图15A中，低掺杂的p型本体区1704在n型区1702中用传统的注入和驱入(drive)技术形成。在一种具体实施方式中，n型区1702包括高掺杂的基板区，低掺杂的n型外延层形成在该基板区上。在该具体实施方式中，本体区1704在n型外延层中形成。
在图15B中，包括下电介质层1706、中电介质层1708、以及上电介质层1710的电介质堆叠(介电叠层，dielectric stack)形成在本体区1704上。中电介质层需要是不同于上电介质层的电介质材料。在一种具体实施方式中，电介质堆叠包括氧化物-氮化物-氧化物。如将要看到的，中电介质层1708的厚度影响电介质帽1720(图15D)的厚度，该电介质帽1720在后来的工艺步骤中形成在栅极上，从而必须仔细选择中电介质层的厚度。下电介质层相对薄，以便使在去除下电介质层1702的后续工艺步骤中进行的电介质层1720厚度减少最小化。如图所示，电介质堆叠被图案化且被蚀刻，以限定开口1712，后来栅极沟槽通过该开口而形成。
在图15C中，实施传统的硅蚀刻以形成沟槽1703，该沟槽延伸通过本体区1704且终止于n型区1702。随后形成为沟槽侧壁和底部加衬的栅极电介质层1714，随后使用传统技术沉积多晶硅层1716。在图15D中，多晶硅层1716凹入沟槽中以形成栅极1718。电介质层在结构上形成且随后被深蚀刻，以使电介质帽1720在栅极1718正上方保留。氮化物层1708在电介质层的深蚀刻过程中用作蚀刻终止(etch stop)或蚀刻终止检测层。在图15E中，氮化物层1708使用传统技术选择性地被剥离以暴露电介质帽1720的侧壁。从而底部氧化物层1706保留在本体区1704的上方，且电介质帽1720也原封不动地保留在栅极1718之上。
在图15F中，在器件的有源区中实施毯式源极注入(blanketsource implant)，以在本体区1704中、在沟槽1703的任一侧形成高掺杂的n型区1722。电介质间隔体1724(例如，包括氧化物)随后沿电介质帽1720的暴露侧壁用传统的技术形成。注入掺杂剂的活化和驱入(drive-in)可以在工艺步骤的此阶段或稍后阶段执行。在图15G中，实施硅蚀刻，以凹入n型区1722的暴露表面，使其如所示地完全通过n型区1722并进入本体区1704。在间隔体1724正下方保留的n型区1722的部分1726形成器件的源极区。重本体区1728随后在凹入区中形成。在一种具体实施方式中，重本体区1728使用传统的技术通过填充带有p+型硅的被蚀刻硅而形成。从而，重本体区1728和源极区1726对于沟槽1703自对准。
在图15H中，电介质帽1720和间隔体1724随后被部分地深蚀刻以暴露源极区1726的表面区。蚀刻之后，半球形电介质1703保留在栅极1718上。随后形成顶部导体层1732，以接触源极区1726和重本体区1728。半球形电介质1730用来使栅极1718与顶部导体层1732电绝缘。在一种具体实施方式中，n型区1702是低掺杂的外延层，其中在该外延层之下延伸有高掺杂的n型基板(未示出)。在该具体实施方式中，形成背侧导体层(未示出)以接触基板，背侧导体层形成器件的漏极端子。这样形成了带有自对准源极和重本体区的沟-栅FET。
在可替换具体实施方式中，厚电介质层(例如，包括氧化物)在形成栅极1718之前沿沟槽1703的底部形成。厚底电介质的厚度大于栅极电介质层1714，且用来减少栅极对漏极的电容，这样提高了器件的开关速度。在又一具体实施方式中，屏蔽电极在栅极1718之下形成，类似于图4和图10-13所示的那些。
在图15A-15H所示的工艺步骤的又一变型中，在与图15F相对应的步骤之后，露出的硅表面没有凹入，且代替的是实施重本体注入和驱入工艺以形成重本体区，该重本体区延伸通过n型区1722并进入本体区1704。获得了类似于图15G的横截面视图，不同之处在于，由于驱入工艺中的侧部扩散的缘故，重本体区1728在电介质间隔体1724下方延伸。电介质间隔体1724需要足够宽，以确保n型区1722不会在重本体区的侧部扩散过程中被完全消耗掉。这可以通过选择较厚的中电介质层1708来实现。
使用电介质堆叠来获得如图15A-15H所示的自对准源极和重本体区的技术可以在类似地此处所披露的多个工艺具体实施方式中实施。例如，在图3A-3E所示的工艺具体实施方式中，对应于图3A-3B的工艺步骤可以用图15B-15E所示的工艺步骤来代替，以便获得如下所述的自对准源极和肖特基接触。
在图3A中用于形成沟槽306的掩模用三个电介质层的电介质堆叠代替，对其进行图案化及蚀刻以形成开口，通过该开口而形成沟槽(类似于图15B和图15C所示的)。其后，在图3B中，当在ONO复合层中的开口被填充以电介质帽时(类似于图15D中的电介质帽1720)，去除ONO复合层的顶层氧化物和中间的氮化物层，以露出电介质帽的侧壁(类似于图15E所示的)。图3C-3E所示的其余处理步骤保持不变。不再需要为暴露电介质312的侧壁而在图3B中实施的n+外延层305的凹入，并且可以使用更薄的外延层305。
通过用图15B-15E所示的工艺步骤代替与图9B-9相对应的工艺步骤，电介质堆叠技术也可以以类似于上述的方式在图9A-9J所示的工艺具体实施方式中实施。
图16示出了根据本发明另一具体实施方式的具有非平坦顶面(在顶部金属形成之前)的p沟道沟-栅FET的简化等比例视图。本发明不局限于p沟道FET。本领域技术人员通过阅览本公开内容将会明白如何在n沟道FET或其它类型的功率晶体管中实施本发明。在图16中，顶部金属层1832被剥去以暴露覆层区域(底层区域，underlying region)。类似地，为了说明的目的，从右侧的两个栅极1818的上方部分地去除电介质帽1820。如图所示，低掺杂的n型本体区1804在低掺杂的p型区1802上方延伸。在一种具体实施方式中，p型区1802是形成于高掺杂p型基板(未示出)上方的外延层，且本体区1804通过本领域已知的注入和驱入适当掺杂剂在外延层1802中形成。
栅极沟槽1806延伸穿过本体区1804且终止于p型区1802。每一栅极沟槽1806衬有栅极电介质1805，并且随后被填充有多晶硅，其相对于相邻硅台面区(mesa region)的顶面是凹入的。电介质帽1820在各栅极1818上方垂直地延伸。高掺杂的p型源极区1826在本体区1804中相邻的沟槽之间形成。如图所示，电介质帽1820的顶面处于高于源极区1826的顶面的平面上，这导致了非平坦顶面。在一种具体实施方式中，此非平坦性(平面性，planarity)通过凹入电介质帽1820之间的硅台面而获得。重本体区1828沿带状本体区1804在相邻沟槽之间断续地形成。顶侧金属层1832在结构上方形成，以同时与源极区1826和重本体区1828电接触。该FET结构的优点是，通过沿源极带(source stripe)断续地形成重本体区而减少了单元间距，从而获得了高密度的FET。
将利用图17A、图17B-1和图17B-2来描述形成图16的FET的两种方法。这些图没有示出重本体区，因为这些图对应于沿图16的等比例视图的前面的横截面视图。在图17A中，n型本体区1904使用传统的注入和驱入技术在p型外延层1902中形成。沟槽1906、为沟槽1906加衬的栅极绝缘体1907、以及凹入的多晶硅栅极1918用已知的技术形成。电介质层在结构上方形成，随后被平坦化，并且最终被均匀地深蚀刻直到露出硅表面。位于每一栅极正上方的空间则被填充有电介质帽1920。在一种具体实施方式中，相邻电介质区1920之间的露出硅台面表面凹入至介于电介质区1920的顶面和底面之间的深度，接着进行源极注入以形成p型源极区。在可替换具体实施方式中，在凹入硅之前实施源极的形成。重本体区(未示出)可以在形成源极区之前或之后形成。
图17B-1示出了一种变型，其中实施了硅凹入(硅凹陷，siliconrecess)，以便电介质区1920的上侧壁变得暴露(即，源极区1926具有平坦的顶面)。图17B-2示出了另一变型，其中实施了硅凹入，以便相邻沟槽之间的源极区的顶面为弓形(碗形，bowl-shaped)从而电介质区1920的侧壁不暴露。在一种具体实施方式中，这可以通过实施各向异性硅蚀刻来实现。图17B-2变型的优点在于提供了较大的源极表面区来与顶部导体层1935接触，从而减小了源极接触电阻。并且，通过沿源极带断续地形成重本体区而获得了更紧凑的单元间距，由此获得了高密度的FET。
图18是简化横截面，其示出了用于获得带有自对准重本体区和源极区的高度紧凑的沟-栅FET的技术。在图18中，其中带有栅极2012的栅极沟槽延伸穿过p-阱区2004并终止于n型漂移区2000。在一种具体实施方式中，n型漂移区2000是形成于高掺杂n型基板(未示出)上方的外延层。每一栅极沟槽包括栅极2012上的电介质帽2014。如图所示，两沟槽之间的台面区是凹入的，使得硅凹入具有倾斜的外壁，该外壁从电介质帽2014的顶部附近延伸到台面槽的底部。
如垂直于台面槽底表面延伸的实线箭头2019所指示的，高掺杂p型重本体区2016通过以0度角实施掺杂剂(例如，BF2)的毯式注入(blanket implant)而形成。在设定0度角的重本体注入的情况下，各沟槽侧壁的相对的斜面及台面槽的与其非常接近的外壁以及精心选择的注入掺杂剂类型和注入变量(诸如注入能量)，保证了被注入掺杂剂不会到达沿沟槽侧壁在阱区2004中延伸的沟道区。
如两个成角的虚线箭头2018所指示的，实施n型掺杂剂的两路成角的毯式注入，以沿各台面槽的倾斜侧壁形成源极区2020。如图所示，沟槽的上拐角阻碍了源极注入进入重本体区的中心部分。可以看出，在重本体区注入或双流倾斜源极注入过程中都没有使用掩模。事实上，台面槽形成了能够形成自对准重本体区和源极区的自然掩模。
自对准重本体区和源极区使单元间距显著地减小了，结果产生了高密度的单元结构，其继而有助于减小晶体管的导通电阻。而且，自对准重本体区有助于改善未钳位感应开关(unclamped inductiveswitching，UIL)的耐久性(ruggedness)。并且，以自对准方式形成源极区和重本体区减少了掩模数量，从而降低了制造成本，同时简化了工艺步骤并提高制造产率。另外，源极区和重本体区的具体轮廓(profile)的好处在于：(i)台面槽的倾斜外壁提供了大的源极表面区，其有助于减小源极接触电阻，以及(ii)重本体区交叠在源极区之下，其有助于提高晶体管的UIL耐久性。而且，可以看出，图18所示的技术适合于许多厚底电介质工艺，且其自身很好地适用于LOCOS(硅的局部氧化)工艺。
图18A-18I、图19A-19H、图20A-20G、图21A-21H、以及图22A-22F示出了各种工艺步骤，其中，图18所示的技术用于形成具有自对准特性的各种FET。具有图18中所描述的和所实施的技术的许多其它工艺步骤或在此所披露的那些的变型对于本领域技术人员来说在阅览本公开内容的情况下是可以预见的。
图18A-18I示出了根据本发明另一具体实施方式的用于形成具有自对准源极和重本体区的沟-栅FET的不同工艺步骤的横截面视图。在图18A中，传统的硅蚀刻和LOCOS工艺用于在终止区(termination region)形成绝缘-填充沟槽2001。焊盘氧化物层(未示出)和氮化物层(未示出)首先在n型硅区2000上形成。随后使用第一掩模在端子区限定硅区2000的待去除硅的部分。氮化物层、焊盘氧化物以及下面的硅区通过第一掩模而去除，以在端子区形成沟槽2001。随后实施局部氧化，以用绝缘材料2002填充沟槽2001。虽然未示出，但起始材料可以包括其上形成(例如，外延地形成)有n型区2000的高掺杂n型基板。
在图18B中，实施毯式阱注入和驱入，以便在硅区2000上形成p型阱区2004。可替换地，所注入的杂质可以在工艺的后面阶段驱入。在图18C中，实施第二掩模步骤，以限定和蚀刻沟槽2006，该沟槽延伸穿过阱区2004并终止于硅区2000内。沟槽2006的底部填充有绝缘材料，例如通过沉积高密度等离子体(HDP)氧化物，并且随后蚀刻所沉积的HDP氧化物，以形成厚底氧化物2008。
在图18D中，栅极绝缘层2010沿包括沟槽侧壁的所有表面区形成。随后沉积多晶硅并进行掺杂(例如，原位掺杂)。使用第三掩模来限定和蚀刻多晶硅，以在有源区中形成凹入式栅极2012A、并形成终止沟槽栅极(termination trench gate)2012B和表面栅极2012C。在图18E中，电介质层在结构上形成。接着使用第四掩模来限定有源区的部分和在终止区的开口2015，在此处，电介质层将会被深蚀刻。通过掩模开口蚀刻电介质层，直到触及硅。从而，在有源区，位于各栅极2012A正上方的空间保留为被填充有电介质材料2014A，同时开口2015在终止区形成。如可以看到的，有源区中阱区2004B以及终止区的阱区2004A的表面被暴露。
在图18F中，实施硅蚀刻步骤以使有源区和终止区中所暴露的硅表面区凹入。基本弓形的硅表面在有源区的相邻沟槽之间的阱区2004B中以及在终止区的阱区2004A中形成。接着，实施0度重本体注入(例如，BF2)，以在有源区的阱区2004B中形成p型重本体区2016B，以及在终止区的阱区2004A中形成重本体区2016A。源极区2020如箭头2018所示随后利用两路成角源极注入而形成。在双流倾斜注入(两路成角注入，two-pass angled implant)中，n型杂质以如下角度注入，即，沟槽的上拐角阻止重本体区的中心部分2016B接收注入。源极区2020因而接近沟槽地立即形成，同时重本体区的中心部分2016B如图所示原封不动地保留着。由于开口2015(图18E)的纵横比和两路源极注入的角度的缘故，终止阱区2004A没有接收到源极注入。
在图18G中，实施注入活化步骤以将注入的掺杂剂驱入。随后使用第五掩模来限定和蚀刻绝缘层2014C，以形成栅极接触开口2019。在图18H中，导体层(例如，包括金属)随后在结构上形成。使用第六掩模来限定和蚀刻导体层，以便使源极导体2021A与栅极导体2021B绝缘。在图18I中，沉积钝化层。随后使用第七掩模来蚀刻部分钝化层，从而限定将形成引线接合触点的源极区和栅极区。在不需要钝化层的具体实施方式中，可省略相应的掩模和工艺步骤。
可以看出，在形成重本体区2016B和源极区2020的过程中没有使用掩模。同样，重本体区和源极区都与沟槽边缘是自对准的。而且，重本体区2016B叠置在源极区2020之下，但没有延伸到沟道区中。从而获得了紧凑的单元间距以及异常弹回(快反向，snapback)和UIL耐久性。小的单元间距有助于获得较低的Rdson。同样，由于源极区2020沿阱区2004B的外弯曲表面形成，因此获得了较大的源极接触面积，从而获得了较低的源极接触电阻。另外，简单工艺步骤使用了数量减少的掩模步骤，适于许多厚底氧化物(TBO)处理模块，并且其自身很好地适用于形成TBO的LOCOS方法。
图18A-18I的横截面仅示出了示例性工艺步骤和示例性终止结构。该工艺步骤可以以各种方式优化以便进一步减少掩模数量并且实现不同的终止结构，其包括下面所描述的图19A-19H、图20A-20G、图21A-21H、以及图22A-22F中的工艺步骤所图解说明的那些。
图19A-19H是工艺步骤的横截面视图，其中，形成有沟槽的多晶硅来代替表面多晶硅，与图18A-18I的工艺步骤相比，该有沟槽的多晶硅使掩模的数量减少了一个。与图19A-19C对应的工艺步骤类似于图18A-18C所对应的那些，因而将不作解释。在图19D中，形成栅极绝缘体2110并且随后沉积多晶硅并进行掺杂。对沉积的多晶硅进行毯式蚀刻，以使在沟槽中保留了凹入式栅极2112。这里，前述具体实施方式的图18D中的栅极掩模被省略了。在图19E中，实施类似于图18E中的工艺步骤顺序的工艺步骤，以使位于各栅极2112正上方的空间被填充电介质材料2114A，同时开口2115在电介质层中在终止p-阱2014A上形成。在图19F中，实施类似图18F中工艺步骤顺序的工艺步骤，以形成自对准重本体区2116A和2116B和自对准源极区2120。
在图19G中，使用栅极接触掩模(第四掩模)而在电介质层中在远离的左栅极沟槽上限定和蚀刻栅极接触开口2113，接着进行注入掺杂剂的活化。栅极接触开口2113提供通向有沟槽的多晶硅栅极的电通道(electrical)，所述有沟槽的多晶硅栅极沿图19G中未示出的第三维度互连。在可替换具体实施方式中，允许终止p-阱2104A漂移，由此省去了对终止源极导体2121A的需要。
在图19H中，沉积导体层(例如，包括金属)，接着是掩模步骤(第五)，以限定源极导体部分2121A并使源极导体部分2121A与栅极导体部分2121B绝缘。可以看出，在图19A-19H所示的工艺中仅使用了五个掩模。直接位于栅极导体层和源极导体层下方的薄层是可选的势垒金属。
图20A-20G是另一工艺步骤的横截面视图，该工艺步骤与图18A-18I所示的工艺相比使用的掩模较少。图20A-20D所对应的工艺步骤类似于图18A-18D所对应的工艺步骤，因此将不作解释。图20E所对应的工艺步骤类似于图18E所对应的工艺步骤，所不同的是，使用第四掩模在终止电介质层中在表面多晶硅2212C上形成额外的开口2217。图20F所对应的工艺步骤类似于图18F所对应的工艺步骤。然而，由于表面多晶硅2212C上的开口2217(在图20E中)的缘故，用于凹入暴露的台面的硅蚀刻也蚀刻了表面多晶硅2212C的已暴露部分，从而产生开口2218。表面多晶硅的侧壁则通过接触开口2218而变得暴露。根据有源区中台面槽的深度和表面多晶硅2212C的厚度，台面槽蚀刻可以完全蚀刻并穿过表面多晶硅2212C或沿开口2218的底部留下多晶硅的薄层。在一种具体实施方式中，形成开口2218，以致它的纵横比使两个成角的源极注入2218到达表面多晶硅部分2213A和2213B的侧壁。这有利地使后来形成的栅极导体层2221B(图20G)与表面多晶硅部分2213A和2213B之间的接触电阻最小化。
除了图20G的工艺步骤包括对注入区的活化以外，图20G所对应的工艺步骤类似于图18H所对应的工艺步骤。同样，不像图18H(其中栅极导体2021B接触多晶硅2012C的顶面)，图20G中的栅极导体2221B通过开口2218接触表面多晶硅的侧壁。如果在图20F中的硅凹入步骤之后表面多晶硅2212C没有完全蚀穿(即，它的一部分沿开口2218的底部保留着)，那么栅极导体2021B将同样接触开口2218中留下的多晶硅的表面区。
在图20G中，直接位于源极导体层和栅极导体层之下的薄层是可选的势垒金属。该具体实施方式的优点在于，类似于图19A-19H的具体实施方式，在形成顶侧导体的整个步骤中仅使用五个掩模，而且还通过省掉包围周边栅极导体层2121B(图19H)的源极导体层2121A(图19H)而保存了表面区。
图21A-21H是不同工艺步骤的横截面视图，该工艺步骤用于形成类似于图18A-18I所示的工艺得到的沟-栅FET的沟-栅FET，不同之处在于，肖特基二极管与FET集成。图21A所对应的工艺步骤类似于图18A所对应的工艺步骤，因而将不再解释。在图21B中，使用p-阱屏蔽掩模(blocking mask)(第二掩模)来注入和驱入p型杂质，以在n型硅区2300中形成阱区2304。可替换地，所注入的杂质可在工艺步骤的稍后阶段被驱入推阱。p-阱屏蔽掩模阻止p型杂质被注入到硅区2300的(如所示)形成肖特基区的部分2303中。
在图21C和图21D中，实施类似于图18C和图18D的一批工艺步骤，因此将不再描述。在图21E中，实施与图18E相类似的工艺步骤，但是还实施接触掩模(第五)和电介质平坦化步骤，以使绝缘层的部分2314D保留在肖特基区2303上，以防止该区域在稍后的源极和重本体注入步骤(图21F)过程中接收掺杂剂。图21F所对应的工艺步骤类似于图18F所对应的工艺步骤，因此将不再描述。
在图21G中，实施注入活化步骤以驱入被注入的掺杂剂。随后使用第六掩模，以在肖特基区2303上限定和蚀刻绝缘区2314D并且在表面栅极2312C上形成栅极接触开口2319。图21H所对应的工艺步骤与图18H所对应的相同，不同之处在于，在与源极和重本体区相接触之外，源极导体2321A还与肖特基区2303相接触，以与硅区2300形成肖特基接触，该硅区例如使用硅化钛作为势垒金属。这样就形成了具有集成肖特基二极管的沟-栅FET。
虽然图21A-21H示出了如何利用图18A-18I所示的工艺步骤集成肖特基二极管，但是可以类似地改变图19A-19H、图20A-20G、图21A-21H、图22A-22F、图23A-23I、以及图24A-24I各自所示的工艺步骤以集成肖特基二极管。
图22A-22F是根据具体实施方式的用于形成沟-栅FET的另一工艺步骤的横截面视图，其中，在顶侧源极和栅极导体的整个形成过程中的掩模数量减少至四个。在图22A中，焊盘氧化物层(未示出)形成于n型硅区2400上。p型传导性的掺杂剂被注入并驱入(推阱)，以在n型硅区2400中形成p-阱区2404。可替换地，所注入的杂质可以在工艺步骤的稍后阶段被驱入。使用第一掩模以在有源区限定和蚀刻沟槽2406并且在终止区限定和蚀刻宽沟槽2401。随后，使用LOCOS厚底氧化物(TBO)工艺沿有源沟槽2406和宽终止沟槽(termination trench)2401两者的底部以及相邻沟槽之间硅台面(silicon mesa)的顶面上形成绝缘材料2402的层。
图22C所对应的工艺步骤类似于图20D所对应的工艺步骤，然而，在图22C中，代替图20D中形成平坦的表面多晶硅2212C的是，多晶硅2412C在终止p-阱2204A上延伸并且下降到宽沟槽2401中。图22D、图22E和图22F各自所对应的工艺步骤分别类似于图20E、图20F、和图20G各自所对应的工艺步骤，因而将不再描述。如在图22F中可以看到的，栅极导体2421B与终止区宽沟槽内的栅极2412D的侧壁接触。如在图20A-20G具体实施方式中的一样，如果在图22E的硅凹入步骤之后，终止多晶硅2412C没有完全蚀穿(即，它的一部分沿多晶硅2412C的开口2218的底部保留)，那么栅极导体2021B也将接触开口2218中的残留多晶硅的顶面区。总共使用了四个掩模，其与钝化焊盘掩模一起(例如，像在图18I所对应的工艺步骤中所确定的一样)合计5个掩模。
图23A-23I是根据本发明又一具体实施方式的用于形成具有自对准特征的沟-栅FET的不同工艺步骤的横截面视图。图23A-23D所对应的工艺步骤类似于图18A-18D所对应的那些，因此将不再描述。在图23E中，电介质层在结构上形成。随后，使用第四掩模来覆盖终止区，这是因为在有源区中实施电介质的平坦化蚀刻以使电介质帽2514A保留在各沟槽栅极2512A上。在图23F中，实施台面槽蚀刻，以使p型阱区2504B凹入电介质帽2514A的顶面之下，从而电介质帽2514A的上侧壁变得暴露。随后实施掺杂剂(例如砷)的毯式注入，以在相邻沟槽之间的阱区2504B中形成n+区2517。随后，使用传统技术在n+区2517上沿电介质帽2514A的露出侧壁形成氮化物间隔体2518。在图23G中，使相邻间隔体2518之间所暴露的硅台面凹入到阱区2504B内的深度。硅凹入去除了n+区2517的中间部分(图23F)，留下了n+区2517的在完整的间隔体2518正下方延伸的外部2520。部分2520形成晶体管的源极区。随后，注入p型杂质掺杂剂，以形成重本体区2516。
在图23H中，使用传统技术去除氮化物间隔体2518。随后，在终止区使用第五掩模，以在电介质区2514B中产生开口2515和2519。在图23I中，源极导体和栅极导体以类似于图18I中的方式形成。这样总计使用了六个掩模。该工艺步骤尤其适合于形成具有宽间距本体的沟栅FET。而且，该工艺步骤有利地产生对于沟槽来说是自对准的源极区和重本体区的形成。
图24A-24I是根据本发明又一具体实施方式的用于形成沟-栅FET的不同工艺步骤的横截面视图。图24A-24D所对应的工艺步骤类似于图19A-19D所对应的那些，因此将不再描述。在图24E中，电介质层形成在结构上。随后，使用第三掩模来覆盖终止区，这是因为在有源区中实施电介质平坦化蚀刻，以便在各沟槽栅极2612上形成电介质帽2614A。图24F和图24G所对应的工艺步骤分别类似于图23F和图23G所对应的那些，因此将不再描述。
在图24H中，使用传统技术来去除氮化物间隔体2618。随后在终止区中使用第四掩模，以在电介质区2614B(图24G)中产生开口2615。在图24I中，金属层在结构上形成，并且使用第五掩模来限定源极导体2621A和栅极导体2621B。如图所示，源极导体2621A沿其顶面和侧壁与重本体区2616和源极区2620相接触。终止阱区2604B电漂移。可替换地，阱区2604B可通过沿进入纸面的方向所进行的电接触而偏压。
与图23A-23I所表示的具体实施方式类似，本具体实施方式适合于形成具有宽间距本体的沟栅FET，并且本具体实施方式具有相对于沟槽是自对准的源极和重本体区。然而，有利地，本具体实施方式需要比图23A-23I具体实施方式所需要的掩模少一个的掩模。
虽然由图18A-18I、图19A-19H、图20A-20G、图21A-21H、图22A-22F、图23A-23I、以及图24A-24I所表示的各工艺步骤是以单个栅极沟槽结构为背景示出的，但对于本领域技术人员而言在阅读本公开内容的情况下，对这些工艺步骤进行修改以包括栅极之下的屏蔽电极(类似于图10中的屏蔽栅极1324)将是显而易见的。
本发明的各种结构和方法可以与上面所参照的普通转让申请第11/026，276号中所披露的一种或多种大量电荷扩散技术结合，以获得更低的导通电阻、更高的阻断能力和更高的效率。
不同具体实施方式的横截面视图可以不按规定比例，并且同样地并不意味着在相应结构布图设计中限制可能的变型。并且，各种晶体管可以在开放单元结构(例如，带)中或封闭单元结构(例如，六边形或方形单元)中形成。
虽然以上示出和描述了大量的具体具体实施方式，但本发明的具体实施方式不限于此。例如，应当理解，在不背离本发明的情况下，已示出和描述的结构的掺杂极性可以反向，和/或各要素(element)的掺杂浓度可以改变。作为另一实例，上述的各种示例性的积累型和增强型垂直晶体管(纵向晶体管)具有终止于漂移区(在基板上延伸的低掺杂的外延层)的沟槽，但是它们也可以终止于高掺杂的基板。同样，在不背离本发明的范围的情况下，本发明的一个或多个具体实施方式的特征可以与本发明其它具体实施方式的一个或多个特征组合。由于这样和那样的原因，因此，以上描述不应该理解为限制本发明的范围，本发明的范围由所附权利要求所限定。

Claims (8)

1.一种形成场效应晶体管的方法，所述场效应晶体管具有有源区和围绕所述有源区的终止区，所述方法包括：
在第一硅区中形成阱区，所述阱区和所述第一硅区是相反传导型的；
形成栅极沟槽，所述栅极沟槽延伸穿过所述阱区并终止于所述第一硅区内；
在每一栅极沟槽中形成凹入式栅极；
在每一凹入式栅极上形成电介质帽；
使相邻沟槽之间的所述阱区凹入，以暴露每一电介质帽的上侧壁；
实施毯式源极注入，以在每两个相邻沟槽之间的所述凹入阱区的上部中形成第二硅区，所述第二硅区与第一硅区是相同传导型的；
沿所述电介质帽的每一暴露的上侧壁形成电介质间隔体，位于每两个相邻栅极沟槽之间的每两个相邻电介质间隔体在所述第二硅区上形成开口；以及
通过在每两个相邻电介质间隔体之间的所述开口使所述第二硅区凹入，以使仅所述第二硅区的在所述电介质间隔体正下方的部分保留下来，所述第二硅区的所述保留部分形成源极区。
2.根据权利要求1所述的方法，进一步包括在形成顶侧导体层之前去除所述电介质间隔体，以使所述顶侧导体层接触每一源极区的顶面。
3.根据权利要求1所述的方法，进一步包括：
在形成所述凹入式栅极之前，沿每一栅极沟槽的底部形成厚底电介质；以及
在形成所述凹入式栅极之前，形成为每一栅极沟槽的所述侧壁加衬的栅极电介质，其中，所述厚底电介质厚于所述栅极电介质。
4.根据权利要求1所述的方法，进一步包括：
在形成所述凹入式栅极之前，沿每一栅极沟槽的底部形成屏蔽电极；以及
在形成所述凹入式栅极之前，在每一屏蔽电极上形成电介质层。
5.根据权利要求1所述的方法，进一步包括：
在所述终止区中形成宽沟槽；以及用LOCOS填充所述宽沟槽。
6.根据权利要求1所述的方法，进一步包括在所述栅极沟槽中形成所述凹入式栅极的同时，在所述终止区内形成表面栅极。
7.根据权利要求6所述的方法，进一步包括：
在所述表面栅极上形成开口；以及形成通过所述开口接触所述表面栅极的栅极导体。
8.根据权利要求1所述的方法，进一步包括：
在形成所述栅极沟槽的同时，在所述终止区内形成终止沟槽；
在所述栅极沟槽内形成所述凹入式栅极的同时，在所述终止沟槽中形成凹入式栅极；
在所述终止沟槽中的所述凹入式栅极上形成开口；以及
形成栅极导体，所述栅极导体通过所述开口接触所述终止沟槽中的所述凹入式栅极。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367360A (zh) * 2012-03-26 2013-10-23 株式会社东芝 半导体元件
US8680611B2 (en) 2005-04-06 2014-03-25 Fairchild Semiconductor Corporation Field effect transistor and schottky diode structures
CN105977157A (zh) * 2016-07-25 2016-09-28 吉林华微电子股份有限公司 一种igbt器件的制造方法及其器件
CN106098561A (zh) * 2016-07-25 2016-11-09 吉林华微电子股份有限公司 一种mosfet器件的制造方法及其器件
CN106098752A (zh) * 2016-07-25 2016-11-09 吉林华微电子股份有限公司 一种igbt器件及其制造方法

Families Citing this family (163)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6916745B2 (en) 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
US9685524B2 (en) 2005-03-11 2017-06-20 Vishay-Siliconix Narrow semiconductor trench structure
DE112006001516T5 (de) 2005-06-10 2008-04-17 Fairchild Semiconductor Corp. Feldeffekttransistor mit Ladungsgleichgewicht
TWI400757B (zh) * 2005-06-29 2013-07-01 Fairchild Semiconductor 形成遮蔽閘極場效應電晶體之方法
US9159568B2 (en) * 2006-02-04 2015-10-13 Cypress Semiconductor Corporation Method for fabricating memory cells having split charge storage nodes
US8409954B2 (en) 2006-03-21 2013-04-02 Vishay-Silconix Ultra-low drain-source resistance power MOSFET
US7446374B2 (en) 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
JP2007311574A (ja) * 2006-05-18 2007-11-29 Nec Electronics Corp 半導体装置及びその製造方法
US7732842B2 (en) * 2006-12-06 2010-06-08 Fairchild Semiconductor Corporation Structure and method for forming a planar schottky contact
KR100780658B1 (ko) * 2006-12-27 2007-11-30 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US9437729B2 (en) * 2007-01-08 2016-09-06 Vishay-Siliconix High-density power MOSFET with planarized metalization
US8564057B1 (en) 2007-01-09 2013-10-22 Maxpower Semiconductor, Inc. Power devices, structures, components, and methods using lateral drift, fixed net charge, and shield
US8659074B2 (en) * 2007-01-09 2014-02-25 Maxpower Semiconductor, Inc. Semiconductor device
US7670908B2 (en) * 2007-01-22 2010-03-02 Alpha & Omega Semiconductor, Ltd. Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling
US9947770B2 (en) * 2007-04-03 2018-04-17 Vishay-Siliconix Self-aligned trench MOSFET and method of manufacture
US20080296674A1 (en) * 2007-05-30 2008-12-04 Qimonda Ag Transistor, integrated circuit and method of forming an integrated circuit
JP4492735B2 (ja) * 2007-06-20 2010-06-30 株式会社デンソー 半導体装置及び半導体装置の製造方法
US8497549B2 (en) * 2007-08-21 2013-07-30 Fairchild Semiconductor Corporation Method and structure for shielded gate trench FET
US8686493B2 (en) * 2007-10-04 2014-04-01 Fairchild Semiconductor Corporation High density FET with integrated Schottky
US9484451B2 (en) * 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
JP5196980B2 (ja) * 2007-12-10 2013-05-15 株式会社東芝 半導体装置
US20100013009A1 (en) * 2007-12-14 2010-01-21 James Pan Structure and Method for Forming Trench Gate Transistors with Low Gate Resistance
JP2009188294A (ja) * 2008-02-08 2009-08-20 Nec Electronics Corp パワーｍｏｓｆｅｔ
US9882049B2 (en) * 2014-10-06 2018-01-30 Alpha And Omega Semiconductor Incorporated Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
US8878292B2 (en) * 2008-03-02 2014-11-04 Alpha And Omega Semiconductor Incorporated Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
JP5721308B2 (ja) * 2008-03-26 2015-05-20 ローム株式会社 半導体装置
US8269263B2 (en) * 2008-05-12 2012-09-18 Vishay-Siliconix High current density power field effect transistor
US7910439B2 (en) * 2008-06-11 2011-03-22 Maxpower Semiconductor Inc. Super self-aligned trench MOSFET devices, methods, and systems
US7807576B2 (en) * 2008-06-20 2010-10-05 Fairchild Semiconductor Corporation Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices
US7872305B2 (en) * 2008-06-26 2011-01-18 Fairchild Semiconductor Corporation Shielded gate trench FET with an inter-electrode dielectric having a nitride layer therein
JP5342182B2 (ja) * 2008-07-01 2013-11-13 古河電気工業株式会社 ショットキーバリアダイオードおよびその製造方法
US8237195B2 (en) * 2008-09-29 2012-08-07 Fairchild Semiconductor Corporation Power MOSFET having a strained channel in a semiconductor heterostructure on metal substrate
US7915672B2 (en) * 2008-11-14 2011-03-29 Semiconductor Components Industries, L.L.C. Semiconductor device having trench shield electrode structure
US8304829B2 (en) 2008-12-08 2012-11-06 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8174067B2 (en) * 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8188484B2 (en) 2008-12-25 2012-05-29 Rohm Co., Ltd. Semiconductor device
US8188538B2 (en) 2008-12-25 2012-05-29 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US8227855B2 (en) * 2009-02-09 2012-07-24 Fairchild Semiconductor Corporation Semiconductor devices with stable and controlled avalanche characteristics and methods of fabricating the same
US8148749B2 (en) * 2009-02-19 2012-04-03 Fairchild Semiconductor Corporation Trench-shielded semiconductor device
TWI419457B (zh) * 2009-05-21 2013-12-11 Chip Goal Electronics Corp 交直流轉換整合元件與使用該元件的積體電路
US7915645B2 (en) * 2009-05-28 2011-03-29 International Rectifier Corporation Monolithic vertically integrated composite group III-V and group IV semiconductor device and method for fabricating same
JP2012160485A (ja) * 2009-06-09 2012-08-23 Panasonic Corp 半導体装置とその製造方法
US8049276B2 (en) 2009-06-12 2011-11-01 Fairchild Semiconductor Corporation Reduced process sensitivity of electrode-semiconductor rectifiers
US9443974B2 (en) 2009-08-27 2016-09-13 Vishay-Siliconix Super junction trench power MOSFET device fabrication
US9425305B2 (en) * 2009-10-20 2016-08-23 Vishay-Siliconix Structures of and methods of fabricating split gate MIS devices
US9431530B2 (en) * 2009-10-20 2016-08-30 Vishay-Siliconix Super-high density trench MOSFET
US8021947B2 (en) 2009-12-09 2011-09-20 Semiconductor Components Industries, Llc Method of forming an insulated gate field effect transistor device having a shield electrode structure
CN102097468B (zh) * 2009-12-15 2013-03-13 上海华虹Nec电子有限公司 沟槽型mosfet结构及其制备方法
JP2011134910A (ja) 2009-12-24 2011-07-07 Rohm Co Ltd ＳｉＣ電界効果トランジスタ
JP2011134985A (ja) * 2009-12-25 2011-07-07 Fuji Electric Co Ltd トレンチゲート型半導体装置とその製造方法
US20110198689A1 (en) * 2010-02-17 2011-08-18 Suku Kim Semiconductor devices containing trench mosfets with superjunctions
CN102214603B (zh) * 2010-04-06 2013-09-04 科轩微电子股份有限公司 具有肖特基二极管的功率半导体结构及其制造方法
US8618462B2 (en) * 2010-05-26 2013-12-31 Semiconductor Energy Laboratory Co., Ltd. Photoelectric transducer device having a rectifier is a second transistor with diode-connected and normally on
US8432000B2 (en) * 2010-06-18 2013-04-30 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
JP5691259B2 (ja) * 2010-06-22 2015-04-01 株式会社デンソー 半導体装置
WO2012055119A1 (zh) * 2010-10-29 2012-05-03 上海韦尔半导体股份有限公司 一种沟槽式mosfet的侧墙结构及其制造方法
US8362550B2 (en) * 2011-01-20 2013-01-29 Fairchild Semiconductor Corporation Trench power MOSFET with reduced on-resistance
TW201240016A (en) * 2011-03-25 2012-10-01 Taiwan Semiconductor Co Ltd Manufacturing method of semiconductor substrate
US8431470B2 (en) * 2011-04-04 2013-04-30 Alpha And Omega Semiconductor Incorporated Approach to integrate Schottky in MOSFET
US8502313B2 (en) * 2011-04-21 2013-08-06 Fairchild Semiconductor Corporation Double layer metal (DLM) power MOSFET
US8502314B2 (en) * 2011-04-21 2013-08-06 Fairchild Semiconductor Corporation Multi-level options for power MOSFETS
US8502302B2 (en) * 2011-05-02 2013-08-06 Alpha And Omega Semiconductor Incorporated Integrating Schottky diode into power MOSFET
US8466513B2 (en) 2011-06-13 2013-06-18 Semiconductor Components Industries, Llc Semiconductor device with enhanced mobility and method
US9431484B2 (en) * 2011-07-29 2016-08-30 Infineon Technologies Austria Ag Vertical transistor with improved robustness
US8829574B2 (en) * 2011-12-22 2014-09-09 Avogy, Inc. Method and system for a GaN vertical JFET with self-aligned source and gate
JP6290526B2 (ja) 2011-08-24 2018-03-07 ローム株式会社 半導体装置およびその製造方法
US8575685B2 (en) * 2011-08-25 2013-11-05 Alpha And Omega Semiconductor Incorporated Buried field ring field effect transistor (BUF-FET) integrated with cells implanted with hole supply path
DE102011054372B4 (de) * 2011-10-11 2013-11-21 Infineon Technologies Austria Ag Verfahren zur Herstellung einer Halbleitertransistorstruktur
KR20130049919A (ko) * 2011-11-07 2013-05-15 현대자동차주식회사 실리콘카바이드 쇼트키 배리어 다이오드 소자 및 이의 제조 방법
US9431249B2 (en) 2011-12-01 2016-08-30 Vishay-Siliconix Edge termination for super junction MOSFET devices
CN103187282B (zh) * 2011-12-29 2016-04-13 立新半导体有限公司 一种沟槽半导体功率器件的制备方法
CN103187281B (zh) * 2011-12-29 2016-04-13 立新半导体有限公司 一种沟槽半导体功率分立器件的制备方法
US8785278B2 (en) 2012-02-02 2014-07-22 Alpha And Omega Semiconductor Incorporated Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
DE102012102533B3 (de) * 2012-03-23 2013-08-22 Infineon Technologies Austria Ag Integrierte Leistungstransistorschaltung mit Strommesszelle und Verfahren zu deren Herstellung sowie eine Anordnung diese enthaltend
US8759172B2 (en) * 2012-04-18 2014-06-24 International Business Machines Corporation Etch stop layer formation in metal gate process
CN103426738B (zh) 2012-05-17 2018-05-18 恩智浦美国有限公司 具有边缘端部结构的沟槽半导体器件及其制造方法
US8642425B2 (en) 2012-05-29 2014-02-04 Semiconductor Components Industries, Llc Method of making an insulated gate semiconductor device and structure
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US8896060B2 (en) 2012-06-01 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Trench power MOSFET
US8969955B2 (en) * 2012-06-01 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Power MOSFET and methods for forming the same
JP2013258327A (ja) * 2012-06-13 2013-12-26 Toshiba Corp 半導体装置及びその製造方法
TWI521719B (zh) 2012-06-27 2016-02-11 財團法人工業技術研究院 雙凹溝槽式蕭基能障元件
US9054183B2 (en) * 2012-07-13 2015-06-09 United Silicon Carbide, Inc. Trenched and implanted accumulation mode metal-oxide-semiconductor field-effect transistor
US8778764B2 (en) 2012-07-16 2014-07-15 Semiconductor Components Industries, Llc Method of making an insulated gate semiconductor device having a shield electrode structure and structure therefor
JP2014056890A (ja) * 2012-09-11 2014-03-27 Toshiba Corp 半導体装置及びその製造方法
CN103681316A (zh) * 2012-09-14 2014-03-26 北大方正集团有限公司 一种深沟槽肖特基二极管及其工艺制作方法
KR101920247B1 (ko) * 2012-09-17 2018-11-20 삼성전자 주식회사 반도체 장치 및 그 제조 방법
JP6091941B2 (ja) * 2012-09-27 2017-03-08 ルネサスエレクトロニクス株式会社 半導体装置
US9799762B2 (en) 2012-12-03 2017-10-24 Infineon Technologies Ag Semiconductor device and method of manufacturing a semiconductor device
TW201423869A (zh) * 2012-12-13 2014-06-16 Anpec Electronics Corp 溝渠式電晶體的製作方法
TWI520337B (zh) 2012-12-19 2016-02-01 財團法人工業技術研究院 階梯溝渠式金氧半場效電晶體及其製造方法
TWI521718B (zh) 2012-12-20 2016-02-11 財團法人工業技術研究院 接面位障蕭特基二極體嵌於金氧半場效電晶體單元陣列之整合元件
CN103022090A (zh) * 2012-12-27 2013-04-03 淄博美林电子有限公司 一种高效率、高耐压肖特基芯片
JP6170812B2 (ja) * 2013-03-19 2017-07-26 株式会社東芝 半導体装置の製造方法
JP2014187141A (ja) * 2013-03-22 2014-10-02 Toshiba Corp 半導体装置
KR101934893B1 (ko) 2013-03-27 2019-01-03 삼성전자 주식회사 그루브 소스 컨택 영역을 가진 반도체 소자의 제조 방법
KR101828495B1 (ko) * 2013-03-27 2018-02-12 삼성전자주식회사 평탄한 소스 전극을 가진 반도체 소자
US10249721B2 (en) 2013-04-04 2019-04-02 Infineon Technologies Austria Ag Semiconductor device including a gate trench and a source trench
TW201443999A (zh) * 2013-05-14 2014-11-16 Anpec Electronics Corp 溝渠式功率半導體元件的製作方法
US9029220B2 (en) 2013-06-18 2015-05-12 Infineon Technologies Austria Ag Method of manufacturing a semiconductor device with self-aligned contact plugs and semiconductor device
US9666663B2 (en) 2013-08-09 2017-05-30 Infineon Technologies Ag Semiconductor device with cell trench structures and contacts and method of manufacturing a semiconductor device
US9029974B2 (en) * 2013-09-11 2015-05-12 Infineon Technologies Ag Semiconductor device, junction field effect transistor and vertical field effect transistor
US9076838B2 (en) 2013-09-13 2015-07-07 Infineon Technologies Ag Insulated gate bipolar transistor with mesa sections between cell trench structures and method of manufacturing
KR20150035198A (ko) * 2013-09-27 2015-04-06 삼성전자주식회사 반도체 소자 및 그 제조방법
US9306058B2 (en) 2013-10-02 2016-04-05 Infineon Technologies Ag Integrated circuit and method of manufacturing an integrated circuit
US9287404B2 (en) 2013-10-02 2016-03-15 Infineon Technologies Austria Ag Semiconductor device and method of manufacturing a semiconductor device with lateral FET cells and field plates
US9401399B2 (en) 2013-10-15 2016-07-26 Infineon Technologies Ag Semiconductor device
US20150118810A1 (en) * 2013-10-24 2015-04-30 Madhur Bobde Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path
KR101790818B1 (ko) * 2013-10-28 2017-10-27 매그나칩 반도체 유한회사 반도체 소자
US9385228B2 (en) 2013-11-27 2016-07-05 Infineon Technologies Ag Semiconductor device with cell trench structures and contacts and method of manufacturing a semiconductor device
US9553179B2 (en) 2014-01-31 2017-01-24 Infineon Technologies Ag Semiconductor device and insulated gate bipolar transistor with barrier structure
US9508596B2 (en) 2014-06-20 2016-11-29 Vishay-Siliconix Processes used in fabricating a metal-insulator-semiconductor field effect transistor
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
US9269779B2 (en) 2014-07-21 2016-02-23 Semiconductor Components Industries, Llc Insulated gate semiconductor device having a shield electrode structure
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
EP3183753A4 (en) 2014-08-19 2018-01-10 Vishay-Siliconix Electronic circuit
CN104201194B (zh) * 2014-08-26 2016-10-05 电子科技大学 一种具有超低比导通电阻特性的高压功率器件
DE102015011718A1 (de) * 2014-09-10 2016-03-10 Infineon Technologies Ag Gleichrichtervorrichtung und Anordnung von Gleichrichtern
US9627328B2 (en) 2014-10-09 2017-04-18 Infineon Technologies Americas Corp. Semiconductor structure having integrated snubber resistance
KR102143438B1 (ko) * 2014-12-04 2020-08-11 삼성전자주식회사 반도체 소자용 액티브 구조물 및 이의 형성 방법
US9281368B1 (en) * 2014-12-12 2016-03-08 Alpha And Omega Semiconductor Incorporated Split-gate trench power MOSFET with protected shield oxide
KR101655153B1 (ko) * 2014-12-12 2016-09-22 현대자동차 주식회사 반도체 소자 및 그 제조 방법
CN104617045B (zh) * 2015-01-19 2017-06-06 上海华虹宏力半导体制造有限公司 沟槽栅功率器件的制造方法
US9621058B2 (en) * 2015-01-20 2017-04-11 Infineon Technologies Austria Ag Reducing switching losses associated with a synchronous rectification MOSFET
JP6441192B2 (ja) * 2015-09-11 2018-12-19 株式会社東芝 半導体装置
JP6032337B1 (ja) * 2015-09-28 2016-11-24 富士電機株式会社 半導体装置および半導体装置の製造方法
CN106601811B (zh) * 2015-10-19 2020-03-03 大中积体电路股份有限公司 沟槽式功率晶体管
CN105226090B (zh) * 2015-11-10 2018-07-13 株洲中车时代电气股份有限公司 一种绝缘栅双极晶体管及其制作方法
US10347724B2 (en) * 2015-12-07 2019-07-09 Mitsubishi Electric Corporation Silicon carbide semiconductor device
KR20170070505A (ko) 2015-12-14 2017-06-22 현대자동차주식회사 반도체 소자 및 그 제조 방법
JP6966844B2 (ja) * 2016-03-04 2021-11-17 ローム株式会社 半導体装置
US9947787B2 (en) * 2016-05-06 2018-04-17 Silicet, LLC Devices and methods for a power transistor having a schottky or schottky-like contact
KR102430498B1 (ko) 2016-06-28 2022-08-09 삼성전자주식회사 쇼트키 다이오드를 갖는 전자 소자
WO2018000357A1 (en) * 2016-06-30 2018-01-04 Texas Instruments Incorporated Power mosfet with metal filled deep sinker contact for csp
KR101836258B1 (ko) 2016-07-05 2018-03-08 현대자동차 주식회사 반도체 소자 및 그 제조 방법
JP6625938B2 (ja) * 2016-07-22 2019-12-25 株式会社東芝 半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び、昇降機
CN106206738B (zh) * 2016-08-22 2019-09-27 电子科技大学 一种积累型功率dmos器件
US9761712B1 (en) * 2016-10-31 2017-09-12 International Business Machines Corporation Vertical transistors with merged active area regions
CN106328647B (zh) * 2016-11-01 2019-05-03 华羿微电子股份有限公司 高速的沟槽mos器件及其制造方法
JP6872951B2 (ja) * 2017-03-30 2021-05-19 エイブリック株式会社 半導体装置及びその製造方法
JP6911486B2 (ja) * 2017-04-20 2021-07-28 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
US10396216B2 (en) 2017-05-03 2019-08-27 Semiconductor Components Industries, Llc Device including a sidewall Schottky interface
JP7059556B2 (ja) 2017-10-05 2022-04-26 富士電機株式会社 半導体装置
CN107895737A (zh) * 2017-11-30 2018-04-10 上海华虹宏力半导体制造有限公司 沟槽栅功率晶体管及其制造方法
JP6923457B2 (ja) * 2018-01-19 2021-08-18 株式会社日立製作所 炭化ケイ素半導体装置およびその製造方法、電力変換装置、自動車並びに鉄道車両
CN108447899A (zh) * 2018-02-09 2018-08-24 江苏如高第三代半导体产业研究院有限公司 一种垂直结构GaN功率器件的制备方法
US10797131B2 (en) * 2018-04-05 2020-10-06 Pakal Technologies, Inc. Enhancements to cell layout and fabrication techniques for MOS-gated devices
US10439075B1 (en) 2018-06-27 2019-10-08 Semiconductor Components Industries, Llc Termination structure for insulated gate semiconductor device and method
US10566466B2 (en) 2018-06-27 2020-02-18 Semiconductor Components Industries, Llc Termination structure for insulated gate semiconductor device and method
JP2020047726A (ja) * 2018-09-18 2020-03-26 トヨタ自動車株式会社 半導体装置
WO2021014570A1 (ja) * 2019-07-23 2021-01-28 三菱電機株式会社 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法
CN110416211A (zh) * 2019-07-24 2019-11-05 上海朕芯微电子科技有限公司 一种超自对准功率Trench MOSFET制作方法及结构
CN112992682A (zh) * 2019-12-13 2021-06-18 华润微电子（重庆）有限公司 沟槽型场效应晶体管结构及其制备方法
US11469313B2 (en) * 2020-01-16 2022-10-11 Ipower Semiconductor Self-aligned trench MOSFET and IGBT structures and methods of fabrication
CN113497123A (zh) * 2020-04-01 2021-10-12 成都蓉矽半导体有限公司 一种具有更快切换速度的分离绝缘栅双极晶体管
KR102426997B1 (ko) * 2020-12-30 2022-07-28 포항공과대학교 산학협력단 트리플 트렌치 구조를 구비하는 SiC 트랜지스터 및 그것의 제조 방법
KR102426998B1 (ko) * 2020-12-30 2022-07-28 포항공과대학교 산학협력단 트리플 트렌치 구조를 구비하는 Si 트랜지스터 및 그것의 제조 방법
CN113241374B (zh) * 2021-05-19 2023-07-14 深圳真茂佳半导体有限公司 功率晶体管结构及其制造方法
CN115394851B (zh) * 2022-06-24 2023-09-01 安世半导体科技(上海)有限公司 半导体器件及其制备方法
TWI823771B (zh) * 2022-12-08 2023-11-21 美商達爾科技股份有限公司 垂直式半導體功率器件及其製造方法
CN116364766A (zh) * 2023-02-17 2023-06-30 天狼芯半导体(成都)有限公司 半导体器件的制备方法、半导体器件和电子设备
CN116546815B (zh) * 2023-06-21 2023-11-24 长鑫存储技术有限公司 半导体结构及其形成方法

Family Cites Families (395)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3404295A (en) 1964-11-30 1968-10-01 Motorola Inc High frequency and voltage transistor with added region for punch-through protection
US3412297A (en) 1965-12-16 1968-11-19 United Aircraft Corp Mos field-effect transistor with a onemicron vertical channel
US3497777A (en) 1967-06-13 1970-02-24 Stanislas Teszner Multichannel field-effect semi-conductor device
US3564356A (en) 1968-10-24 1971-02-16 Tektronix Inc High voltage integrated circuit transistor
US3660697A (en) 1970-02-16 1972-05-02 Bell Telephone Labor Inc Monolithic semiconductor apparatus adapted for sequential charge transfer
US4003072A (en) 1972-04-20 1977-01-11 Sony Corporation Semiconductor device with high voltage breakdown resistance
US4011105A (en) 1975-09-15 1977-03-08 Mos Technology, Inc. Field inversion control for n-channel device integrated circuits
US4337474A (en) 1978-08-31 1982-06-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4698653A (en) 1979-10-09 1987-10-06 Cardwell Jr Walter T Semiconductor devices controlled by depletion regions
US4638344A (en) 1979-10-09 1987-01-20 Cardwell Jr Walter T Junction field-effect transistor controlled by merged depletion regions
US4338616A (en) * 1980-02-19 1982-07-06 Xerox Corporation Self-aligned Schottky metal semi-conductor field effect transistor with buried source and drain
US4345265A (en) 1980-04-14 1982-08-17 Supertex, Inc. MOS Power transistor with improved high-voltage capability
US4868624A (en) 1980-05-09 1989-09-19 Regents Of The University Of Minnesota Channel collector transistor
US4300150A (en) 1980-06-16 1981-11-10 North American Philips Corporation Lateral double-diffused MOS transistor device
US4326332A (en) 1980-07-28 1982-04-27 International Business Machines Corp. Method of making a high density V-MOS memory array
DE3070786D1 (en) 1980-11-12 1985-07-25 Ibm Deutschland Electrically switchable read-only memory
US4324038A (en) 1980-11-24 1982-04-13 Bell Telephone Laboratories, Incorporated Method of fabricating MOS field effect transistors
US4969028A (en) 1980-12-02 1990-11-06 General Electric Company Gate enhanced rectifier
GB2089119A (en) 1980-12-10 1982-06-16 Philips Electronic Associated High voltage semiconductor devices
US4983535A (en) * 1981-10-15 1991-01-08 Siliconix Incorporated Vertical DMOS transistor fabrication process
US4974059A (en) 1982-12-21 1990-11-27 International Rectifier Corporation Semiconductor high-power mosfet device
JPH0612828B2 (ja) * 1983-06-30 1994-02-16 株式会社東芝 半導体装置
JPS6016420A (ja) 1983-07-08 1985-01-28 Mitsubishi Electric Corp 選択的エピタキシヤル成長方法
US4639761A (en) 1983-12-16 1987-01-27 North American Philips Corporation Combined bipolar-field effect transistor resurf devices
US4568958A (en) 1984-01-03 1986-02-04 General Electric Company Inversion-mode insulated-gate gallium arsenide field-effect transistors
FR2566179B1 (fr) 1984-06-14 1986-08-22 Commissariat Energie Atomique Procede d'autopositionnement d'un oxyde de champ localise par rapport a une tranchee d'isolement
US5208657A (en) 1984-08-31 1993-05-04 Texas Instruments Incorporated DRAM Cell with trench capacitor and vertical channel in substrate
US4824793A (en) 1984-09-27 1989-04-25 Texas Instruments Incorporated Method of making DRAM cell with trench capacitor
US4694313A (en) 1985-02-19 1987-09-15 Harris Corporation Conductivity modulated semiconductor structure
US4673962A (en) 1985-03-21 1987-06-16 Texas Instruments Incorporated Vertical DRAM cell and method
US4774556A (en) 1985-07-25 1988-09-27 Nippondenso Co., Ltd. Non-volatile semiconductor memory device
US5262336A (en) 1986-03-21 1993-11-16 Advanced Power Technology, Inc. IGBT process to produce platinum lifetime control
US4767722A (en) 1986-03-24 1988-08-30 Siliconix Incorporated Method for making planar vertical channel DMOS structures
US5034785A (en) 1986-03-24 1991-07-23 Siliconix Incorporated Planar vertical channel DMOS structure
US4716126A (en) 1986-06-05 1987-12-29 Siliconix Incorporated Fabrication of double diffused metal oxide semiconductor transistor
US5607511A (en) 1992-02-21 1997-03-04 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US4746630A (en) 1986-09-17 1988-05-24 Hewlett-Packard Company Method for producing recessed field oxide with improved sidewall characteristics
US4941026A (en) 1986-12-05 1990-07-10 General Electric Company Semiconductor devices exhibiting minimum on-resistance
JP2577330B2 (ja) 1986-12-11 1997-01-29 新技術事業団 両面ゲ−ト静電誘導サイリスタの製造方法
US5105243A (en) 1987-02-26 1992-04-14 Kabushiki Kaisha Toshiba Conductivity-modulation metal oxide field effect transistor with single gate structure
US4821095A (en) 1987-03-12 1989-04-11 General Electric Company Insulated gate semiconductor device with extra short grid and method of fabrication
DE3787468T2 (de) 1987-03-25 1994-01-13 Komatsu Mfg Co Ltd Vorrichtung zur regelung des drucks einer hydraulischen kupplung.
US4745079A (en) 1987-03-30 1988-05-17 Motorola, Inc. Method for fabricating MOS transistors having gates with different work functions
US4801986A (en) 1987-04-03 1989-01-31 General Electric Company Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method
US4823176A (en) 1987-04-03 1989-04-18 General Electric Company Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area
US4799990A (en) * 1987-04-30 1989-01-24 Ibm Corporation Method of self-aligning a trench isolation structure to an implanted well region
JP2724146B2 (ja) * 1987-05-29 1998-03-09 日産自動車株式会社 縦形ｍｏｓｆｅｔ
US5164325A (en) 1987-10-08 1992-11-17 Siliconix Incorporated Method of making a vertical current flow field effect transistor
US4893160A (en) 1987-11-13 1990-01-09 Siliconix Incorporated Method for increasing the performance of trenched devices and the resulting structure
US4914058A (en) 1987-12-29 1990-04-03 Siliconix Incorporated Grooved DMOS process with varying gate dielectric thickness
EP0332822A1 (de) 1988-02-22 1989-09-20 Asea Brown Boveri Ag Feldeffektgesteuertes, bipolares Leistungshalbleiter-Bauelement sowie Verfahren zu seiner Herstellung
US4967245A (en) 1988-03-14 1990-10-30 Siliconix Incorporated Trench power MOSFET device
US5283201A (en) 1988-05-17 1994-02-01 Advanced Power Technology, Inc. High density power device fabrication process
KR0173111B1 (ko) 1988-06-02 1999-02-01 야마무라 가쯔미 트렌치 게이트 mos fet
US4961100A (en) 1988-06-20 1990-10-02 General Electric Company Bidirectional field effect semiconductor device and circuit
JPH0216763A (ja) 1988-07-05 1990-01-19 Toshiba Corp 半導体装置の製造方法
US4853345A (en) 1988-08-22 1989-08-01 Delco Electronics Corporation Process for manufacture of a vertical DMOS transistor
US5268311A (en) 1988-09-01 1993-12-07 International Business Machines Corporation Method for forming a thin dielectric layer on a substrate
US5156989A (en) 1988-11-08 1992-10-20 Siliconix, Incorporated Complementary, isolated DMOS IC technology
US5346834A (en) 1988-11-21 1994-09-13 Hitachi, Ltd. Method for manufacturing a semiconductor device and a semiconductor memory device
US5072266A (en) 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US5111253A (en) 1989-05-09 1992-05-05 General Electric Company Multicellular FET having a Schottky diode merged therewith
US4992390A (en) 1989-07-06 1991-02-12 General Electric Company Trench gate structure with thick bottom oxide
EP0450082B1 (en) 1989-08-31 2004-04-28 Denso Corporation Insulated gate bipolar transistor
US5248894A (en) 1989-10-03 1993-09-28 Harris Corporation Self-aligned channel stop for trench-isolated island
JP2893835B2 (ja) * 1990-04-06 1999-05-24 日産自動車株式会社 半導体装置の製造方法
US5023196A (en) 1990-01-29 1991-06-11 Motorola Inc. Method for forming a MOSFET with substrate source contact
US5134448A (en) 1990-01-29 1992-07-28 Motorola, Inc. MOSFET with substrate source contact
US5242845A (en) 1990-06-13 1993-09-07 Kabushiki Kaisha Toshiba Method of production of vertical MOS transistor
US5071782A (en) 1990-06-28 1991-12-10 Texas Instruments Incorporated Vertical memory cell array and method of fabrication
US5079608A (en) 1990-11-06 1992-01-07 Harris Corporation Power MOSFET transistor circuit with active clamp
EP0487022B1 (en) 1990-11-23 1997-04-23 Texas Instruments Incorporated A method of simultaneously fabricating an insulated gate-field-effect transistor and a bipolar transistor
US5065273A (en) 1990-12-04 1991-11-12 International Business Machines Corporation High capacity DRAM trench capacitor and methods of fabricating same
US5684320A (en) 1991-01-09 1997-11-04 Fujitsu Limited Semiconductor device having transistor pair
US5168331A (en) 1991-01-31 1992-12-01 Siliconix Incorporated Power metal-oxide-semiconductor field effect transistor
JP2825004B2 (ja) * 1991-02-08 1998-11-18 インターナショナル・ビジネス・マシーンズ・コーポレーション 側壁電荷結合撮像素子及びその製造方法
CN1019720B (zh) 1991-03-19 1992-12-30 电子科技大学 半导体功率器件
US5164802A (en) 1991-03-20 1992-11-17 Harris Corporation Power vdmosfet with schottky on lightly doped drain of lateral driver fet
US5250450A (en) 1991-04-08 1993-10-05 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
JP2603886B2 (ja) 1991-05-09 1997-04-23 日本電信電話株式会社 薄層ｓｏｉ型絶縁ゲート型電界効果トランジスタの製造方法
KR940002400B1 (ko) 1991-05-15 1994-03-24 금성일렉트론 주식회사 리세스 게이트를 갖는 반도체장치의 제조방법
US5219793A (en) 1991-06-03 1993-06-15 Motorola Inc. Method for forming pitch independent contacts and a semiconductor device having the same
KR940006702B1 (ko) 1991-06-14 1994-07-25 금성일렉트론 주식회사 모스패트의 제조방법
US5298761A (en) * 1991-06-17 1994-03-29 Nikon Corporation Method and apparatus for exposure process
JP2570022B2 (ja) 1991-09-20 1997-01-08 株式会社日立製作所 定電圧ダイオード及びそれを用いた電力変換装置並びに定電圧ダイオードの製造方法
JPH0590595A (ja) * 1991-09-27 1993-04-09 Nissan Motor Co Ltd 半導体装置
JPH0613627A (ja) 1991-10-08 1994-01-21 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US5300452A (en) 1991-12-18 1994-04-05 U.S. Philips Corporation Method of manufacturing an optoelectronic semiconductor device
JPH05198583A (ja) * 1992-01-22 1993-08-06 Toshiba Corp 横型金属ベーストランジスタ
JPH05304297A (ja) 1992-01-29 1993-11-16 Nec Corp 電力用半導体装置およびその製造方法
US5283452A (en) 1992-02-14 1994-02-01 Hughes Aircraft Company Distributed cell monolithic mircowave integrated circuit (MMIC) field-effect transistor (FET) amplifier
JPH05267674A (ja) * 1992-03-23 1993-10-15 Nissan Motor Co Ltd 半導体装置
US5315142A (en) 1992-03-23 1994-05-24 International Business Machines Corporation High performance trench EEPROM cell
JP2904635B2 (ja) 1992-03-30 1999-06-14 株式会社東芝 半導体装置およびその製造方法
US5554862A (en) 1992-03-31 1996-09-10 Kabushiki Kaisha Toshiba Power semiconductor device
JPH06196723A (ja) 1992-04-28 1994-07-15 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5640034A (en) 1992-05-18 1997-06-17 Texas Instruments Incorporated Top-drain trench based resurf DMOS transistor structure
US5233215A (en) 1992-06-08 1993-08-03 North Carolina State University At Raleigh Silicon carbide power MOSFET with floating field ring and floating field plate
US5430324A (en) * 1992-07-23 1995-07-04 Siliconix, Incorporated High voltage transistor having edge termination utilizing trench technology
US5910669A (en) 1992-07-24 1999-06-08 Siliconix Incorporated Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof
US5558313A (en) 1992-07-24 1996-09-24 Siliconix Inorporated Trench field effect transistor with reduced punch-through susceptibility and low RDSon
US5281548A (en) 1992-07-28 1994-01-25 Micron Technology, Inc. Plug-based floating gate memory
US5294824A (en) 1992-07-31 1994-03-15 Motorola, Inc. High voltage transistor having reduced on-resistance
GB9216599D0 (en) 1992-08-05 1992-09-16 Philips Electronics Uk Ltd A semiconductor device comprising a vertical insulated gate field effect device and a method of manufacturing such a device
US5300447A (en) 1992-09-29 1994-04-05 Texas Instruments Incorporated Method of manufacturing a minimum scaled transistor
JPH06163907A (ja) 1992-11-20 1994-06-10 Hitachi Ltd 電圧駆動型半導体装置
US5275965A (en) 1992-11-25 1994-01-04 Micron Semiconductor, Inc. Trench isolation using gated sidewalls
US5326711A (en) 1993-01-04 1994-07-05 Texas Instruments Incorporated High performance high voltage vertical transistor and method of fabrication
DE4300806C1 (de) 1993-01-14 1993-12-23 Siemens Ag Verfahren zur Herstellung von vertikalen MOS-Transistoren
US5418376A (en) 1993-03-02 1995-05-23 Toyo Denki Seizo Kabushiki Kaisha Static induction semiconductor device with a distributed main electrode structure and static induction semiconductor device with a static induction main electrode shorted structure
US5341011A (en) 1993-03-15 1994-08-23 Siliconix Incorporated Short channel trenched DMOS transistor
DE4309764C2 (de) 1993-03-25 1997-01-30 Siemens Ag Leistungs-MOSFET
GB9306895D0 (en) 1993-04-01 1993-05-26 Philips Electronics Uk Ltd A method of manufacturing a semiconductor device comprising an insulated gate field effect device
KR960012585B1 (en) 1993-06-25 1996-09-23 Samsung Electronics Co Ltd Transistor structure and the method for manufacturing the same
US5349224A (en) 1993-06-30 1994-09-20 Purdue Research Foundation Integrable MOS and IGBT devices having trench gate structure
US5371396A (en) 1993-07-02 1994-12-06 Thunderbird Technologies, Inc. Field effect transistor having polycrystalline silicon gate junction
US5365102A (en) 1993-07-06 1994-11-15 North Carolina State University Schottky barrier rectifier with MOS trench
BE1007283A3 (nl) 1993-07-12 1995-05-09 Philips Electronics Nv Halfgeleiderinrichting met een most voorzien van een extended draingebied voor hoge spanningen.
JPH07122749A (ja) 1993-09-01 1995-05-12 Toshiba Corp 半導体装置及びその製造方法
JP3400846B2 (ja) 1994-01-20 2003-04-28 三菱電機株式会社 トレンチ構造を有する半導体装置およびその製造方法
US5429977A (en) 1994-03-11 1995-07-04 Industrial Technology Research Institute Method for forming a vertical transistor with a stacked capacitor DRAM cell
US5434435A (en) 1994-05-04 1995-07-18 North Carolina State University Trench gate lateral MOSFET
DE4417150C2 (de) * 1994-05-17 1996-03-14 Siemens Ag Verfahren zur Herstellung einer Anordnung mit selbstverstärkenden dynamischen MOS-Transistorspeicherzellen
US5405794A (en) 1994-06-14 1995-04-11 Philips Electronics North America Corporation Method of producing VDMOS device of increased power density
JPH0823093A (ja) * 1994-07-08 1996-01-23 Nissan Motor Co Ltd 半導体装置およびその製造方法
US5424231A (en) 1994-08-09 1995-06-13 United Microelectronics Corp. Method for manufacturing a VDMOS transistor
US5583368A (en) * 1994-08-11 1996-12-10 International Business Machines Corporation Stacked devices
DE69525003T2 (de) 1994-08-15 2003-10-09 Siliconix Inc Verfahren zum Herstellen eines DMOS-Transistors mit Grabenstruktur unter Verwendung von sieben Masken
US5581100A (en) 1994-08-30 1996-12-03 International Rectifier Corporation Trench depletion MOSFET
JP3708998B2 (ja) 1994-11-04 2005-10-19 シーメンス アクチエンゲゼルシヤフト 電界効果により制御可能の半導体デバイスの製造方法
US5583065A (en) 1994-11-23 1996-12-10 Sony Corporation Method of making a MOS semiconductor device
US5674766A (en) 1994-12-30 1997-10-07 Siliconix Incorporated Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer
US6008520A (en) 1994-12-30 1999-12-28 Siliconix Incorporated Trench MOSFET with heavily doped delta layer to provide low on- resistance
US5597765A (en) * 1995-01-10 1997-01-28 Siliconix Incorporated Method for making termination structure for power MOSFET
JPH08204179A (ja) * 1995-01-26 1996-08-09 Fuji Electric Co Ltd 炭化ケイ素トレンチｍｏｓｆｅｔ
US5670803A (en) 1995-02-08 1997-09-23 International Business Machines Corporation Three-dimensional SRAM trench structure and fabrication method therefor
JP3325736B2 (ja) 1995-02-09 2002-09-17 三菱電機株式会社 絶縁ゲート型半導体装置
DE69602114T2 (de) 1995-02-10 1999-08-19 Siliconix Inc Graben-Feldeffekttransistor mit PN-Verarmungsschicht-Barriere
JP3291957B2 (ja) 1995-02-17 2002-06-17 富士電機株式会社 縦型トレンチｍｉｓｆｅｔおよびその製造方法
US5595927A (en) * 1995-03-17 1997-01-21 Taiwan Semiconductor Manufacturing Company Ltd. Method for making self-aligned source/drain mask ROM memory cell using trench etched channel
US5592005A (en) 1995-03-31 1997-01-07 Siliconix Incorporated Punch-through field effect transistor
US5554552A (en) 1995-04-03 1996-09-10 Taiwan Semiconductor Manufacturing Company PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof
US5744372A (en) 1995-04-12 1998-04-28 National Semiconductor Corporation Fabrication of complementary field-effect transistors each having multi-part channel
JPH08306914A (ja) * 1995-04-27 1996-11-22 Nippondenso Co Ltd 半導体装置およびその製造方法
US5567634A (en) 1995-05-01 1996-10-22 National Semiconductor Corporation Method of fabricating self-aligned contact trench DMOS transistors
KR0143459B1 (ko) 1995-05-22 1998-07-01 한민구 모오스 게이트형 전력 트랜지스터
US6140678A (en) 1995-06-02 2000-10-31 Siliconix Incorporated Trench-gated power MOSFET with protective diode
US6049108A (en) 1995-06-02 2000-04-11 Siliconix Incorporated Trench-gated MOSFET with bidirectional voltage clamping
US5648670A (en) * 1995-06-07 1997-07-15 Sgs-Thomson Microelectronics, Inc. Trench MOS-gated device with a minimum number of masks
GB9512089D0 (en) 1995-06-14 1995-08-09 Evans Jonathan L Semiconductor device fabrication
US5689128A (en) 1995-08-21 1997-11-18 Siliconix Incorporated High density trenched DMOS transistor
US5629543A (en) 1995-08-21 1997-05-13 Siliconix Incorporated Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness
FR2738394B1 (fr) 1995-09-06 1998-06-26 Nippon Denso Co Dispositif a semi-conducteur en carbure de silicium, et son procede de fabrication
US5847464A (en) 1995-09-27 1998-12-08 Sgs-Thomson Microelectronics, Inc. Method for forming controlled voids in interlevel dielectric
US5705409A (en) * 1995-09-28 1998-01-06 Motorola Inc. Method for forming trench transistor structure
US5879971A (en) * 1995-09-28 1999-03-09 Motorola Inc. Trench random access memory cell and method of formation
US5679966A (en) * 1995-10-05 1997-10-21 North Carolina State University Depleted base transistor with high forward voltage blocking capability
US5616945A (en) 1995-10-13 1997-04-01 Siliconix Incorporated Multiple gated MOSFET for use in DC-DC converter
US5973367A (en) 1995-10-13 1999-10-26 Siliconix Incorporated Multiple gated MOSFET for use in DC-DC converter
US5949124A (en) 1995-10-31 1999-09-07 Motorola, Inc. Edge termination structure
US6037632A (en) * 1995-11-06 2000-03-14 Kabushiki Kaisha Toshiba Semiconductor device
KR0159075B1 (ko) 1995-11-11 1998-12-01 김광호 트렌치 dmos장치 및 그의 제조방법
US5721148A (en) * 1995-12-07 1998-02-24 Fuji Electric Co. Method for manufacturing MOS type semiconductor device
US5780343A (en) 1995-12-20 1998-07-14 National Semiconductor Corporation Method of producing high quality silicon surface for selective epitaxial growth of silicon
US5637898A (en) 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
US6097063A (en) 1996-01-22 2000-08-01 Fuji Electric Co., Ltd. Semiconductor device having a plurality of parallel drift regions
DE59711481D1 (de) * 1996-02-05 2004-05-06 Infineon Technologies Ag Durch Feldeffekt steuerbares Halbleiterbauelement
US5868624A (en) * 1996-02-09 1999-02-09 Exedy Corporation Flex plate and flywheel configuration
US6084268A (en) 1996-03-05 2000-07-04 Semiconductor Components Industries, Llc Power MOSFET device having low on-resistance and method
US5821583A (en) 1996-03-06 1998-10-13 Siliconix Incorporated Trenched DMOS transistor with lightly doped tub
US5814858A (en) 1996-03-15 1998-09-29 Siliconix Incorporated Vertical power MOSFET having reduced sensitivity to variations in thickness of epitaxial layer
DE19611045C1 (de) 1996-03-20 1997-05-22 Siemens Ag Durch Feldeffekt steuerbares Halbleiterbauelement
DE69630944D1 (de) 1996-03-29 2004-01-15 St Microelectronics Srl Hochspannungsfester MOS-Transistor und Verfahren zur Herstellung
US5895951A (en) 1996-04-05 1999-04-20 Megamos Corporation MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches
US5770878A (en) 1996-04-10 1998-06-23 Harris Corporation Trench MOS gate device
US5767004A (en) 1996-04-22 1998-06-16 Chartered Semiconductor Manufacturing, Ltd. Method for forming a low impurity diffusion polysilicon layer
US5719409A (en) * 1996-06-06 1998-02-17 Cree Research, Inc. Silicon carbide metal-insulator semiconductor field effect transistor
AU3724197A (en) 1996-07-19 1998-02-10 Siliconix Incorporated High density trench dmos transistor with trench bottom implant
US5808340A (en) 1996-09-18 1998-09-15 Advanced Micro Devices, Inc. Short channel self aligned VMOS field effect transistor
DE19638438A1 (de) 1996-09-19 1998-04-02 Siemens Ag Durch Feldeffekt steuerbares, vertikales Halbleiterbauelement
DE19638439C2 (de) 1996-09-19 2000-06-15 Siemens Ag Durch Feldeffekt steuerbares, vertikales Halbleiterbauelement und Herstellungsverfahren
JP2891205B2 (ja) 1996-10-21 1999-05-17 日本電気株式会社 半導体集積回路の製造方法
US5972741A (en) 1996-10-31 1999-10-26 Sanyo Electric Co., Ltd. Method of manufacturing semiconductor device
JP3397057B2 (ja) 1996-11-01 2003-04-14 日産自動車株式会社 半導体装置
US6207994B1 (en) * 1996-11-05 2001-03-27 Power Integrations, Inc. High-voltage transistor with multi-layer conduction region
US6168983B1 (en) * 1996-11-05 2001-01-02 Power Integrations, Inc. Method of making a high-voltage transistor with multiple lateral conduction layers
KR100233832B1 (ko) 1996-12-14 1999-12-01 정선종 반도체 소자의 트랜지스터 및 그 제조방법
US6011298A (en) * 1996-12-31 2000-01-04 Stmicroelectronics, Inc. High voltage termination with buried field-shaping region
JPH10256550A (ja) 1997-01-09 1998-09-25 Toshiba Corp 半導体装置
KR100218260B1 (ko) 1997-01-14 1999-09-01 김덕중 트랜치 게이트형 모스트랜지스터의 제조방법
JP3938964B2 (ja) 1997-02-10 2007-06-27 三菱電機株式会社 高耐圧半導体装置およびその製造方法
US5877528A (en) * 1997-03-03 1999-03-02 Megamos Corporation Structure to provide effective channel-stop in termination areas for trenched power transistors
US6057558A (en) 1997-03-05 2000-05-02 Denson Corporation Silicon carbide semiconductor device and manufacturing method thereof
US5981354A (en) 1997-03-12 1999-11-09 Advanced Micro Devices, Inc. Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process
KR100225409B1 (ko) * 1997-03-27 1999-10-15 김덕중 트렌치 디-모오스 및 그의 제조 방법
US6163052A (en) 1997-04-04 2000-12-19 Advanced Micro Devices, Inc. Trench-gated vertical combination JFET and MOSFET devices
US5879994A (en) * 1997-04-15 1999-03-09 National Semiconductor Corporation Self-aligned method of fabricating terrace gate DMOS transistor
US6281547B1 (en) 1997-05-08 2001-08-28 Megamos Corporation Power transistor cells provided with reliable trenched source contacts connected to narrower source manufactured without a source mask
JPH113936A (ja) 1997-06-13 1999-01-06 Nec Corp 半導体装置の製造方法
JP3618517B2 (ja) 1997-06-18 2005-02-09 三菱電機株式会社 半導体装置およびその製造方法
US6110799A (en) 1997-06-30 2000-08-29 Intersil Corporation Trench contact process
US6096608A (en) 1997-06-30 2000-08-01 Siliconix Incorporated Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench
US6037628A (en) * 1997-06-30 2000-03-14 Intersil Corporation Semiconductor structures with trench contacts
US5907776A (en) 1997-07-11 1999-05-25 Magepower Semiconductor Corp. Method of forming a semiconductor structure having reduced threshold voltage and high punch-through tolerance
DE19731495C2 (de) 1997-07-22 1999-05-20 Siemens Ag Durch Feldeffekt steuerbarer Bipolartransistor und Verfahren zu seiner Herstellung
US5801082A (en) 1997-08-18 1998-09-01 Vanguard International Semiconductor Corporation Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits
JP3502531B2 (ja) * 1997-08-28 2004-03-02 株式会社ルネサステクノロジ 半導体装置の製造方法
US6239463B1 (en) 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
DE19740195C2 (de) * 1997-09-12 1999-12-02 Siemens Ag Halbleiterbauelement mit Metall-Halbleiterübergang mit niedrigem Sperrstrom
DE19743342C2 (de) 1997-09-30 2002-02-28 Infineon Technologies Ag Feldeffekttransistor hoher Packungsdichte und Verfahren zu seiner Herstellung
US5776813A (en) 1997-10-06 1998-07-07 Industrial Technology Research Institute Process to manufacture a vertical gate-enhanced bipolar transistor
US6121089A (en) 1997-10-17 2000-09-19 Intersil Corporation Methods of forming power semiconductor devices having merged split-well body regions therein
KR100249505B1 (ko) 1997-10-28 2000-03-15 정선종 수평형 이중 확산 전력 소자의 제조 방법
US6337499B1 (en) * 1997-11-03 2002-01-08 Infineon Technologies Ag Semiconductor component
US5943581A (en) 1997-11-05 1999-08-24 Vanguard International Semiconductor Corporation Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits
US6005271A (en) 1997-11-05 1999-12-21 Magepower Semiconductor Corp. Semiconductor cell array with high packing density
GB9723468D0 (en) 1997-11-07 1998-01-07 Zetex Plc Method of semiconductor device fabrication
US6081009A (en) 1997-11-10 2000-06-27 Intersil Corporation High voltage mosfet structure
US6429481B1 (en) 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
US6426260B1 (en) 1997-12-02 2002-07-30 Magepower Semiconductor Corp. Switching speed improvement in DMO by implanting lightly doped region under gate
JPH11204782A (ja) 1998-01-08 1999-07-30 Toshiba Corp 半導体装置およびその製造方法
KR100333797B1 (ko) 1998-01-22 2002-04-26 다니구찌 이찌로오, 기타오카 다카시 절연 게이트형 바이폴라 반도체 장치
US6396102B1 (en) 1998-01-27 2002-05-28 Fairchild Semiconductor Corporation Field coupled power MOSFET bus architecture using trench technology
US5900663A (en) 1998-02-07 1999-05-04 Xemod, Inc. Quasi-mesh gate structure for lateral RF MOS devices
US5949104A (en) * 1998-02-07 1999-09-07 Xemod, Inc. Source connection structure for lateral RF MOS devices
GB9826291D0 (en) 1998-12-02 1999-01-20 Koninkl Philips Electronics Nv Field-effect semi-conductor devices
DE19808348C1 (de) 1998-02-27 1999-06-24 Siemens Ag Durch Feldeffekt steuerbares Halbleiterbauelement
JP3641547B2 (ja) 1998-03-25 2005-04-20 株式会社豊田中央研究所 横型ｍｏｓ素子を含む半導体装置
US5897343A (en) 1998-03-30 1999-04-27 Motorola, Inc. Method of making a power switching trench MOSFET having aligned source regions
EP0996981A1 (de) 1998-04-08 2000-05-03 Siemens Aktiengesellschaft Hochvolt-randabschluss für planarstrukturen
US5945724A (en) * 1998-04-09 1999-08-31 Micron Technology, Inc. Trench isolation region for semiconductor device
US6137152A (en) 1998-04-22 2000-10-24 Texas Instruments - Acer Incorporated Planarized deep-shallow trench isolation for CMOS/bipolar devices
US6262453B1 (en) 1998-04-24 2001-07-17 Magepower Semiconductor Corp. Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate
US6150697A (en) 1998-04-30 2000-11-21 Denso Corporation Semiconductor apparatus having high withstand voltage
US6303969B1 (en) 1998-05-01 2001-10-16 Allen Tan Schottky diode with dielectric trench
US6063678A (en) 1998-05-04 2000-05-16 Xemod, Inc. Fabrication of lateral RF MOS devices with enhanced RF properties
US6048772A (en) * 1998-05-04 2000-04-11 Xemod, Inc. Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection
DE19820223C1 (de) * 1998-05-06 1999-11-04 Siemens Ag Verfahren zum Herstellen einer Epitaxieschicht mit lateral veränderlicher Dotierung
US6104054A (en) 1998-05-13 2000-08-15 Texas Instruments Incorporated Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies
US6146970A (en) * 1998-05-26 2000-11-14 Motorola Inc. Capped shallow trench isolation and method of formation
US6015727A (en) * 1998-06-08 2000-01-18 Wanlass; Frank M. Damascene formation of borderless contact MOS transistors
US6064088A (en) 1998-06-15 2000-05-16 Xemod, Inc. RF power MOSFET device with extended linear region of transconductance characteristic at low drain current
DE19828191C1 (de) 1998-06-24 1999-07-29 Siemens Ag Lateral-Hochspannungstransistor
KR100372103B1 (ko) 1998-06-30 2003-03-31 주식회사 하이닉스반도체 반도체소자의소자분리방법
GB9815021D0 (en) * 1998-07-11 1998-09-09 Koninkl Philips Electronics Nv Semiconductor power device manufacture
US6054365A (en) 1998-07-13 2000-04-25 International Rectifier Corp. Process for filling deep trenches with polysilicon and oxide
US6156611A (en) 1998-07-20 2000-12-05 Motorola, Inc. Method of fabricating vertical FET with sidewall gate electrode
EP1026749B1 (en) 1998-07-23 2003-09-17 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device and semiconductor device obtainable thereby
JP3988262B2 (ja) 1998-07-24 2007-10-10 富士電機デバイステクノロジー株式会社 縦型超接合半導体素子およびその製造方法
JP4253374B2 (ja) 1998-07-24 2009-04-08 千住金属工業株式会社 プリント基板のはんだ付け方法および噴流はんだ槽
DE19839970C2 (de) 1998-09-02 2000-11-02 Siemens Ag Randstruktur und Driftbereich für ein Halbleiterbauelement sowie Verfahren zu ihrer Herstellung
US6429581B1 (en) 1998-09-10 2002-08-06 Corning Incorporated TIR lens for uniform brightness
DE19841754A1 (de) 1998-09-11 2000-03-30 Siemens Ag Schalttransistor mit reduzierten Schaltverlusten
JP3382163B2 (ja) 1998-10-07 2003-03-04 株式会社東芝 電力用半導体装置
US7462910B1 (en) 1998-10-14 2008-12-09 International Rectifier Corporation P-channel trench MOSFET structure
DE19848828C2 (de) * 1998-10-22 2001-09-13 Infineon Technologies Ag Halbleiterbauelement mit kleiner Durchlaßspannung und hoher Sperrfähigkeit
US5998833A (en) 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
US6545316B1 (en) 2000-06-23 2003-04-08 Silicon Wireless Corporation MOSFET devices having linear transfer characteristics when operating in velocity saturation mode and methods of forming and operating same
US6194741B1 (en) * 1998-11-03 2001-02-27 International Rectifier Corp. MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance
JP3951522B2 (ja) 1998-11-11 2007-08-01 富士電機デバイステクノロジー株式会社 超接合半導体素子
US6291856B1 (en) 1998-11-12 2001-09-18 Fuji Electric Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
JP3799888B2 (ja) 1998-11-12 2006-07-19 富士電機デバイステクノロジー株式会社 超接合半導体素子およびその製造方法
US6156606A (en) 1998-11-17 2000-12-05 Siemens Aktiengesellschaft Method of forming a trench capacitor using a rutile dielectric material
JP2000156978A (ja) 1998-11-17 2000-06-06 Fuji Electric Co Ltd ソフトスイッチング回路
US6084264A (en) 1998-11-25 2000-07-04 Siliconix Incorporated Trench MOSFET having improved breakdown and on-resistance characteristics
DE19854915C2 (de) * 1998-11-27 2002-09-05 Infineon Technologies Ag MOS-Feldeffekttransistor mit Hilfselektrode
GB9826041D0 (en) 1998-11-28 1999-01-20 Koninkl Philips Electronics Nv Trench-gate semiconductor devices and their manufacture
US6452230B1 (en) 1998-12-23 2002-09-17 International Rectifier Corporation High voltage mosgated device with trenches to reduce on-resistance
US6222229B1 (en) 1999-02-18 2001-04-24 Cree, Inc. Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability
US6351018B1 (en) * 1999-02-26 2002-02-26 Fairchild Semiconductor Corporation Monolithically integrated trench MOSFET and Schottky diode
US6204097B1 (en) * 1999-03-01 2001-03-20 Semiconductor Components Industries, Llc Semiconductor device and method of manufacture
JP3751463B2 (ja) 1999-03-23 2006-03-01 株式会社東芝 高耐圧半導体素子
DE19913375B4 (de) 1999-03-24 2009-03-26 Infineon Technologies Ag Verfahren zur Herstellung einer MOS-Transistorstruktur
JP3417336B2 (ja) 1999-03-25 2003-06-16 関西日本電気株式会社 絶縁ゲート型半導体装置およびその製造方法
US6316806B1 (en) 1999-03-31 2001-11-13 Fairfield Semiconductor Corporation Trench transistor with a self-aligned source
US6188105B1 (en) * 1999-04-01 2001-02-13 Intersil Corporation High density MOS-gated power device and process for forming same
US6413822B2 (en) 1999-04-22 2002-07-02 Advanced Analogic Technologies, Inc. Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer
TW425701B (en) * 1999-04-27 2001-03-11 Taiwan Semiconductor Mfg Manufacturing method of stack-type capacitor
WO2000068997A1 (en) 1999-05-06 2000-11-16 C.P. Clare Corporation Mosfet with field reducing trenches in body region
WO2000068998A1 (en) 1999-05-06 2000-11-16 C.P. Clare Corporation High voltage mosfet structures
US6313482B1 (en) 1999-05-17 2001-11-06 North Carolina State University Silicon carbide power devices having trench-based silicon carbide charge coupling regions therein
US6433385B1 (en) 1999-05-19 2002-08-13 Fairchild Semiconductor Corporation MOS-gated power device having segmented trench and extended doping zone and process for forming same
US6198127B1 (en) 1999-05-19 2001-03-06 Intersil Corporation MOS-gated power device having extended trench and doping zone and process for forming same
US6373098B1 (en) 1999-05-25 2002-04-16 Fairchild Semiconductor Corporation Trench-gated device having trench walls formed by selective epitaxial growth and process for forming device
US6291298B1 (en) 1999-05-25 2001-09-18 Advanced Analogic Technologies, Inc. Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses
US6191447B1 (en) 1999-05-28 2001-02-20 Micro-Ohm Corporation Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same
DE69938541D1 (de) 1999-06-03 2008-05-29 St Microelectronics Srl Leistungshalbleiteranordnung mit einer Randabschlussstruktur mit einem Spannungsteiler
KR100773380B1 (ko) 1999-06-03 2007-11-06 제네럴 세미컨덕터, 인코포레이티드 전력 ｍｏｓｆｅｔ, 이를 형성하는 방법, 및 이 방법에 의해 형성되는 다른 전력 ｍｏｓｆｅｔ
DE50015742D1 (de) * 1999-06-25 2009-10-29 Infineon Technologies Ag Trench-mos-transistor
JP3851744B2 (ja) 1999-06-28 2006-11-29 株式会社東芝 半導体装置の製造方法
US6274905B1 (en) 1999-06-30 2001-08-14 Fairchild Semiconductor Corporation Trench structure substantially filled with high-conductivity material
GB9916370D0 (en) 1999-07-14 1999-09-15 Koninkl Philips Electronics Nv Manufacture of semiconductor devices and material
GB9916520D0 (en) 1999-07-15 1999-09-15 Koninkl Philips Electronics Nv Manufacture of semiconductor devices and material
GB9917099D0 (en) * 1999-07-22 1999-09-22 Koninkl Philips Electronics Nv Cellular trench-gate field-effect transistors
JP3971062B2 (ja) * 1999-07-29 2007-09-05 株式会社東芝 高耐圧半導体装置
TW411553B (en) 1999-08-04 2000-11-11 Mosel Vitelic Inc Method for forming curved oxide on bottom of trench
JP4774580B2 (ja) 1999-08-23 2011-09-14 富士電機株式会社 超接合半導体素子
US6077733A (en) 1999-09-03 2000-06-20 Taiwan Semiconductor Manufacturing Company Method of manufacturing self-aligned T-shaped gate through dual damascene
US6566804B1 (en) 1999-09-07 2003-05-20 Motorola, Inc. Field emission device and method of operation
US20030060013A1 (en) * 1999-09-24 2003-03-27 Bruce D. Marchant Method of manufacturing trench field effect transistors with trenched heavy body
US6228727B1 (en) 1999-09-27 2001-05-08 Chartered Semiconductor Manufacturing, Ltd. Method to form shallow trench isolations with rounded corners and reduced trench oxide recess
GB9922764D0 (en) 1999-09-28 1999-11-24 Koninkl Philips Electronics Nv Manufacture of trench-gate semiconductor devices
JP3507732B2 (ja) 1999-09-30 2004-03-15 株式会社東芝 半導体装置
US6271552B1 (en) 1999-10-04 2001-08-07 Xemod, Inc Lateral RF MOS device with improved breakdown voltage
US6222233B1 (en) 1999-10-04 2001-04-24 Xemod, Inc. Lateral RF MOS device with improved drain structure
US6103619A (en) 1999-10-08 2000-08-15 United Microelectronics Corp. Method of forming a dual damascene structure on a semiconductor wafer
JP4450122B2 (ja) 1999-11-17 2010-04-14 株式会社デンソー 炭化珪素半導体装置
US6184092B1 (en) * 1999-11-23 2001-02-06 Mosel Vitelic Inc. Self-aligned contact for trench DMOS transistors
GB9928285D0 (en) * 1999-11-30 2000-01-26 Koninkl Philips Electronics Nv Manufacture of trench-gate semiconductor devices
GB9929613D0 (en) 1999-12-15 2000-02-09 Koninkl Philips Electronics Nv Manufacture of semiconductor material and devices using that material
US20030235936A1 (en) * 1999-12-16 2003-12-25 Snyder John P. Schottky barrier CMOS device and method
US6461918B1 (en) 1999-12-20 2002-10-08 Fairchild Semiconductor Corporation Power MOS device with improved gate charge performance
US6285060B1 (en) 1999-12-30 2001-09-04 Siliconix Incorporated Barrier accumulation-mode MOSFET
US6346469B1 (en) * 2000-01-03 2002-02-12 Motorola, Inc. Semiconductor device and a process for forming the semiconductor device
GB0002235D0 (en) 2000-02-02 2000-03-22 Koninkl Philips Electronics Nv Trenched schottky rectifiers
JP4765012B2 (ja) * 2000-02-09 2011-09-07 富士電機株式会社 半導体装置及びその製造方法
US6376878B1 (en) 2000-02-11 2002-04-23 Fairchild Semiconductor Corporation MOS-gated devices with alternating zones of conductivity
GB0003185D0 (en) 2000-02-12 2000-04-05 Koninkl Philips Electronics Nv An insulated gate field effect device
GB0003184D0 (en) 2000-02-12 2000-04-05 Koninkl Philips Electronics Nv A semiconductor device and a method of fabricating material for a semiconductor device
US6271100B1 (en) 2000-02-24 2001-08-07 International Business Machines Corporation Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield
JP2001244461A (ja) 2000-02-28 2001-09-07 Toyota Central Res & Dev Lab Inc 縦型半導体装置
GB0005650D0 (en) 2000-03-10 2000-05-03 Koninkl Philips Electronics Nv Field-effect semiconductor devices
US6246090B1 (en) 2000-03-14 2001-06-12 Intersil Corporation Power trench transistor device source region formation using silicon spacer
KR100766874B1 (ko) * 2000-03-17 2007-10-15 제네럴 세미컨덕터, 인코포레이티드 트렌치 ｄｍｏｓ를 형성하는 방법과, 이러한 ｄｍｏｓ 트랜지스터 셀과, 이러한 트랜지스터 구조
TW439176B (en) 2000-03-17 2001-06-07 United Microelectronics Corp Manufacturing method of capacitors
JP3636345B2 (ja) * 2000-03-17 2005-04-06 富士電機デバイステクノロジー株式会社 半導体素子および半導体素子の製造方法
GB0006957D0 (en) 2000-03-23 2000-05-10 Koninkl Philips Electronics Nv A semiconductor device
US6376315B1 (en) 2000-03-31 2002-04-23 General Semiconductor, Inc. Method of forming a trench DMOS having reduced threshold voltage
US6580123B2 (en) * 2000-04-04 2003-06-17 International Rectifier Corporation Low voltage power MOSFET device and process for its manufacture
US6392290B1 (en) 2000-04-07 2002-05-21 Siliconix Incorporated Vertical structure for semiconductor wafer-level chip scale packages
JP4534303B2 (ja) * 2000-04-27 2010-09-01 富士電機システムズ株式会社 横型超接合半導体素子
JP4240752B2 (ja) 2000-05-01 2009-03-18 富士電機デバイステクノロジー株式会社 半導体装置
US6509240B2 (en) * 2000-05-15 2003-01-21 International Rectifier Corporation Angle implant process for cellular deep trench sidewall doping
DE10026924A1 (de) 2000-05-30 2001-12-20 Infineon Technologies Ag Kompensationsbauelement
US6627949B2 (en) * 2000-06-02 2003-09-30 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
US6479352B2 (en) 2000-06-02 2002-11-12 General Semiconductor, Inc. Method of fabricating high voltage power MOSFET having low on-resistance
JP3773755B2 (ja) * 2000-06-02 2006-05-10 セイコーインスツル株式会社 縦形ｍｏｓトランジスタ及びその製造方法
US6635534B2 (en) * 2000-06-05 2003-10-21 Fairchild Semiconductor Corporation Method of manufacturing a trench MOSFET using selective growth epitaxy
EP1170803A3 (en) * 2000-06-08 2002-10-09 Siliconix Incorporated Trench gate MOSFET and method of making the same
US6472678B1 (en) 2000-06-16 2002-10-29 General Semiconductor, Inc. Trench MOSFET with double-diffused body profile
JP4984345B2 (ja) 2000-06-21 2012-07-25 富士電機株式会社 半導体装置
JP4528460B2 (ja) * 2000-06-30 2010-08-18 株式会社東芝 半導体素子
JP3833903B2 (ja) * 2000-07-11 2006-10-18 株式会社東芝 半導体装置の製造方法
US6555895B1 (en) 2000-07-17 2003-04-29 General Semiconductor, Inc. Devices and methods for addressing optical edge effects in connection with etched trenches
US6921939B2 (en) * 2000-07-20 2005-07-26 Fairchild Semiconductor Corporation Power MOSFET and method for forming same using a self-aligned body implant
US6445035B1 (en) * 2000-07-24 2002-09-03 Fairchild Semiconductor Corporation Power MOS device with buried gate and groove
JP2002043571A (ja) * 2000-07-28 2002-02-08 Nec Kansai Ltd 半導体装置
US6472708B1 (en) 2000-08-31 2002-10-29 General Semiconductor, Inc. Trench MOSFET with structure having low gate charge
EP1205980A1 (en) 2000-11-07 2002-05-15 Infineon Technologies AG A method for forming a field effect transistor in a semiconductor substrate
US6362112B1 (en) * 2000-11-08 2002-03-26 Fabtech, Inc. Single step etched moat
US6608350B2 (en) * 2000-12-07 2003-08-19 International Rectifier Corporation High voltage vertical conduction superjunction semiconductor device
US6781195B2 (en) * 2001-01-23 2004-08-24 Semiconductor Components Industries, L.L.C. Semiconductor bidirectional switching device and method
US6713813B2 (en) * 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure
US6677641B2 (en) * 2001-10-17 2004-01-13 Fairchild Semiconductor Corporation Semiconductor structure with improved smaller forward voltage loss and higher blocking capability
US6916745B2 (en) * 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6870220B2 (en) * 2002-08-23 2005-03-22 Fairchild Semiconductor Corporation Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses
JP4932088B2 (ja) * 2001-02-19 2012-05-16 ルネサスエレクトロニクス株式会社 絶縁ゲート型半導体装置の製造方法
KR100485297B1 (ko) * 2001-02-21 2005-04-27 미쓰비시덴키 가부시키가이샤 반도체 장치 및 그 제조 방법
US6683346B2 (en) * 2001-03-09 2004-01-27 Fairchild Semiconductor Corporation Ultra dense trench-gated power-device with the reduced drain-source feedback capacitance and Miller charge
KR100393201B1 (ko) * 2001-04-16 2003-07-31 페어차일드코리아반도체 주식회사 낮은 온 저항과 높은 브레이크다운 전압을 갖는 고전압수평형 디모스 트랜지스터
US6892098B2 (en) * 2001-04-26 2005-05-10 Biocontrol Medical Ltd. Nerve stimulation for treating spasticity, tremor, muscle weakness, and other motor disorders
US6998678B2 (en) 2001-05-17 2006-02-14 Infineon Technologies Ag Semiconductor arrangement with a MOS-transistor and a parallel Schottky-diode
DE10214160B4 (de) * 2002-03-28 2014-10-09 Infineon Technologies Ag Halbleiteranordnung mit Schottky-Kontakt
DE10127885B4 (de) * 2001-06-08 2009-09-24 Infineon Technologies Ag Trench-Leistungshalbleiterbauelement
US7033876B2 (en) * 2001-07-03 2006-04-25 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same
US6621107B2 (en) * 2001-08-23 2003-09-16 General Semiconductor, Inc. Trench DMOS transistor with embedded trench schottky rectifier
US6762127B2 (en) * 2001-08-23 2004-07-13 Yves Pierre Boiteux Etch process for dielectric materials comprising oxidized organo silane materials
US6444574B1 (en) 2001-09-06 2002-09-03 Powerchip Semiconductor Corp. Method for forming stepped contact hole for semiconductor devices
US6465304B1 (en) 2001-10-04 2002-10-15 General Semiconductor, Inc. Method for fabricating a power semiconductor device having a floating island voltage sustaining layer
US6657254B2 (en) * 2001-11-21 2003-12-02 General Semiconductor, Inc. Trench MOSFET device with improved on-resistance
DE10296970B4 (de) 2001-11-30 2008-04-24 Shindengen Electric Mfg. Co. Ltd. Halbleitervorrichtung und Verfahren zur Herstellung derselben
US6534824B1 (en) * 2002-02-20 2003-03-18 International Business Machines Corporation Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell
US7091573B2 (en) * 2002-03-19 2006-08-15 Infineon Technologies Ag Power transistor
DE10212149B4 (de) 2002-03-19 2007-10-04 Infineon Technologies Ag Transistoranordnung mit Schirmelektrode außerhalb eines aktiven Zellenfeldes und reduzierter Gate-Drain-Kapazität
TWI248136B (en) * 2002-03-19 2006-01-21 Infineon Technologies Ag Method for fabricating a transistor arrangement having trench transistor cells having a field electrode
DE10214151B4 (de) * 2002-03-28 2007-04-05 Infineon Technologies Ag Halbleiterbauelement mit erhöhter Durchbruchspannung im Randbereich
TW573344B (en) * 2002-05-24 2004-01-21 Nanya Technology Corp Separated gate flash memory and its manufacturing method
WO2003103056A2 (en) 2002-05-31 2003-12-11 Koninklijke Philips Electronics N.V. Trench-gate semiconductor device,corresponding module and apparatus ,and method of operating the device
JP2004055803A (ja) * 2002-07-19 2004-02-19 Renesas Technology Corp 半導体装置
US6878994B2 (en) 2002-08-22 2005-04-12 International Rectifier Corporation MOSgated device with accumulated channel region and Schottky contact
JP3875184B2 (ja) * 2002-11-20 2007-01-31 富士通株式会社 ショットキーダイオード及びその製造方法
US6861701B2 (en) * 2003-03-05 2005-03-01 Advanced Analogic Technologies, Inc. Trench power MOSFET with planarized gate bus
US7638841B2 (en) * 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
DE10324754B4 (de) * 2003-05-30 2018-11-08 Infineon Technologies Ag Halbleiterbauelement
US6800509B1 (en) * 2003-06-24 2004-10-05 Anpec Electronics Corporation Process for enhancement of voltage endurance and reduction of parasitic capacitance for a trench power MOSFET
US7473929B2 (en) * 2003-07-02 2009-01-06 Panasonic Corporation Semiconductor device and method for fabricating the same
TWI251342B (en) * 2003-07-24 2006-03-11 Samsung Electronics Co Ltd Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same
US6987305B2 (en) * 2003-08-04 2006-01-17 International Rectifier Corporation Integrated FET and schottky device
JP2005285913A (ja) * 2004-03-29 2005-10-13 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US7259415B1 (en) * 2004-09-02 2007-08-21 Micron Technology, Inc. Long retention time single transistor vertical memory gain cell
DE102004057237B4 (de) * 2004-11-26 2007-02-08 Infineon Technologies Ag Verfahren zum Herstellen von Kontaktlöchern in einem Halbleiterkörper sowie Transistor mit vertikalem Aufbau
DE102004057235B4 (de) * 2004-11-26 2007-12-27 Infineon Technologies Ag Vertikaler Trenchtransistor und Verfahren zu dessen Herstellung
US7285822B2 (en) * 2005-02-11 2007-10-23 Alpha & Omega Semiconductor, Inc. Power MOS device
KR101236030B1 (ko) 2005-04-06 2013-02-21 페어차일드 세미컨덕터 코포레이션 트랜치-게이트 전계효과 트랜지스터 및 그 형성 방법

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8680611B2 (en) 2005-04-06 2014-03-25 Fairchild Semiconductor Corporation Field effect transistor and schottky diode structures
CN103367360A (zh) * 2012-03-26 2013-10-23 株式会社东芝 半导体元件
CN105977157A (zh) * 2016-07-25 2016-09-28 吉林华微电子股份有限公司 一种igbt器件的制造方法及其器件
CN106098561A (zh) * 2016-07-25 2016-11-09 吉林华微电子股份有限公司 一种mosfet器件的制造方法及其器件
CN106098752A (zh) * 2016-07-25 2016-11-09 吉林华微电子股份有限公司 一种igbt器件及其制造方法

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US20140203355A1 (en) 2014-07-24
TW200644243A (en) 2006-12-16
US7504306B2 (en) 2009-03-17
CN102867825B (zh) 2016-04-06
HK1120160A1 (en) 2009-03-20
CN101185169A (zh) 2008-05-21
US20120319197A1 (en) 2012-12-20
DE112006000832T5 (de) 2008-02-14
US8084327B2 (en) 2011-12-27
JP2008536316A (ja) 2008-09-04
WO2006108011A2 (en) 2006-10-12
KR20120127677A (ko) 2012-11-22
US8680611B2 (en) 2014-03-25
TWI434412B (zh) 2014-04-11
US20090111227A1 (en) 2009-04-30
DE112006000832B4 (de) 2018-09-27
US20060267090A1 (en) 2006-11-30
US20120156845A1 (en) 2012-06-21
AT504998A2 (de) 2008-09-15
CN101185169B (zh) 2010-08-18

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