CN101971332B - 包括嵌入倒装芯片的半导体管芯封装 - Google Patents

包括嵌入倒装芯片的半导体管芯封装 Download PDF

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Publication number
CN101971332B
CN101971332B CN200980108883.5A CN200980108883A CN101971332B CN 101971332 B CN101971332 B CN 101971332B CN 200980108883 A CN200980108883 A CN 200980108883A CN 101971332 B CN101971332 B CN 101971332B
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semiconductor element
lead frame
frame structure
semiconductor
die package
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CN101971332A (zh
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Y·刘
J·鞠
袁忠发
R·罗
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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Abstract

一种半导体管芯封装。该半导体管芯封装包括引线框架结构、包括附连至引线框架结构的第一侧的第一表面的第一半导体管芯、以及附连至引线框架结构的第二侧的第二半导体管芯。该第二半导体管芯包括集成电路管芯。外壳材料在引线框架结构的至少一部分、第一半导体管芯和第二半导体管芯之上形成。模制材料的外表面与半导体管芯的第一表面基本共面。

Description

包括嵌入倒装芯片的半导体管芯封装
相关申请的交叉参照
本申请与同日提交的题为“包括多个半导体管芯的半导体管芯封装（Semiconductor Die Package Including Multiple Semiconductor Dice）”的美国专利申请No.12/046,939（律师卷号No.018865-027900US）相关，该申请通用地通过引用全部结合于此。
背景技术
诸如蜂窝电话的便携式设备层出不穷。因此存在对具有更好散热性质的更小半导体管芯封装的需求。
小半导体管芯封装可能有用的一个特定区域是在电路中，该半导体管芯封装为包括D+/D-线路的连接提供过电压保护（OVP）。一家公司On Semi生产了包括该功能（Vbus（V总线）OVP功能）的半导体管芯封装。然而，它是双共面管芯封装。它不具有如本发明实施例的在堆叠双管芯封装中的D+/D-连接性检测功能。
本发明各实施例单独地和共同地解决上述问题及其它问题。
简述
本发明各实施例涉及半导体管芯封装及其制造方法。
本发明的一个实施例涉及一种半导体管芯封装。该半导体管芯封装包括引线框架结构、附连至引线框架结构的第一面的包括第一表面的第一半导体管芯、以及附连至引线框架结构的第二面的第二半导体管芯。该第二半导体管芯包括集成电路管芯。外壳材料在引线框架结构的至少一部分上形成，并保护该第一半导体管芯和第二半导体管芯。模制材料的外表面可与该半导体管芯的第一表面基本共面，且该第一表面可通过该模制材料暴露。
本发明的另一实施例涉及一种半导体管芯封装，该半导体管芯封装包括：包括功率晶体管的第一半导体管芯；以及包括集成电路的第二半导体管芯。第一半导体管芯被配置成检测USB设备。第一半导体管芯和第二半导体管芯被堆叠在该半导体管芯封装内。
本发明的另一实施例涉及一种方法，该方法包括：获取引线框架结构；将包括第一表面的第一半导体管芯附连至引线框架结构的第一面；以及将第二半导体管芯附连至引线框架结构的第二面。该第二半导体管芯包括集成电路管芯。该方法还包括在引线框架结构的至少一部分上形成外壳材料。在所形成的半导体管芯封装中，模制材料的外表面可与该半导体管芯的第一表面基本共面，且该第一表面可通过该模制材料暴露。
本发明的另一实施例涉及一种用于制造半导体管芯封装的方法。该方法包括：获取包括功率晶体管的第一半导体管芯；并将包括集成电路的第二半导体管芯堆叠在第一半导体管芯上，该第二半导体管芯被配置成检测USB设备。
在详细描述中参照附图进一步详细描述了本发明的这些和其他实施例。
附图简述
图1示出根据本发明一实施例的半导体管芯封装的俯视立体图。
图2示出根据本发明一实施例的半导体管芯封装的仰视立体图。
图3示出图1所示半导体管芯封装的俯视立体图，其中示出了该封装的内部部件。
图4示出图1所示半导体管芯封装的俯视立体图，其中示出了该封装的内部部件。
图5示出该半导体管芯封装的仰视立体图，其中在腔壁与半导体管芯之间的间隙中没有填充材料。
图6示出已被放置在至少部分地由外壳材料形成的腔体内的倒装芯片的特写图。
图7示出图1中所示半导体管芯封装的俯视平面图。
图8示出图2中所示半导体管芯封装的仰视平面图。
图9-10示出该半导体管芯封装的侧视图。
图11(a)-11(f)示出在形成半导体管芯封装的过程期间形成的前体。
图12-13示出电路图。
在附图中，相同标记可指示相同元件，且不再重复对这些元件的描述。
详细描述
本发明诸实施例涉及一种设计在诸如模制外壳结构的外壳中的集成电路（或IC）管芯与引线框架结构之间的电互连的方法。在本发明的实施例中，该引线框架结构可为安装在其上的半导体管芯提供电连接和热通道。
本发明的另一实施例涉及一种用于设计模制外壳中的腔体的方法，其中该模制外壳至少装有集成电路管芯和引线框架结构。具有与其附连的焊料隆起焊盘的功率MOSFET管芯可倒装附连至限定腔体的底面。引线框架中的源和栅连接焊盘部分可通过所形成的腔体底部处的模制材料暴露。
本发明诸实施例还涉及制造半导体管芯封装的方法。此类实施例包括用于将半导体管芯附连至上述腔体的底部、并用诸如底填充材料的材料填充该管芯与形成腔体的壁之间的间隙的方法。该底填充材料使半导体管芯在该腔体内稳定。
本发明诸实施例还提供用于蜂窝电话系统级应用的堆叠和嵌入管芯封装开关，该开关可组合集成电路管芯与功率晶体管管芯（例如可从本申请的受让人处购得的p沟道MOSFET倒装芯片）。本发明诸实施例能为Vbus引脚提供功率保护功能，以及带有D+/D-连接性检测的过电压保护。
根据本发明一实施例的封装可具有标准工业引脚输出。所暴露的MOSFET漏极区能提供至外部环境的电连接引脚（V输出）和热通道。在根据本发明一实施例的封装中，在引线框架结构的DAP（管芯附连焊盘或垫）中设计了多个热通道以得到附加的热传递能力。
图1示出根据本发明一实施例的半导体管芯封装100的俯视立体图。半导体管芯封装100包括长度L（例如约2.6mm）、宽度W（例如约1.8mm）以及高度H（例如0.7mm）。如图所示，封装100包括覆盖引线框架结构的模制材料24。在图1中，示出了引线框架的引线20(c)。这些引线20(c)不延伸通过模制材料24（例如环氧化物模制材料）的横向表面，但在本发明的其他实施例中，这些引线可延伸通过模制材料24的横向表面。虽然在本文中详细讨论了模制材料24，但应理解本发明诸实施例不限于此，且可使用任何其他合适的工艺或材料来形成外壳材料。
图2示出图1中所示的半导体管芯封装100的仰视立体图。如图2所示，模制材料24的外表面24(a)可与半导体管芯封装100中的半导体管芯26的管芯表面26(a)基本共面，且可暴露该管芯表面26(a)。该半导体管芯26至少部分地由该模制材料24保护。因为该管芯表面26(a)通过模制材料24暴露，所以从半导体管芯26产生的热可迅速传递至在下方的电路板。
绝缘材料52填充管芯26与模制材料24之间的间隙，并覆盖管芯26的边缘。该绝缘材料52可包括诸如环氧化合物的底填充材料，而且可与模制材料24相同或不同。
在该特定实施例中，引线20(c)可指定如下：Vbus（来自充电器、USB设备或手持电池的电源输入）、D-（USB数据输入）、D+（USB数据输入）、R1（或者可选地LS控制或负载开关控制）、Vss（设备接地）、标记2（过电压/欠电压标记）以及标记1（充电器/USB设备检测标记）。引线20(c)可附加地或替代地形成通往外部环境的热通道。管芯表面26(a)可形成半导体管芯封装100的V输出（输出电压）连接，因此不需要单独的V输出引线。这节省了引线，从而节省出的引线能有利地用于某其他功能。
图3示出半导体管芯封装100的俯视立体图，而图4示出半导体管芯封装100的仰视立体图。还示出了半导体管芯封装100中的内部部件。半导体管芯封装100包括引线框架结构20、附连至引线框架结构20的第一面的包括第一表面26(a)的第一半导体管芯26、以及附连至引线框架结构20的第二面的第二半导体管芯30。模制材料24在引线框架20的至少一部分以及第二半导体管芯30上形成且与它们接触。模制材料24的外表面24(a)与第一半导体管芯26的第一表面26(a)基本共面。
第一半导体管芯26可包括任何合适的半导体器件。合适的器件可包括垂直或水平器件。垂直器件具有在管芯一面的至少一个输入和在管芯另一面的输出，以使电流能垂直流过该管芯。水平器件包括在管芯一面的至少一个输入和在管芯同一面的至少一个输出，以使电流水平地流过该管芯。美国专利申请No.6,274,905和6,351,018中也描述了示例性垂直功率器件，以上两个专利均转让给与本申请相同的受让人，且通用地通过引用整体结合于此。
垂直功率晶体管包括VDMOS晶体管和垂直双极晶体管。VDMOS晶体管是具有通过扩散形成的两个或多个半导体区的MOSFET。它具有源极区、漏极区以及栅极。该器件是垂直的，因为源极区和漏极区在半导体管芯的两个相反表面上。栅极可以是沟槽型栅极结构或平面栅极结构，且在与源极区相同的表面上形成。沟槽型栅极结构是优选的，因为沟槽型栅极结构较窄，从而比平面栅极结构占据更少空间。在工作期间，VDMOS器件中从源极区流向漏极区的电流基本垂直于管芯表面。
在一些实施例中，第一半导体管芯26可以是具有诸如功率MOSFET的分立器件的半导体管芯。例如，第一半导体管芯26可以是可从费尔洽德（Fairchild）半导体公司买到的P沟道MOSFET管芯。
第二半导体管芯30可包括集成电路管芯。集成电路管芯中包括许多电器件，且可被配置成执行控制或检测功能。例如，该集成电路管芯可被配置成检测USB设备或电池充电器的存在。集成电路管芯可与仅具有一个分立器件的管芯相当。在本发明的其他实施例中可使用各种类型的集成电路管芯。
图5示出该封装的俯视立体图，且模制材料24与第一半导体管芯26之间的间隙50中没有填充上述绝缘材料。间隙50包围第一半导体管芯50的边缘。
图6示出被安装在栅极管芯附连焊盘部20(f)和源极管芯附连焊盘部20(g)上的第一半导体管芯26的特写立体图。源极焊球22(s)可将第一半导体管芯26的MOSFET中的源极区电耦合至源极管芯附连焊盘部20(g)。栅极焊球22(f)将栅极管芯附连焊盘部20(f)电耦合至第一半导体管芯26的MOSFET中的栅极区。
参照图3和6，引线框架结构20可提供第一半导体管芯26与第二半导体管芯30之间的连接。例如，源极附连焊盘部20(g)可连接至第一半导体管芯26中的源极区，并经由导线32(b)连接至封装100中的Vbus引线和第二半导体管芯30中的Vbus端子。导线32(a)可将第二半导体管芯30中的端子（例如标记3端子）连接至引线框架20的栅极管芯附连部20(f)，从而连接至第一半导体管芯26的MOSFET中的栅极区。
图7-10中示出了该半导体管芯封装的附加视图。图7示出图1中所示半导体管芯封装的俯视平面图。图8示出图1中所示半导体管芯封装的仰视平面图。图9-10示出该半导体管芯封装的侧视图。如图7-10所示，引线20(c)不延伸通过模制材料24。而且，如图10所示，第一和第二半导体管芯26、30在引线框架20的相反两面上，且因为它们相互交迭而成堆叠关系。
可参照图11(a)-11(f)描述根据本发明一实施例的方法。根据本发明一实施例的一种方法可包括：获取引线框架结构；将包括第一表面的第一半导体管芯附连至该引线框架结构的第一面；将第二半导体管芯附连至该引线框架的第二面，其中该第二半导体管芯包括集成电路管芯；以及在该引线框架的至少一部分上形成外壳材料。在所形成的半导体管芯封装中，模制材料的外表面与该半导体管芯的第一表面基本共面。在该过程期间，第一半导体管芯被堆叠在第二半导体管芯上，因为它们附连至引线框架结构的相反两面且在所形成的半导体管芯封装中相互交迭。
图11(a)示出引线框架结构10。它可按照任何合适的方式来获得。例如，它可如下所述地来制造，或它可以其他方式从商业源获得。
术语“引线框架结构”可表示从引线框架取得的结构，或与引线框架相同。每个引线框架结构可包括两个或多个引线和引线表面以及管芯附连区。这些引线从管芯附连区横向延伸。单个引线框架结构可包括栅极引线结构和源极引线结构。
引线框架结构20可包括任何合适的材料。示例性引线框架结构材料包括诸如铜、铝等金属及其合金。引线框架结构还可包括诸如金、铬、银、钯、镍等的镀层之类的镀层。引线框架结构还可具有任何合适的厚度，包括小于约1mm的厚度（例如小于约0.5mm）。
可使用常规工艺来模压、蚀刻和/或使引线框架图案化，以使引线框架结构的引线或其他部分成形。例如，通过模压并通过蚀刻连续导电薄板以形成预定图案可形成引线框架结构。在蚀刻之前或之后，可任选地模压该引线框架结构，以使引线框架结构的管芯附连表面相对于该引线框架结构的引线表面沉降设置。如果使用了模压，则该引线框架结构可以是通过连接杆连接的引线框架结构阵列中的许多引线框架结构之一。还可切割该引线框架结构阵列以将该引线框架结构与其他引线框架结构分离。作为切割的结果，在最终半导体管芯封装中的诸如源极引线和栅极引线的引线框架结构的部分可相互电去耦和机械去耦。因此，引线框架结构可以是连续的金属结构或不连续的金属结构。
参照图11（b），第二半导体管芯30然后可被附连至引线框架结构的管芯附连焊盘。可使用导电粘接剂（例如焊料）或不导电粘接剂将第二半导体管芯30附连至该引线框架结构的管芯附连焊盘。
然后，如图11(c)所示，可在半导体管芯30与引线框架结构20的引线20(c)之间形成引线接合。导线32可包括金、铜、或涂有贵金属的铜。常规的引线接合工艺可在本发明诸实施例中使用。
参照图11(d)，模制材料24然后在引线框架结构20和第二半导体管芯30上形成。如图11(d)所示，腔体54在模制之后形成。腔体54的底面由栅极管芯附连焊盘部24(f)和源极管芯附连焊盘部20(f)以及模制材料24限定。
腔体54的尺寸比第一半导体管芯26的尺寸大，因此腔体54能容纳第一半导体管芯26。焊球位于第一半导体管芯26的第一面处。带有隆起焊盘的第一半导体管芯26然后可倒装在栅极管芯附连焊盘部24(f)以及源极管芯附连焊盘部20(f)上，且在腔体54内，如图11(e)所示。然后可执行标准的回流工艺。
如图11(f)所示，绝缘材料52可填充第一半导体管芯26与限定腔体54的表面之间的间隙50。该绝缘材料可以与模制材料24相同或不同。如果该绝缘材料与模制材料相同，则绝缘材料52与模制材料24之间会存在界面，因为它们在不同时刻形成。
图12示出可与上述封装关联的电路图。器件400可包括在单个封装中的Vbus过电压保护（OVP）和D+/D-连接性检测。该器件400可以是用于确定标准USB设备是否已连接或电池充电装置是否已连接的USB连接监测器件。在工作时，器件400可将标记1引线设置为逻辑高或低，以作为对系统控制器的标准USB设备或充电器已连接至USB端口的指示。它还监测Vbus的过电压或欠电压状况。如果存在Vbus引线低于3.3V或高于6.0V的状况，则标记2引线可被设置为低。如果存在Vbus引线低于3.3V或高于6.0V的状况，则LS（负载开关）控制（LS控制）引线可被设置为高，从而使PMOS开关截止。
在一示例性实施例中，器件400中的端子连接可如下：Vbus（来自充电器或其他外部电源的电源连接）；D-输入（USB数据输入）；D+输入（USB数据输入）；Gnd（设备接地引脚）；标记2（指示Vbus是否在电压范围（例如3.3V-6V）之外）；标记1（指示D-和D+是否短路；低：标准USB设备；高：充电器；标准输出驱动H=2.5V、L=0.8V）。
图13示出可与上述封装关联的电路图。图13示出与功率晶体管管芯302电耦合的集成电路管芯300。分立器件管芯302可以是P沟道功率MOSFET管芯。集成电路管芯300可以是被配置成确定标准USB设备是否已连接或电池充电装置是否已连接的USB连接监测器件。集成电路管芯300的特征可包括过电压/欠电压检测、充电器/USB设备检测，且可在2.7V到6V的Vbus电源电压下工作。在图13中，虚线可示出可设置封装引线连接的位置。
虽然在图12-13中示出了具体电路，但本发明的实施例不限于此。例如，根据本发明一实施例的封装可使用作为功率MOSFET的第一半导体管芯和作为具有与上述功能不同的控制功能的集成电路管芯的第二半导体管芯。该封装可在功率电路中使用，但不需要用于检测USB设备的存在。
本发明诸实施例具有优点。例如，本发明诸实施例紧凑，因为半导体管芯可相互堆叠。此外，在本发明诸实施例中高效地散热，因为该封装中的至少一个管芯被暴露给外部环境。此外，本发明诸实施例能使用标准倒装焊技术。
本文中已采用的术语和表达被用作描述术语而非作为限制，而且使用这些术语和表达不旨在排除所示和所描述特征的等价物或其部分，应理解各种变型可落在所声明要求保护的本发明的范围内。此外，本发明的任一实施例的任一个或多个特征可与本发明的任一其他实施例的任一个或多个其他特征组合，而不背离本发明的范围。例如，虽然示出了具有两个管芯的半导体管芯封装，但本发明的其他实施例可包括在单个半导体管芯封装内的两个以上半导体管芯。
以上提及的所有专利申请、专利以及出版物通用地通过引用整体结合于此。没有一种被认为是现有技术。

Claims (14)

1.一种半导体管芯封装，包括：
引线框架结构；
包括第一表面的第一半导体管芯，附连至所述引线框架结构的第一面，并且所述第一半导体管芯被倒装附连到所述引线框架结构的引线；
第二半导体管芯，所述第二半导体管芯附连至所述引线框架结构的第二面，其中所述第二半导体管芯包括集成电路管芯，并且所述集成电路管芯引线接合至所述引线框架结构的引线；以及
外壳材料，所述外壳材料在所述引线框架结构的至少一部分上并且在整个第二半导体管芯上形成，并保护所述第一半导体管芯和所述第二半导体管芯，其中所述第一半导体管芯的第一表面通过所述外壳材料暴露，
其中所述外壳材料的外表面与所述第一半导体管芯的第一表面基本共面；
其中所述第一半导体管芯包括边缘，且其中所述外壳材料进一步包括由壁限定的腔体，其中所述第一半导体管芯被设置在所述腔体内，且所述壁与所述第一半导体管芯的边缘分隔开；以及
其中所述引线框架的一个或多个引线被倒装连接到所述第一管芯并引线接合至所述第二管芯，从而将所述管芯彼此连接。
2.如权利要求1所述的半导体管芯封装，其特征在于，所述第一半导体管芯的边缘与限定所述腔体的壁之间的区域用绝缘材料填充，以保护所述第一半导体管芯的边缘并继续暴露所述半导体管芯的第一面。
3.如权利要求1所述的半导体管芯封装，其特征在于，所述外壳材料是模制材料。
4.如权利要求1所述的半导体管芯封装，其特征在于，所述引线框架结构包括栅极附连焊盘，其中所述栅极附连焊盘被电连接至所述第二半导体管芯并且所述第二半导体管芯是集成电路，以用于控制所述第一半导体的运行。
5.如权利要求1所述的半导体管芯封装，其特征在于，所述第一半导体管芯包括功率晶体管。
6.如权利要求1所述的半导体管芯封装，其特征在于，所述第一半导体管芯包括垂直功率MOSFET。
7.如权利要求1所述的半导体管芯封装，其特征在于，所述半导体管芯封装被配置成提供过电压保护和USB连接性检测。
8.一种用于制造半导体管芯封装的方法，包括：
获取引线框架结构；
倒装芯片将包括第一表面的第一半导体管芯附连至所述引线框架结构的第一面以及所述引线框架结构的栅极管芯附连焊盘部和源极管芯附连焊盘部；
将第二半导体管芯附连至所述引线框架结构的第二面，并且将所述第二半导体管芯引线接合至所述引线框架结构的引线，其中所述第二半导体管芯包括集成电路管芯；以及
在所述引线框架结构的至少一部分上且在整个第二半导体管芯上形成保护所述第一半导体管芯和所述第二半导体管芯的外壳材料，所述外壳材料的外表面与所述第一半导体管芯的第一表面基本上共面，所述第一半导体管芯的第一表面通过所述外壳材料暴露，
其中所述第一半导体管芯包括边缘，且其中所述外壳材料进一步包括由壁限定的腔体，其中所述第一半导体管芯被设置在所述腔体内，且所述壁与所述第一半导体管芯的边缘分隔开；以及
其中所述引线框架的一个或多个引线被倒装连接到所述第一管芯并引线接合至所述第二管芯，从而将所述管芯彼此连接。
9.如权利要求8所述的方法，其特征在于，所述第一半导体管芯的边缘与限定所述腔体的壁之间的区域用绝缘材料填充，以保护所述第一半导体管芯的边缘并继续暴露所述半导体管芯的第一面。
10.如权利要求8所述的方法，其特征在于，所述外壳材料是模制材料。
11.如权利要求8所述的方法，其特征在于，所述栅极附连焊盘被电连接至所述第二半导体管芯并且所述第二半导体管芯是集成电路，以用于控制所述第一半导体管芯的运行。
12.如权利要求8所述的方法，其特征在于，所述第一半导体管芯包括功率晶体管。
13.如权利要求8所述的方法，其特征在于，所述第一半导体管芯包括垂直功率MOSFET。
14.如权利要求8所述的方法，其特征在于，所述半导体管芯封装被配置成提供过电压保护和USB连接性检测。
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US20090230537A1 (en) 2009-09-17
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TW200943517A (en) 2009-10-16
US7768108B2 (en) 2010-08-03
TWI464851B (zh) 2014-12-11
MY149770A (en) 2013-10-14
WO2009114392A3 (en) 2009-11-26
KR101483204B1 (ko) 2015-01-15
CN101971332A (zh) 2011-02-09

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