CN101989183A - Method for realizing energy-saving storing of hybrid main storage - Google Patents
Method for realizing energy-saving storing of hybrid main storage Download PDFInfo
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Abstract
The invention discloses a method for realizing energy-saving storing of a hybrid main storage. The method comprises the following steps: constructing the hybrid main storage taking a phase change storage as a main storage and a dynamic random storage as a buffer storage, designing a read-write policy adapting to the structure of the main storage, and reading and writing data in a disc and the phase change storage according to the read-write policy. The invention ensures that the structure of the original main storage is improved, and fully utilizes the advantages of high capacity and low power consumption of the phase change storage and the characteristic of low time delay of the dynamic random storage, so that the hybrid main storage acquires higher capacity on the premise that the power consumption and the time delay are not increased, thereby reducing the times of accessing the disc and realizing energy saving in storing.
Description
Affiliated technical field
The present invention relates to embedded system storage energy-saving field, relate in particular to a kind of method of improving primary memory structure and the energy-conservation storage of read-write strategy realization.
Background technology
Storer is very important ingredient in the computer system, is to be used for the parts of stored programme and data.Primary memory is the storage space that processor can directly address, and all programs and data must be loaded in the primary memory and could move.Therefore, the performance of primary memory directly has influence on the travelling speed of whole computer system.Along with the speed of processor constantly promotes, the read or write speed of primary memory does not catch up with the speed of processor far away, becomes the bottleneck that improves system performance gradually.Therefore, how under the prerequisite that does not increase expense and energy consumption, the capacity and the read or write speed that improve primary memory to greatest extent are the focuses of research always.
The proposition of cache technology is exactly in order to solve the slow problem of primary memory read or write speed.Because the speed of processor is more a lot of soon than the access speed of primary memory, processor is being waited for through regular meeting and is just being continued after the primary memory read-write is finished to carry out.Make that like this performance of processors does not fully obtain utilizing.In order to alleviate the gaps between their growth rates of processor and primary memory, the cache technology is just arisen at the historic moment.Cache is a kind of special memory sub-system between processor and primary memory, and its access speed is faster than primary memory.The data in the primary memory of processor frequent access and the memory address of these data have been stored among the cache.When processor need be visited certain address in the primary memory, cache just checked whether store this address.If there is this address, just the data with this address correspondence return to processor; If do not store this address, just carry out main memory accesses generally.
Virtual memory is exactly a kind of technology that solves the main memory capacity deficiency.This technology combines the temporary space on primary memory and the disk, makes application program think that it has the internal memory of a very large continuous whole in space.Virtual memory is in fact when the primary memory remaining space is not enough, and partial data is moved to the hard disk from primary memory, continues operation with the release portion space to program.
Though processor and the contradiction of primary memory on speed have been alleviated in the proposition of these technology to a certain extent, the relief capabilities of these technology is limited all the time.For example:, on the basis of one-level cache, proposed secondary cache even three grades of cache in order to adapt to the raising of processor speed.But the performance impact of three grades of cache is just not too obvious, just helps large programs such as server or recreation, and is little to most of home computer effects.The capacity of virtual memory neither be unlimited, is generally 1.5-2 times of physical memory, can not surpass the memory address scope 4GB of 32-bit operating system simultaneously.As seen, these technology still do not change the situation that the read or write speed of primary memory is the bottleneck of the whole computer system performance lifting of restriction.Because the lifting of processor speed far is unable to catch up with in the lifting of main memory accesses speed, the contradiction between them on speed all can show especially out sooner or later with avoiding.
The arrival in multinuclear epoch has proposed acid test more to primary memory.The present primary memory based on dynamic RAM DRAM of main flow has reached its limit.If improve the capacity of primary memory in order to adapt to the high-speed of processor, just must pay higher expense and energy consumption, cost performance is reduced greatly.Yet along with the quantity of nuclear is more and more, present primary memory will face increasing challenge.Therefore, many experts and scholars are devoted to study better storage medium, to solve the residing predicament of present memory technology.
The Flash storer is a kind of Electrically Erasable Read Only Memory, has characteristics such as solid-state property, volume are little, in light weight, anti-vibration, low energy consumption.It is a kind of not volatile storer, promptly still can preserve data muchly under the situation that does not have power supply, and its storage characteristics is equivalent to disk.It aspect price, access delay, transmission bandwidth, storage density and the energy consumption between RAM and disk.Because the Flash storer differs greatly than primary memory on access delay, therefore be difficult to apply it in the primary memory.At present, the Flash storer is mainly used in movable storage device, for example: USB flash disk, MP3, digital camera etc.Along with capacity is increasing more and more lower with price, the Flash storer may replace disk in the near future and be applied in the computer system.
Phase transition storage PCM is based on the storer of Ovshinsky in the Ao Fuxinsiji electronic effect of late 1960s proposition, utilizes the characteristic of chalcogenide compound material rapid phase transition under the electric pulse effect.Because the restriction of technology, this semiconductor memory technologies is all made progress very slow always.Up to latter stage in last century, along with the manufacturing technology of semi-conductor industry circle reaches nanometer scale, this technology just embodies its great superiority, thereby is able to develop rapidly.Phase transition storage has characteristics such as enhanced scalability, high access speed, high storage density and low energy consumption.It is only slow a little than dynamic RAM on access speed.According to these characteristics of phase transition storage, if can apply it to well in the primary memory, must solve problems such as low capacity that current primary memory faces, high energy consumption effectively, thereby greatly promote the overall performance of computer system.Because its access speed is lower with respect to dynamic RAM DRAM, if simply it as primary memory, can reduce performance of computer systems on the contrary.If can combine the composition primary memory to it and dynamic RAM, reach the effect of learning from other's strong points to offset one's weaknesses, having complementary advantages, should be helpful to promoting the primary memory performance.
Summary of the invention
For under the prerequisite that does not increase power consumption and time delay, increase the capacity of primary memory to greatest extent, adapt to the fast lifting of processor speed, reduce access times disk, reduce the energy that storage is consumed, the invention provides a kind of method that primary memory is realized energy-conservation storage of mixing.
The technical solution adopted for the present invention to solve the technical problems is:
A kind ofly mix the method that primary memory is realized energy-conservation storage, comprise the steps:
1) structure mixes primary memory:
Mix primary memory and be made up of phase transition storage PCM and dynamic RAM DRAM, phase transition storage provides the main capacity that mixes primary memory, needed instruction and data when being used for the stored programme operation; DRAM links to each other with phase transition storage with disk by data line, is used to cushion the data of disk and phase transition storage, and DRAM also links to each other with processor by data line, is used for sending data to processor;
2) according to following read-write strategy the data in disk and the phase transition storage are read and write:
When processor needs data or instruction, judge at first whether they are present in the DRAM buffer zone, just send it to processor if exist; If there is no in the DRAM buffer zone, just continue to judge whether they are present in the phase transition storage, just earlier it is read in the DRAM buffer zone, send to processor then if be present in phase transition storage; If they are not present in the phase transition storage, just from disk, it is read in the DRAM buffer zone, send to processor then;
When the DRAM buffer zone is full, the part page table can be replaced to load new data, before these page tables are replaced, judge at first whether whether page table that this plan is replaced be dirty data in the phase transition storage neutralization, if it is not in phase transition storage or dirty data, then with in its recording phase change memory, otherwise, directly it is override with new data.
For convenience the data in the DRAM buffer zone are managed, the present invention returns each item number in the DRAM buffer zone according to adding a TAG label, judge the following information of its flag data by the TAG label: whether effective, whether in phase transition storage, whether be modified; The data structure of described TAG label comprises significance bit item, PCM position item, dirty data position item, and wherein each is stored with a bit, and being provided with of each is regular as follows:
1) significance bit setting: when data deposited the DRAM buffer zone in, the significance bit among its label TAG was set to 1; When data were replaced out the DRAM buffer zone, the significance bit among its label TAG was set to 0; Significance bit is that new data can not be loaded in 1 the pairing data field of TAG, and significance bit is that new data can be loaded in 0 the pairing data field of TAG, loads that the significance bit of its TAG is set to 1 after the new data;
2) the PCM position is provided with: when data were read in the DRAM buffer zone from disk, the PCM position among its label TAG was set to 0; When data were read in the DRAM buffer zone from phase transition storage PCM, the PCM position among its label TAG was set to 1;
3) the dirty data position is provided with: when data were read in the DRAM buffer zone from disk or phase transition storage, the dirty data position among its label TAG was set to 0; After data were revised by processor, the dirty data position among its label TAG was set to 1.
At the DRAM buffer zone in the process that phase transition storage is write, also be provided with a phase transition storage write queue, when the page table that is replaced when the DRAM buffer zone need write back in the phase transition storage, earlier these page tables are sent in the phase transition storage write queue, and then recording phase change memory.
Compare with background technology, the useful effect that the present invention has is:
The mixing primary memory that utilizes phase transition storage and dynamic RAM to combine and form can make full use of their advantages separately, reaches the effect of mutual supplement with each other's advantages.Phase transition storage provides the main capacity that mixes primary memory, utilizes its high storage density characteristic greatly to improve main memory capacity, utilizes its low-voltage, low energy consumption characteristic to effectively reduce the energy consumption of whole primary memory.Dynamic RAM utilizes the characteristic of its high access speed to guarantee that the access speed of primary memory is not subjected to the influence of phase transition storage as the buffer zone that mixes primary memory.Therefore, mixing primary memory of the present invention can obtain following characteristic: high capacity, low expense, low energy consumption, high storage density and high access speed.These characteristics of mixing primary memory can solve the problems such as low capacity, high cost and high energy consumption that present primary memory faces effectively, thereby promote the overall performance of computer system.
Description of drawings
Fig. 1 is the mixing primary memory structural representation of the embodiment of the invention;
Fig. 2 is the data structure diagram of TAG in the DRAM buffer zone of the embodiment of the invention;
Fig. 3 is that the mixing primary memory of the embodiment of the invention is read strategic process figure;
Fig. 4 is that the mixing primary memory of the embodiment of the invention is write strategic process figure.
Embodiment
The embodiment of the embodiment of the invention is: at first, build the hardware environment of system according to mixing primary memory structural representation shown in Figure 1; Then according to TAG data structure configuration DRAM buffer zone shown in Figure 2; According to the read-write strategy data in disk and the phase transition storage are read and write at last.This implementation process is described in more detail below.
(1) structure mixes primary memory
The mixing primary memory is made up of phase transition storage PCM and dynamic RAM DRAM.Wherein, phase transition storage provides the main capacity that mixes primary memory, needed instruction and data when being used for the stored programme operation; Dynamic RAM is used to cushion the data of disk and phase transition storage as the memory buffer of mixing primary memory.The DRAM buffer zone can reading disk and the data of phase transition storage, so it needs data line directly to link to each other with phase transition storage with disk.The DRAM buffer zone is unique parts that can directly send data to processor, therefore has only it to have data line directly to link to each other with processor.When the DRAM buffer zone was full, the part page table will be replaced to load new data.If the data that are replaced not in phase transition storage or dirty data (be in the DRAM buffer zone data and its source data in disk or phase transition storage inconsistent), then need to write in the phase transition storage.In order to alleviate the lower writing rate of phase transition storage, avoid processor to wait as long for, in the process that phase transition storage is write, increase a phase transition storage write queue at the DRAM buffer zone.Therefore, the data line that the DRAM buffer zone writes back does not directly link to each other with phase transition storage, but is connected to the PCM write queue earlier, and then is connected to phase transition storage PCM.The structure of mixing primary memory as shown in Figure 1.
(2) DRAM buffer zone label TAG:
The DRAM buffer zone manages wherein data for convenience, gives each item number according to adding a label TAG, can judge the following information of its flag data by TAG: whether effective, whether in phase transition storage, whether be modified.The data structure of TAG as shown in Figure 2, wherein each is stored with a bit.Each setting regular as follows:
1) significance bit setting: when data deposited the DRAM buffer zone in, the significance bit among its label TAG was set to 1; When data were replaced out the DRAM buffer zone, the significance bit among its label TAG was set to 0.Significance bit is that new data can not be loaded in 1 the pairing data field of TAG, and significance bit is that new data can be loaded in 0 the pairing data field of TAG, loads that the significance bit of its TAG is set to 1 after the new data.
2) the PCM position is provided with: when data were read in the DRAM buffer zone from disk, the PCM position among its label TAG was set to 0; When data were read in the DRAM buffer zone from phase transition storage PCM, the PCM position among its label TAG was set to 1.
3) the dirty data position is provided with: when data were read in the DRAM buffer zone from disk or phase transition storage, the dirty data position among its label TAG was set to 0; After data were revised by processor, the dirty data position among its label TAG was set to 1.
(3) the read-write strategy of mixing primary memory:
When processor needs data or instruction, judge at first whether they are present in the DRAM buffer zone, just send it to processor if exist; If there is no in the DRAM buffer zone, just continue to judge whether they are present among the phase transition storage PCM, earlier it is read in the DRAM buffer zone if just exist, send to processor then, it is 110 that this data item TAG is set simultaneously; If they are not present in the phase transition storage, just from disk, it is read in the DRAM buffer zone, send to processor then, it is 100 that this data item TAG is set simultaneously.Read tactful idiographic flow as shown in Figure 3.When the DRAM buffer zone is full, the part page table will be replaced to load new data, before these page tables are replaced, to judge at first whether whether it neutralizes at phase transition storage is dirty data, if it is not in phase transition storage or dirty data, then earlier it is sent in the PCM write queue, recording phase change memory PCM then, otherwise the significance bit among this data item TAG is set to 0.Write tactful idiographic flow as shown in Figure 4.
Claims (3)
1. one kind is mixed the method that primary memory is realized energy-conservation storage, it is characterized in that comprising the steps:
1) structure mixes primary memory:
Mix primary memory and be made up of phase transition storage PCM and dynamic RAM DRAM, phase transition storage provides the main capacity that mixes primary memory, needed instruction and data when being used for the stored programme operation; DRAM links to each other with phase transition storage with disk by data line, is used to cushion the data of disk and phase transition storage, and DRAM also links to each other with processor by data line, is used for sending data to processor;
2) according to following read-write strategy the data in disk and the phase transition storage are read and write:
When processor needs data or instruction, judge at first whether they are present in the DRAM buffer zone, just send it to processor if exist; If there is no in the DRAM buffer zone, just continue to judge whether they are present in the phase transition storage, just earlier it is read in the DRAM buffer zone, send to processor then if be present in phase transition storage; If they are not present in the phase transition storage, just from disk, it is read in the DRAM buffer zone, send to processor then;
When the DRAM buffer zone is full, the part page table can be replaced to load new data, before these page tables are replaced, judge at first whether whether page table that this plan is replaced be dirty data in the phase transition storage neutralization, if it is not in phase transition storage or dirty data, then with in its recording phase change memory, otherwise, directly it is override with new data.
2. mixing primary memory as claimed in claim 1 is realized the method for energy-conservation storage, it is characterized in that: give each item number in the DRAM buffer zone according to adding a TAG label, judge the following information of its flag data by the TAG label: whether effective, whether in phase transition storage, whether be modified; The data structure of described TAG label comprises significance bit item, PCM position item, dirty data position item, and wherein each is stored with a bit, and being provided with of each is regular as follows:
1) significance bit setting: when data deposited the DRAM buffer zone in, the significance bit among its label TAG was set to 1; When data were replaced out the DRAM buffer zone, the significance bit among its label TAG was set to 0; Significance bit is that new data can not be loaded in 1 the pairing data field of TAG, and significance bit is that new data can be loaded in 0 the pairing data field of TAG, loads that the significance bit of its TAG is set to 1 after the new data;
2) the PCM position is provided with: when data were read in the DRAM buffer zone from disk, the PCM position among its label TAG was set to 0; When data were read in the DRAM buffer zone from phase transition storage PCM, the PCM position among its label TAG was set to 1;
3) the dirty data position is provided with: when data were read in the DRAM buffer zone from disk or phase transition storage, the dirty data position among its label TAG was set to 0; After data were revised by processor, the dirty data position among its label TAG was set to 1.
3. mixing primary memory as claimed in claim 1 is realized the method for energy-conservation storage, it is characterized in that: at the DRAM buffer zone in the process that phase transition storage is write, be provided with a phase transition storage write queue, when the page table that is replaced when the DRAM buffer zone need write back in the phase transition storage, earlier these page tables are sent in the phase transition storage write queue, and then recording phase change memory.
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| CN104834608B (en) * | 2015-05-12 | 2017-09-29 | 华中科技大学 | A kind of buffer replacing method under isomery memory environment |
| CN106469020A (en) * | 2015-08-19 | 2017-03-01 | 旺宏电子股份有限公司 | Cache element and control method and its application system |
| CN107704400A (en) * | 2017-10-12 | 2018-02-16 | 郑州云海信息技术有限公司 | A kind of caching of page method towards non-volatile memory |
| CN111177023A (en) * | 2019-12-27 | 2020-05-19 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Method and device for distributing storage intervals in embedded equipment |
| CN111984201A (en) * | 2020-09-01 | 2020-11-24 | 云南财经大学 | Astronomical observation data high-reliability acquisition method and system based on persistent memory |
| CN111984201B (en) * | 2020-09-01 | 2023-01-31 | 云南财经大学 | Astronomical observation data high-reliability acquisition method and system based on persistent memory |
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