CN102117762B

CN102117762B - Shallow trench isolation channel

Info

Publication number: CN102117762B
Application number: CN201010027221XA
Authority: CN
Inventors: 钱文生; 丁宇
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2010-01-05
Filing date: 2010-01-05
Publication date: 2012-11-07
Anticipated expiration: 2030-01-05
Also published as: CN102117762A

Abstract

The invention discloses a shallow trench isolation channel. The shallow trench isolation channel consists of an upper part and a lower part which are vertically connected, wherein the width of the lower part is more than that of the upper part. The shallow trench isolation is formed by the following steps: partial width of the isolation channel is photoetched and etched, wherein the etching depth is less than that of the shallow trench isolation channel, and photoresist is removed; a thin oxidation layer is precipitated; by utilizing an etching process, the oxidation layer at the bottom of the shallow trench isolation channel is removed, and an oxidation layer on a lateral wall is left; isotropic etching of a dry method is carried out, and the depth of the shallow trench isolation channel is achieved finally after etching; and the oxidation layer on the lateral wall is removed, and a linear oxidation layer grows, and a high-density plasma oxidation layer is precipitated. By the shallow trench isolation, the problems of electric leakage of a device and worse isolation due to the fact that a metal silicate extends downwards the edge of the shallow trench isolation in a process that the metal silicate groves precipitate can be solved.

Description

Shallow ditch non-intercommunicating cells

Technical field

The present invention relates to a kind of semiconductor integrated circuit manufacturing process, particularly relate to a kind of shallow ditch non-intercommunicating cells.

Background technology

In the manufacture of semiconductor technology, shallow ditch non-intercommunicating cells (Shallow Trench Isolation is called for short STI) is the device isolation structure of main flow, and it has save area, and the characteristics that isolation effect is good are widely used in all kinds of deep-submicron manufacture of semiconductor.

Can cause the problem of marginal trough (Divot) in the technical process of existing formation STI.Because the existence at the little angle of depression at STI edge; Usually cause in the process of metal silicide (Silicide) growth deposition, extending below along the little angle of depression; As shown in Figure 1; The metal silicide that is formed at N+ layer and P+ layer is that the P trap is that the N trap links to each other with NW to extending below with its corresponding PW all respectively, and this can cause leakage current (Leakage) to increase, and influences isolation effect.For some small size devices, this will be very serious problem.

Summary of the invention

Technical problem to be solved by this invention provides a kind of shallow ditch non-intercommunicating cells, can prevent element leakage, strengthen isolation effect.

For solving the problems of the technologies described above, shallow ditch non-intercommunicating cells provided by the invention is made up of the two parts up and down that vertically join, and the lower part width is greater than the top width, and said top width is greater than 0.1 micron; The degree of depth of said shallow ditch non-intercommunicating cells adopts following steps to form less than

:

Step 1, the photoetching of doing top width isolation channel, etching, etching depth removes photoresist less than the degree of depth of said shallow ditch non-intercommunicating cells;

Step 2, deposit one deck thin oxide layer, thickness is in ;

Step 3, utilize etching technics that sidewall oxide is removed, stayed to the oxide layer of trench bottom;

Step 4, do the isotropic etching of dry method, finally reach the degree of depth of said shallow ditch non-intercommunicating cells after the etching;

Step 5, removal sidewall oxide; The linear oxide layer of growing; Thickness is in

; Preferentially be chosen in 200～

then, do the deposit of high-density plasma oxide layer.

The present invention is through increasing an active area etching, can the top shallow isolating trough narrower than the bottom, thus solved effectively in the process of metal silicide growth deposition along the STI edge to extending below element leakage and the problem of isolating variation of causing.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:

Fig. 1 is existing shallow ditch non-intercommunicating cells structural representation;

Fig. 2 is a shallow ditch non-intercommunicating cells structural representation of the present invention;

Fig. 3 is a shallow isolating trough groove tank manufacturing method flow chart of the present invention;

Fig. 4 A-Fig. 4 G is the structural representation in the shallow ditch non-intercommunicating cells manufacture process of the present invention.

Embodiment

As shown in Figure 2, be shallow ditch non-intercommunicating cells structural representation of the present invention, to form by the two parts up and down that vertically join, the lower part width is greater than the top width, and said top width is greater than 0.1 micron; The degree of depth of said shallow ditch non-intercommunicating cells less than

wherein top be in N+ layer and the P+ layer and be not connected with P trap and N trap; The marginal trough problem only is present in said top; The metal silicide that is formed at said N+ layer and P+ layer can only extend downwardly into the bottom on said top at most; Can not link to each other with P trap, N trap; Thereby solved the problem that leakage current increases, improved isolation effect.

As shown in Figure 3, be shallow isolating trough groove tank manufacturing method flow chart of the present invention, step is following:

Step 1, shown in Fig. 4 A, do photoetching, the etching of top width isolation channel, etching depth removes photoresist less than the degree of depth of said shallow ditch non-intercommunicating cells;

Step 2, shown in Fig. 4 B; Deposit one deck thin oxide layer, thickness is in

;

Step 3, shown in Fig. 4 C, utilize etching technics that sidewall oxide is removed, stayed to the oxide layer of trench bottom;

Step 4, shown in Fig. 4 D, do the isotropic etching of dry method, finally reach the degree of depth of said shallow ditch non-intercommunicating cells after the etching;

Step 5, shown in Fig. 4 E, remove sidewall oxide; Shown in Fig. 4 F; Long linear oxide layer; Thickness is in

; Preferentially be chosen in 200～ shown in Fig. 4 G; Then, do the deposit of high-density plasma oxide layer.

More than through specific embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.

Claims

1. shallow ditch non-intercommunicating cells, it is characterized in that: the two parts up and down by vertically joining are formed, and the lower part width is greater than the top width, and wherein top is in N+ layer and the P+ layer and is not connected with P trap and N trap, adopts following steps to form:

Step 2, deposit one deck thin oxide layer, thickness is in

;

; Then, do the deposit of high-density plasma oxide layer.

2. shallow ditch non-intercommunicating cells as claimed in claim 1 is characterized in that: said linear thickness of oxide layer is

to step 5

3. shallow ditch non-intercommunicating cells as claimed in claim 1 is characterized in that: said top width is greater than 0.1 micron; The degree of depth of said shallow ditch non-intercommunicating cells is less than