CN102222696B - 高电压垂直晶体管的分段式柱布局 - Google Patents

高电压垂直晶体管的分段式柱布局 Download PDF

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CN102222696B
CN102222696B CN201110153406.XA CN201110153406A CN102222696B CN 102222696 B CN102222696 B CN 102222696B CN 201110153406 A CN201110153406 A CN 201110153406A CN 102222696 B CN102222696 B CN 102222696B
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V·帕塔萨拉蒂
W·B·格拉波夫斯基
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Abstract

本发明涉及高电压垂直晶体管的分段式柱布局。在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分，和设置在与第一区域相邻的半导体管芯的第二区域中的晶体管段的第二部分。第一和第二部分中的每个晶体管段包括沿垂直方向延伸的半导体材料柱。第一和第二介电区域设置在所述柱的相对侧上。第一和第二场板分别设置在所述第一和第二介电区域中。与第一和第二部分邻接的晶体管段的外场板被分开或者被部分地合并。

Description

高电压垂直晶体管的分段式柱布局
本申请是申请日为2008年2月8日、申请号为200810080754.7、发明名称为“高电压垂直晶体管的分段式柱布局”的发明专利申请的分案申请。
技术领域
本发明涉及用于制造高电压晶体管的半导体器件结构和工艺。
背景技术
在半导体领域中高电压场效应晶体管(HVFET)已是公知的。很多HVFET采用的器件结构包括延伸的漏极区，当器件处于“截止”状态时，该延伸的漏极区支持或阻断所施加的高电压(例如几百伏)。在常规的垂直HVFET结构中，半导体材料的台或柱形成用于导通状态中的电流的延伸的漏极或漂移区。在衬底顶部附近、与台的侧壁区域相邻地形成沟槽栅极结构，在台处将本体区设置在延伸的漏极区上方。向栅极施加适当的电压电势沿着本体区的垂直侧壁部分形成导电沟道，使得电流可以垂直流过半导体材料，即，从设置源极区的衬底顶表面向下流到设置漏极区的衬底底部。
在常规布局中，垂直HVFET由长的连续硅柱结构构成，该硅柱结构跨越半导体管芯延伸，并且该柱结构在垂直于柱长度的方向上重复。不过，该布局引起的问题在于，在高温处理步骤期间硅晶片容易产生大的翘曲。在很多工艺中，翘曲是永久性的且足够大，防碍了在下一处理步骤中用工具加工晶片。
发明内容
根据本发明的一个实施例，提供一种装置，包括：设置在管芯上的多个晶体管段，每个晶体管段具有跑道形状，所述跑道形状具有沿第一横向伸长的长度和沿第二横向的宽度，每个晶体管段包括：半导体材料柱，所述柱包括延伸漏极区，所述延伸漏极区通过所述管芯沿垂直方向延伸；分别设置在所述柱的相对侧上的第一和第二介电区域，所述第一介电区域由所述柱横向包围，并且所述第二介电区域横向包围所述柱；分别设置在所述第一和第二介电区域中的第一和第二场板；其中所述晶体管段被设置成多个部分，第一部分包括沿第二横向设置成并排关系的第一行晶体管段，以及第二部分包括沿第二横向设置成并排关系的第二行晶体管段。
根据本发明的另一个实施例，提供一种装置，包括：设置在管芯上的多个晶体管段，每个晶体管段具有跑道形状，所述跑道形状具有沿第一横向伸长的长度和沿第二横向的宽度，每个晶体管段包括：半导体材料柱，所述柱包括延伸漏极区，所述延伸漏极区通过所述管芯沿垂直方向延伸；分别设置在所述柱的相对侧上的第一和第二介电区域，所述第一介电区域由所述柱横向包围，并且所述第二介电区域横向包围所述柱；分别设置在所述第一和第二介电区域中的第一和第二场板；其中所述晶体管段被设置成多个部分，第一部分的晶体管段沿第一横向相对于第二部分的晶体管段移动，且第一部分的一行的每个晶体管段被第二部分的一对晶体管段分开，所述对沿第一横向设置成端到端的关系，第一和第二部分中的交替的晶体管段的第二介电区域被合并。
根据本发明的另一个实施例，提供一种晶体管，包括：半导体管芯；被设置成基本覆盖所述半导体管芯的多个晶体管段，每个晶体管段具有沿第一横向伸长的长度和沿第二横向的宽度，所述长度大于所述宽度至少20倍，每个晶体管段包括：半导体材料柱，所述柱包括延伸漏极区，所述延伸漏极区通过所述半导体管芯沿垂直方向延伸，所述柱沿第一和第二横向延伸以形成连续的跑道形环或椭圆；分别设置在所述柱的相对侧上的第一和第二介电区域，所述第一介电区域由所述柱横向包围，并且所述第二介电区域横向包围所述柱；分别设置在所述第一和第二介电区域中的第一和第二场板；并且其中所述晶体管段设置成位于半导体管芯的相应区域中的两个或更多个部分。
根据本发明的另一个实施例，提供一种制造在半导体管芯上的晶体管，包括：设置在半导体管芯的第一区域中的晶体管段的第一部分；设置在与第一区域相邻的半导体管芯的第二区域中的晶体管段的第二部分，第一和第二部分中的每个晶体管段包括：沿垂直方向延伸的半导体材料柱，所述柱具有在所述管芯的顶表面附近设置的源极区，和在所述源极区下面设置的延伸漏极区，所述柱沿第一和第二横向延伸以形成连续的跑道形环或椭圆；分别设置在所述柱的相对侧上的第一和第二介电区域，所述第一介电区域由所述柱横向包围，并且所述第二介电区域横向包围所述柱；分别设置在所述第一和第二介电区域中的第一和第二场板；并且其中第一和第二部分的成对的相邻晶体管段的第二场板被分别分开或者被部分地合并。
根据本发明的另一个实施例，提供一种半导体器件，包括：设置在管芯上的多个晶体管段，每个晶体管段具有跑道形状，所述跑道形状具有沿第一横向伸长的长度和沿第二横向的宽度，每个晶体管段包括：半导体材料柱，所述柱包括延伸漏极区，所述延伸漏极区通过所述管芯沿垂直方向延伸；分别设置在所述柱的相对侧上的第一和第二介电区域，所述第一介电区域由所述柱横向包围，并且所述第二介电区域横向包围所述柱；分别设置在所述第一和第二介电区域中的第一和第二场板；其中，所述晶体管段被设置成多个部分，第一部分包括沿第二横向设置成并排关系的第一行晶体管段，第二部分包括沿第二横向设置成并排关系的第二行晶体管段，所述第一和第二部分的晶体管段每个沿第一横向被多个半导体材料伪柱分开，每个伪柱中心分别位于第一和第二部分的第一和第二相邻成对的晶体管段的圆形端之间。
根据本发明的另一个实施例，提供一种半导体器件，包括：设置在管芯上的多个晶体管段，每个晶体管段具有跑道形状，所述跑道形状具有沿第一横向伸长的长度和沿第二横向的宽度，每个晶体管段包括：半导体材料柱，所述柱包括延伸漏极区，所述延伸漏极区通过所述管芯沿垂直方向延伸；分别设置在所述柱的相对侧上的第一和第二介电区域，所述第一介电区域由所述柱横向包围，并且所述第二介电区域横向包围所述柱；分别设置在所述第一和第二介电区域中的第一和第二场板；其中，所述晶体管段被设置成多个部分，第一部分包括沿第二横向设置成并排关系的第一行晶体管段，第二部分包括沿第二横向设置成并排关系的第二行晶体管段，第一部分的每个晶体管段的第二介电区域被合并，第二部分的每个晶体管段的第二介电区域被合并，第一部分的经合并的第二介电区域和第二部分的经合并的第二介电区域沿第一横向被伪半导体材料柱分开。
附图说明
从下面的详细说明和附图将可以更全面地理解本发明，不过，详细说明和附图不应用来将本发明限制到所示的具体实施例，而是仅用于解释和理解。
图1示出了垂直HVFET结构的实例截面侧视图。
图2A示出了图1中所示的垂直HVFET结构的实例布局。
图2B为图2A中所示的实例布局的一部分的放大视图。
图3A示出了图1中所示的垂直HVFET结构的另一实例布局。
图3B为图3A中所示的实例布局的一部分的放大视图。
图4A示出了图1中所示的垂直HVFET结构的又一实例布局。
图4B为图4A中所示的实例布局的一部分的放大视图。
具体实施方式
在下述说明中，为了提供对本发明的透彻理解，给出了具体细节，例如材料类型、尺寸、结构特点、处理步骤等。不过，本领域的普通技术人员将理解，实施本发明可以不需要这些具体细节。还应理解，图中的元件是代表性的，为了清晰起见没有按照比例绘制。
图1示出了垂直HVFET10的实例截面侧视图，该HVFET10具有这样的结构，其包括形成于N+掺杂硅衬底11上的N型硅的延伸漏极区12。对衬底11进行重掺杂以使其对流经漏电极的电流的电阻最小化，在完成的器件中漏电极位于衬底的底部上。在一个实施例中，延伸漏极区12为从衬底11延伸到硅晶片的顶表面的外延层的一部分。接近外延层的顶表面形成P型本体区13以及被P型区域16横向分开的N+掺杂的源极区14a和14b。如可以看到的，P型本体区13设置于延伸漏极区12上方且垂直地将延伸漏极区12与N+源极区14a和14b以及P型区域16分开。
在一个实施例中，外延层包括延伸漏极区12的部分的掺杂浓度是线性渐变的，以产生表现出基本均匀的电场分布的延伸漏极区。线性渐变可以在外延层12的顶表面下方的某个点处停止。
在图1的实例垂直晶体管中，延伸漏极区12、本体区13、源极区14a和14b以及P型区域16共同包括硅材料的台或柱17(在本申请中两个术语作为同义词使用)。用介电材料(例如氧化物)层填充形成于柱17的相对侧上的垂直沟槽，所述介电材料形成介电区域15。可以由器件的击穿电压要求决定柱17的高度和宽度以及相邻垂直沟槽之间的间距。在各实施例中，台17的垂直高度(厚度)在大约30μm到120μm厚的范围内。例如，在尺寸大约为1mm×1mm的管芯上形成的HVFET可以具有垂直厚度为大约60μm的柱17。作为另一实例，在每一侧的大约2mm-4mm的管芯上形成的晶体管结构可以具有大约30μm厚的柱结构。在特定实施例中，柱17的横向宽度尽量窄到能可靠制造的程度(例如大约0.4μm到0.8μm宽)，以便实现非常高的击穿电压(例如600-800V)。
在另一实施例中，不是跨越柱17的横向宽度在N+源极区14a和14b之间布置P型区域16(如图1所示)，而是可以跨越柱17的横向长度在柱17的顶部交替形成N+源极区和P型区域。换句话说，诸如图1中所示的给定的截面图将具有跨越柱17的整个横向宽度延伸的N+源极区14或P型区域16，取决于该截面取自哪里。在这样的实施例中，每个N+源极区14在两侧(沿柱的横向长度)与P型区域16邻接。类似地，每个P型区域16在两侧(沿柱的横向长度)与N+源极区14邻接。
介电区域15a、15b可以包括二氧化硅、氮化硅或其他合适的介电材料。可以使用多种公知方法，包括热生长和化学汽相淀积来形成介电区域15。设置在每个介电层15中并与衬底11和柱17完全绝缘的是场板(field plate)19。用于形成场板19的导电材料可以包括重掺杂的多晶硅、金属(或金属合金)、硅化物或其他适当的材料。在完成的器件结构中，场板19a和19b通常起电容极板的作用，当HVFET处于截止状态时(即当漏极被升高至高电压电势时)所述电容极板可用于耗尽延伸漏极区的电荷。在一个实施例中，将每个场板19与柱17的侧壁分开的氧化物区域15的横向厚度大约为4μm。
垂直HVFET晶体管80的沟槽栅极结构包括栅极元件18a、18b，每个栅极元件分别设置在场板19a、19b和本体区13之间、柱17的相对侧上的氧化物区域15a和15b中。高质量的薄(例如)栅极氧化物层将栅极元件18与和本体区13相邻的柱17的侧壁分开。栅极元件18可以包括多晶硅、或某种其他适合的材料。在一个实施例中，每个栅极元件18具有大约1.5μm的横向宽度和大约3.5μm的深度。
本领域的实践人员将会理解，柱17的顶部附近的N+源极区14和P-型本体区13均可以使用普通的淀积、扩散和/或注入处理技术形成。在形成N+源极区38之后，通过利用常规制造方法形成电连接到器件的相应区域/材料(为了清晰图中未示出)的源、漏、栅、和场板电极可以完成HVFET10。
图2A示出了图1中所示的垂直HVFET结构的实例布局。图2A的顶视图示出了单个分立的HVFET，其包括半导体管芯21上的上部晶体管部分30a和下部晶体管部分30b。由伪硅柱32将这两部分分开。每个部分30包括多个“跑道(racetrack)”形晶体管结构或段，每个晶体管段包括细长环或椭圆，其包括在相对侧由介电区域15a和15b包围的硅柱17。柱17本身在x和y方向上横向延伸以形成连续细长的跑道形环或椭圆。设置在介电区域15a和15b中的是相应的栅极元件18a和18b以及场板19a和19b。场板19a包括单个细长元件，其在圆形指尖(fingertip)区域中终结于任一端。另一方面，场板19b包括环绕柱17的细长环或椭圆。相邻跑道结构的场板19b被示为合并的(merged)，从而它们共享在一侧的公共元件。作为参考，图1的截面图可以取自图2A的实例布局的切割线A-A’。
应当理解，在图2A的实例中，每个跑道形晶体管段在y方向上的宽度(即间距)大约为13μm，在x方向上的长度在大约400μm到1000μm的范围内，且柱高度约为60μm。换句话说，包括部分30a和30b的各个跑道形晶体管段的长宽比在大约30直到80的范围内。在一个实施例中，每个跑道形段的长度大于其间距或宽度至少20倍。
本领域的实践人员将理解，在完成的器件结构中，使用图案化金属层来互连各个晶体管段的每个硅柱17。也就是说，在实际实施例中，分别将所有的源极区、栅极元件和场板一起布线至管芯上对应的电极。在图示的实施例中，每个部分30中的晶体管段基本跨越管芯21的宽度沿y方向设置成并排关系。类似地，在x方向上，部分30a和30b的晶体管段的额外长度基本在管芯21的长度上延伸。在图2A的实例布局中，跨越半导体管芯21，分开硅柱的介电区域15的宽度以及场板的宽度是基本均匀的。以均匀的宽度和间隔距离布置晶体管段防止了在用于共形地淀积包括介电区域15和场板19的层的处理步骤之后形成空隙或孔。
图2B为图2A中所示的实例布局的一部分的放大视图。为了清晰起见，仅示出了每个晶体管段的柱17和介电区域15b。图示的伪硅柱32分开相应晶体管段部分30a和30b的介电区域15b的圆端区域。换句话说，在半导体衬底中被蚀刻来限定柱17的深垂直沟槽也限定伪硅柱32。在一个实施例中，使伪硅柱32在x方向上的宽度(即其分开晶体管段部分)小到能被可靠地制造。
将单个管芯HVFET分段成由伪硅柱32分开的部分的目的在于在细长跑道形晶体管段中引入长度方向上(x方向)的应力消除(stressrelief)。将晶体管器件结构分段或断开成两个或更多个部分减轻了跨越管芯长度的机械应力。该应力由位于柱侧面的氧化物区域引起，并且通常集中于每个跑道形段的圆形端处。由此通过将晶体管器件结构分段成两个或更多个部分来减轻机械应力防止了由应力导致的不希望有的硅柱翘曲和对硅的损伤(例如位错)。
要理解的是，在通过高度分段的布局提供的应力消除和导电区域的损失之间存在折衷。更多的分段导致更大的应力减轻，但是以导电区域为代价。通常，柱的垂直高度越大且半导体管芯越大，则需要的晶体管部分或段的数目越大。在一个实施例中，对于具有60μm高的柱的2mm×2mm的管芯，利用包括四个跑道形晶体管部分的布局在导通电阻约为1欧姆的HVFET中提供足够的应力减轻，所述四个跑道形晶体管部分由伪硅柱分开，每个伪硅柱具有大约13μm的间距(y方向)和大约450μm的长度(x方向)。
在另一个实施例中，不是用伪硅柱来分开成对的跑道形晶体管段，每一对位于不同部分中，而是可以用包括不同材料的伪柱。用于伪柱的材料应当具有接近硅的热膨胀系数或充分不同于介电区域的热膨胀系数的热膨胀系数以便减轻由位于硅柱侧面的介电区域引起的长度方向上的应力。
图3A示出了图1所示的垂直HVFET结构的另一实例布局。图3B为图3A中所示的实例布局的一部分的放大图，仅示出了柱17、氧化物区域15b和可选的伪硅柱33。类似于图2A和2B的实施例，图3A和3B示出了半导体管芯21上的单个分立的HVFET，其包括上部晶体管部分30a和下部晶体管部分30b。但是在图3A和3B的实例中，由氧化物区域15b填充的深垂直沟槽以及晶体管部分30a和30b的场板19b重叠，或者被合并，在分段的晶体管部分之间留下小的菱形伪硅柱33。在该实施例中，单个伪柱中心位于两个部分上相邻成对的晶体管段的四个圆形端之间。在所示的实例中，对于包括管芯21的晶体管部分30中的每N个(其中N为大于1的整数)跑道形段或结构，存在总共N-1个伪柱33。
图4A示出了图1所示的垂直HVFET结构的又一实例布局。图4B为图4A中所示的实例布局的一部分的放大图。在图4B的放大图中为了清晰仅示出了柱17和氧化物区域15b。在该实例中，将半导体管芯21的包括HVFET的晶体管段交替移动每个跑道形段的长度的一半，结果形成交替与上部晶体管部分40a和下部晶体管部分40b相关联的跑道形晶体管段。换句话说，一行部分40a的每个晶体管段由部分40b的一对晶体管段分开，该对晶体管段沿x方向设置成端到端的关系。
要理解的是，可以将各段交替移动段长度的任何百分数(fraction)。换句话说，段的移动不限于长度的50％或一半。多种实施例可以包括交替移动了晶体管段的长度的从大于0％到小于100％的任何百分比或百分数的段。
在图4A和4B的实例中，相应部分40a和40b中交替的晶体管段的介电区域15b被合并。在图示的具体实施例中，与不同相邻部分相关联的晶体管段的圆形端重叠或被合并，使得相邻部分的场板19b在各端处(沿x方向)被合并。而且，不同部分的交替晶体管段的场板19b的延伸的直边部分沿着每个段的基本长度被合并。要理解的是，区域15b和19b在相应部分之间有或没有伪柱(或隔离的伪硅柱)的情况下都可以被合并。
虽然已经结合具体器件类型描述了以上实施例，但是本领域的普通技术人员将理解多种变型和改变都在本发明的范围内。例如，虽然已经描述了HVFET，但是图示的方法、布局和结构同样适用于其他结构和器件类型，包括肖特基、二极管、IGBT和双极型结构。因此，应当将说明书和附图看作是示例性的而不是限制性的。

Claims (8)

1.一种半导体器件，包括：
设置在管芯上的多个晶体管段，每个晶体管段具有跑道形状，所述跑道形状具有沿第一横向伸长的长度和沿第二横向的宽度，每个晶体管段包括：
半导体材料柱，所述柱包括延伸漏极区，所述延伸漏极区通过所述管芯沿垂直方向延伸；
分别设置在所述柱的相对侧上的第一和第二介电区域，所述第一介电区域由所述柱横向包围，并且所述第二介电区域横向包围所述柱；
分别设置在所述第一和第二介电区域中的第一和第二场板；
其中，所述晶体管段被设置成多个部分，第一部分包括沿第二横向设置成并排关系的第一行晶体管段，第二部分包括沿第二横向设置成并排关系的第二行晶体管段，所述第一和第二部分的晶体管段每个沿第一横向被多个半导体材料伪柱分开，每个伪柱中心分别位于第一和第二部分的第一和第二相邻成对的晶体管段的圆形端之间。
2.根据权利要求1所述的半导体器件，其中，所述柱还包括在所述管芯的顶表面附近设置的源极区，以及将所述源极区与所述延伸漏极区垂直地分开的本体区。
3.根据权利要求2所述的半导体器件，还包括与所述本体区相邻的在第一和第二介电区域中设置的栅极，所述栅极与所述本体区和所述第一和第二场板绝缘。
4.根据权利要求1所述的半导体器件，其中，第一和第二部分均沿第二横向跨越管芯的宽度而延伸，第一部分和第二部分附加地沿第一横向跨越管芯的长度而延伸。
5.一种半导体器件，包括：
设置在管芯上的多个晶体管段，每个晶体管段具有跑道形状，所述跑道形状具有沿第一横向伸长的长度和沿第二横向的宽度，每个晶体管段包括：
半导体材料柱，所述柱包括延伸漏极区，所述延伸漏极区通过所述管芯沿垂直方向延伸；
分别设置在所述柱的相对侧上的第一和第二介电区域，所述第一介电区域由所述柱横向包围，并且所述第二介电区域横向包围所述柱；
分别设置在所述第一和第二介电区域中的第一和第二场板；
其中，所述晶体管段被设置成多个部分，
第一部分包括沿第二横向设置成并排关系的第一行晶体管段，第二部分包括沿第二横向设置成并排关系的第二行晶体管段，第一部分的每个晶体管段的第二介电区域被合并，第二部分的每个晶体管段的第二介电区域被合并，第一部分的经合并的第二介电区域和第二部分的经合并的第二介电区域沿第一横向被伪半导体材料柱分开，
其中，每个跑道形状的晶体管段的长度大于其宽度至少20倍。
6.根据权利要求5所述的半导体器件，其中，第一和第二部分均沿第二横向跨越管芯的宽度而延伸，第一部分和第二部分附加地沿第一横向跨越管芯的长度而延伸。
7.根据权利要求5所述的半导体器件，其中，所述柱还包括在所述管芯的顶表面附近设置的源极区，以及将所述源极区与延伸漏极区垂直地分开的本体区。
8.根据权利要求7所述的半导体器件，还包括与所述本体区相邻的在第一和第二介电区域中设置的栅极，所述栅极与所述本体区和所述第一和第二场板绝缘。
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US20090134457A1 (en) 2009-05-28
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