CN102402633A - Method for establishing parameterized device physics territory unit generating program - Google Patents

Method for establishing parameterized device physics territory unit generating program Download PDF

Info

Publication number
CN102402633A
CN102402633A CN2010102850106A CN201010285010A CN102402633A CN 102402633 A CN102402633 A CN 102402633A CN 2010102850106 A CN2010102850106 A CN 2010102850106A CN 201010285010 A CN201010285010 A CN 201010285010A CN 102402633 A CN102402633 A CN 102402633A
Authority
CN
China
Prior art keywords
array
relation
basic physical
array pattern
coordinate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010102850106A
Other languages
Chinese (zh)
Other versions
CN102402633B (en
Inventor
吴玉平
陈岚
叶甜春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN 201010285010 priority Critical patent/CN102402633B/en
Publication of CN102402633A publication Critical patent/CN102402633A/en
Application granted granted Critical
Publication of CN102402633B publication Critical patent/CN102402633B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

The invention discloses a method for establishing a parameterized device physics territory unit generating program, belonging to the technical field of integrated circuit design automation. The method comprises the steps of: inputting physical graphs of a device by using a graph editor, and marking out a design rule parameter among the graphs, a congruent relation ship between a device parameter and the graphs, and an item zone on the physical graphs; scanning the physical graphs and determining the position relationship and the position dependency relationship among basic physical graphs; and establishing a generation sequence and a program flow of each basic physical graph according to the position relationship and the position dependency relationship among the basic physical graphs to generate a program. According to the invention, the parameterized device physics territory unit generating program can be generated automatically.

Description

A kind of method of setting up parametrization device physics domain unit generator program
Technical field
The present invention relates to the IC design technical field of automation, particularly a kind of method of setting up parametrization device physics domain unit generator program.
Background technology
Device physics domain unit design is the important step of Analogous Integrated Electronic Circuits design.For the design of faster devices physical pattern unit, generally adopt parametrization device physics domain unit generator program.For the consistent same types of devices of physical arrangement; By means of parametrization device physics domain unit generator program; Import the physical pattern unit that concrete device parameters value promptly can generate respective devices automatically; Can avoid the physical layout of the hand-designed device of repeatability like this, thereby improve design efficiency, need set up parametrization device physics domain unit generator program for this reason.
At present, set up parametrization device physics domain unit generator program and mainly contain two kinds of methods: the one, the peopleware analyzes manual written-out program according to the device physics domain to hand-designed, and its shortcoming is an inefficiency, and the code maintenance difficulty; Another kind method is to utilize program that the fundamental figure of forming the device physical layout is carried out scanning analysis; According to analysis result; Interactively adds parameter, and its shortcoming is to support the retractility of device effectively, and the fundamental figure generating algorithm is simply based on coordinate; Support parameterization well, the code of generation are difficult to safeguard and use.Therefore need improve to overcome these shortcomings this existent method.
Summary of the invention
In order to solve that the existing method efficient of setting up device physics domain unit generator program is low, code maintenance is difficult and problem such as support parameterization well; The invention provides a kind of method of setting up parametrization device physics domain unit generator program, said method comprises:
Utilize the physical graph of graphic editor entering apparatus, go out the corresponding relation and the option area of design rule parameter, device parameters and figure between figure and the figure at said physical graph subscript;
Scan said physical graph, confirm position relation and position dependence between the basic physical graph;
According to relation of the position between the said basic physical graph and position dependence, set up the genesis sequence and the program circuit of each basic physical graph, generator program.
Said method also comprises adds the figure coordinate relocatable program, specifically comprises: all basic physical graphs of traversal device physical layout calculate horizontal stroke, the minimum coordinate points of ordinate; The reference origin of said device physics domain is moved to said horizontal stroke, the minimum coordinate points of ordinate.
The said step of confirming that the position between the basic physical graph concerns specifically comprises:
According to the area magnitude relationship of each basic physical graph, confirm the encirclement relation between each basic physical graph;
Said basic physical graph is carried out accessible figure and the analysis of obstacle graphic array is arranged;
Said basic physical graph is carried out left and right sides ordinal relation and ordinal relation analysis up and down.
The said step that said basic physical graph is carried out accessible graphic array analysis specifically comprises:
According between the basic physical graph up and down and/or between left and right apart from consistance, basic physical graph is polymerized to one or several one dimensions or two-dimensional array figure;
According to the extension direction of said one dimension or two-dimensional array figure, confirm the figure figurate number of accessible graphic array;
Set up the spacing of said one dimension or two-dimensional array figure and the relation between design rule parameter and the device parameters.
Said extension direction according to the one-dimensional array figure confirms that the step of the figure figurate number of accessible graphic array is specially: the figure figurate number of one-dimensional array figure extension direction=(spacing between the device parameters of corresponding extension direction-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of extension direction).
The step of the relation between the said spacing of setting up said one-dimensional array figure and design rule parameter and the device parameters is specially: the distance values between the said one-dimensional array figure=(spacing-array pattern between the device parameters of corresponding extension direction-2 * array pattern and the outsourcing figure the physical dimension * counterparty of this direction to the figure figurate number)/(counterparty to figure figurate number-1).
Said extension direction according to said two-dimensional array figure; The step of confirming the figure figurate number of accessible graphic array is specially: said two-dimensional array figure is in the figure of directions X figurate number=(spacing between the device parameters of corresponding directions X-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of directions X), and said two-dimensional array figure is in the figure of Y direction figurate number=(spacing between the device parameters of corresponding Y direction-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of Y direction).
The step of the relation between the said spacing of setting up the two-dimensional array figure and design rule parameter and the device parameters is specially: the distance values of directions X between the said two-dimensional array figure=(spacing-array pattern between the device parameters of corresponding directions X-2 * array pattern and the outsourcing figure is in the figure of the physical dimension * directions X of directions X figurate number)/(the figure figurate number-1 of directions X), the spacing of Y direction between the said two-dimensional array figure=(spacing-array pattern between the device parameters of corresponding Y direction-2 * array pattern and the outsourcing figure is in the figure figurate number of the physical dimension * Y direction of Y direction)/(the figure figurate number-1 of Y direction).
The said step that said basic physical graph is carried out left and right sides ordinal relation analysis specifically comprises:
Confirm the alignment thereof of said basic physical graph, said alignment thereof comprises coboundary vertical line alignment, the alignment of central horizontal line, the alignment of lower boundary vertical line and does not have alignment up and down;
With the point coordinate value in its lower left corner of minimum boundary rectangle of array point figure left margin coordinate figure as this array point; Confirm the left and right sides ordinal relation between the array pattern according to the magnitude relationship of X coordinate figure in the left margin coordinate figure; The little array point of X coordinate figure is on a left side, and the big array point of X coordinate figure is on the right side.
The said step that said basic physical graph is carried out up and down ordinal relation analysis specifically comprises:
Confirm the alignment thereof of said basic physical graph, said alignment thereof comprise left margin vertical line alignment, the alignment of center vertical line, the alignment of right margin vertical line and about do not have alignment;
With the point coordinate value in its lower left corner of minimum boundary rectangle of array point figure lower boundary coordinate figure as this array point; Confirm the ordinal relation up and down between the array pattern according to the magnitude relationship of Y coordinate figure in the lower boundary coordinate figure; The little array point of Y coordinate figure is down, and the big array point of Y coordinate figure is last.
The step of the position dependence between said definite basic physical graph specifically comprises:
Encirclement relation according to each basic physical graph is set up the tree-like relation of father and son of stratification;
According to the left and right sides ordinal relation of basic physical graph and up and down ordinal relation set up with the fraternal tree-like relation of layer;
Set up the position dependence between root and the leaf from the bottom of tree derivation;
Set up with the position dependence between the layer leaf figure from same figure of tree derivation.
The step of said creation facilities program (CFP) flow process specifically comprises:
According to said graphic array analysis, the figure of graphic array and array point is generated as a sub-flow process;
Dimension and size according to graphic array in father's flow process are set up loop body, in loop body, calculate and respectively generate required reference position of each array point and input parameter;
Array pattern to generating is shifted according to RP;
Surround relation according to said basic physical graph, make up sub-process and generate besieged figure.
Compared with prior art, the present invention has the following advantages:
The present invention can seek the dependence between proximity relations between the figure, covering relation, the graph position, the ordinal relation that figure generates, the dependence between the dimension of picture etc. automatically according to the device physics layout data; And then generate parametrization device physics domain unit generator program automatically; Need not the user and confirm the above-mentioned relation data by hand, accelerated the exploitation of parametrization device physics domain unit.
Description of drawings
Fig. 1 is the method flow diagram of setting up parametrization device physics domain unit generator program that the embodiment of the invention provides.
Embodiment
In order to understand the present invention in depth, the present invention is elaborated below in conjunction with accompanying drawing and specific embodiment.
Referring to Fig. 1, the embodiment of the invention provides a kind of method of setting up parametrization device physics domain unit generator program, comprises the steps:
Step 101: the physical graph that utilizes the graphic editor entering apparatus;
The physical layout of device is made up of the some basic physical graph that is closely related with device architecture; Each basic physical graph comprises information such as type, coordinate points and process layer, utilizes graphic editor to import the information such as process layer at the type of basic physical graph, coordinate points and basic physical graph place;
Step 102: go out the design rule parameter of figure, corresponding relation and the option area etc. of design rule parameter, device parameters and figure between the figure at the physical graph subscript;
Step 103: scan basic physical graph, confirm the position relation between the basic physical graph;
Position relation between the basic physical graph comprises:
1, figure surrounds relationship analysis
Figure A is surrounded by another figure B on how much fully, and promptly A is in B, and we are referred to as figure A and are subordinated to figure B, and figure surrounds the judgement of relation and can confirm according to the simple plane geometrical calculation;
2, array pattern relationship analysis
Array relation comprise other figures are arranged between the accessible array pattern that do not have other figures between the array point and the array point the obstacle array pattern arranged;
2.1 accessible array pattern analysis
2.1.1 confirming of accessible array pattern: for having the identical basic physical graph of the shape and size parameter that belongs to same process layer that same direct father surrounds; About between the basic physical graph of foundation and/or between left and right apart from consistance, these basic physical graphs are polymerized to one or several one dimensions or two-dimensional array figure; It should be noted that does not have figure at the same level or advanced figure to isolate between the array pattern;
2.1.2 surround concern reconstruct: with the figure in virtual these array patterns of the circumscribed covering of grand plan shape; With the array pattern in this direct father's encirclement of this virtual grand plan shape replacement; Just, surround the virtual grand plan shape of increase one deck between figure and the former array pattern same direct father;
2.1.3 confirm the figure figurate number of accessible array pattern
2.1.3.1 for the one-dimensional array figure, the figure figurate number of array extension direction=(spacing between the device parameters of corresponding extension direction-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of extension direction);
2.1.3.2 for the two-dimensional array figure; In the figure of directions X figurate number=(spacing between the device parameters of corresponding directions X-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of directions X), in the figure of Y direction figurate number=(spacing between the device parameters of corresponding Y direction-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of Y direction);
2.1.4 set up the spacing of array pattern in the accessible array pattern and the relation between design rule parameter and the device parameters: the spacing between the accessible array pattern should satisfy maximum, minimum or the settled principle of design rule parameter, this depends on the design rule file that concrete technology is corresponding; Under the spacing settled principle, the distance values between the accessible array pattern is exactly the given numerical value of design rule file; In maximum, minimum principle but not under the settled principle; Distance values between the accessible array pattern except that with the design rule relating to parameters; Also relevant with the parameter value of device, this parameter is relevant with the outside figure that the restriction array extends, and seeks immediate figure along the array bearing of trend; Thereby seek out the device parameters of this figure of control, this device parameters is exactly the device parameters of indirect array of controls size;
For the one-dimensional array figure, the distance values between the accessible array pattern is: the distance values between the accessible array pattern=(spacing-array pattern between the device parameters of corresponding extension direction-2 * array pattern and the outsourcing figure the physical dimension * counterparty of this direction to the figure figurate number)/(counterparty to figure figurate number-1);
To the two-dimensional array figure; Spacing between the accessible array pattern is: the distance values of directions X between the accessible array pattern=(spacing-array pattern between the device parameters of corresponding directions X-2 * array pattern and the outsourcing figure is in the figure of the physical dimension * directions X of directions X figurate number)/(the figure figurate number-1 of directions X), the spacing of Y direction between the accessible array pattern=(spacing-array pattern between the device parameters of corresponding Y direction-2 * array pattern and the outsourcing figure is in the figure figurate number of the physical dimension * Y direction of Y direction)/(the figure figurate number-1 of Y direction);
2.2 the analysis of obstacle array pattern is arranged
There is the analysis of obstacle array pattern after accessible array pattern analysis, to carry out, have other figure obstacles between the array pattern, but the obstacle figure do not done any influence to these fundamental figure forming arrays; There is the dot matrix size of array pattern of obstacle relevant with device parameters;
2.2.1 confirming of obstacle array pattern: for having the identical figure of shape and size parameter that belongs to same process layer that same direct father surrounds; According between the obstacle array pattern up and down and/or between left and right apart from consistance, these obstacle array patterns are polymerized to one or several one dimensions or two-dimensional array figure; It should be noted that has figure at the same level or senior compound virtual pattern to isolate between the obstacle array pattern, constitute the array pattern of obstacle between the many fingers gate figure like MOSFET;
2.2.2 confirming of obstacle array of figure figurate number: for having the identical basic physical graph of the shape and size parameter that belongs to same process layer that same direct father surrounds; About between the basic physical graph of foundation and/or between left and right apart from consistance, these basic physical graphs are polymerized to one or several one dimensions or two-dimensional array figure; It should be noted that has figure at the same level or advanced figure to isolate between the array pattern; According to parameter identification, confirm the size of array with a device parameters or a plurality of device parameters again;
2.2.3 confirming of obstacle figure: the coordinate figure with the minimum boundary rectangle of figure is confirmed the figure between the array point figure; List the figure between the array point figure in the obstacle figure; The obstacle figure can be a fundamental figure; Also can be the array that fundamental figure is formed, can be directly linked to corresponding virtual grand plan shape;
2.2.4 confirm the distance values between the obstacle array pattern: distance values=obstacle figure is in size+2 * obstacle figure of figure spacing direction and the spacing between the array point figure;
2.3 array pattern left and right sides ordinal relation is analyzed
2.3.1 confirm the alignment thereof between the figure of the left and right sides in the array pattern: the alignment of coboundary vertical line, central horizontal line align, the lower boundary vertical line aligns and do not have alignment up and down;
2.3.2 with the point coordinate value in its lower left corner of minimum boundary rectangle of array point figure left margin coordinate figure as this array point; Confirm the left and right sides ordinal relation between the array pattern according to the magnitude relationship of X coordinate figure in the left margin coordinate figure; The little array point of X coordinate figure is on a left side, and the big array point of X coordinate figure is on the right side;
2.4 array pattern ordinal relation analysis up and down
2.4.1 confirm in the array pattern alignment thereof between the figure up and down: the alignment of left margin vertical line, the alignment of center vertical line, the alignment of right margin vertical line and about do not have alignment;
2.4.2 with the point coordinate value in its lower left corner of minimum boundary rectangle of array point figure lower boundary coordinate figure as this array point; Confirm the ordinal relation up and down between the array pattern according to the magnitude relationship of Y coordinate figure in the lower boundary coordinate figure; The little array point of Y coordinate figure is down, and the big array point of Y coordinate figure is last;
2.5 the analysis of the line figure between the array point
With the connected graph is the Analysis of Topological Structure of basis to line; Analyze the size of line figure in conjunction with design rule; Analyze the covering of line, thereby confirm the position reference figure of line figure figure; In conjunction with design rule, the relation between analysis line figure and other figures is to calculate spacing; Confirm the coordinate formula of line figure;
2.6 option pattern analysis
The option figure is controlled by the option parameter of control device physical layout, according to option sign and option parameter, is the option figure of this option parameter with the logotype in the option area;
Step 104: confirm the position dependence between each basic physical graph;
Set up the tree-like relation of father and son of stratification according to the figure relation of surrounding; Set up with a layer fraternal tree-like relation according to the left and right sides ordinal relation of basic physical graph and ordinal relation up and down; Set up the position dependence between root and the leaf from the bottom of tree derivation; Set up with the position dependence between the layer leaf figure from same of tree derivation figure, so as with one with the position of layer leaf figure as a reference, other move to the relative position place of regulation with layer leaf figure and inner body thereof;
Step 105: the genesis sequence of setting up each basic physical graph;
Set up the genesis sequence of basic physical graph according to relation, upper and lower relation, reference relation etc. about the hierarchical relationship of setting up, same level, its principle is:
1) according to hierarchical relationship: the inner bottom figure generates and surrounds figure prior to direct father;
2) according to reference relation: preferential by its genesis sequence of the figure of reference;
3) according to relation about same level: order generates from left to right;
4) according to the upper and lower relation of same level: order generates from the bottom up;
Step 106: creation facilities program (CFP) flow process;
1, the foundation of flow process stratification relation is surrounded relationship analysis according to array pattern analysis and figure: according to the array pattern analysis, with the figure generation of array pattern and array point as a sub-flow process; Dimension and size according to array pattern in father's flow process are set up loop body, in loop body, calculate and respectively generate required reference position of each array point and input parameter etc., call this sub-process, and then the array pattern that generates is shifted according to RP; Surround relation according to figure, make up sub-process and generate besieged figure;
2, the foundation of flow process relation in the same level
2.1, confirm that the order of program circuit is carried out relation according to the genesis sequence of basic physical graph;
2.2 make up condition judgment and condition execution branch according to option figure and controlled variable thereof, promptly judge nest relation;
2.3 make up the loop blocks flow process with array pattern, carry out the loop nesting relation;
2.4 according to the dependence between the fundamental figure, calculate position coordinates, and generate fundamental figure according to position coordinates with reference to figure;
Step 107: according to the program circuit generator program;
Utilize the order in the existing CASE technical basis flow process to carry out relation, judge that nest relation, loop nesting relation, redirect nest relation etc. are automatically converted to detailed source program code; The language of program can be SKILL, Tcl/tk, Python, C/C++ etc.; The fundamental figure generating function of calling in the source program is derived from the predefine of system;
Step 108: add figure translation program;
The lower left corner with the device housing is that reference origin (0,0) is one of basic demand of parametrization device physics domain, can realize through the figure translation; Specifically comprise: all fundamental figures of traversal device physical layout; Calculate (Xmin, Ymin) with (Xmax, Ymax); To the coordinate point value in the attribute of all fundamental figures (X, Y) change and replace (Xnew=X-Xmin, thus Ynew=Y-Ymin) reference origin is moved to original (Xmin, Ymin) point.
Above-described specific embodiment has carried out further explain to the object of the invention, technical scheme and beneficial effect.Will be appreciated that the above content is merely embodiment of the present invention, is not limited to the present invention.All within essence of the present invention and ultimate principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (12)

1. method of setting up parametrization device physics domain unit generator program is characterized in that said method comprises:
Utilize the physical graph of graphic editor entering apparatus, go out the corresponding relation and the option area of design rule parameter, device parameters and figure between figure and the figure at said physical graph subscript;
Scan said physical graph, confirm position relation and position dependence between the basic physical graph;
According to relation of the position between the said basic physical graph and position dependence, set up the genesis sequence and the program circuit of each basic physical graph, generator program.
2. the method for setting up parametrization device physics domain unit generator program as claimed in claim 1; It is characterized in that; Said method also comprises adds the figure coordinate relocatable program; Specifically comprise: all basic physical graphs of traversal device physical layout calculate horizontal stroke, the minimum coordinate points of ordinate; The reference origin of said device physics domain is moved to said horizontal stroke, the minimum coordinate points of ordinate.
3. according to claim 1 or claim 2 the method for setting up parametrization device physics domain unit generator program is characterized in that, saidly confirms that the step of the relation of the position between the basic physical graph specifically comprises:
According to the area magnitude relationship of each basic physical graph, confirm the encirclement relation between each basic physical graph;
Said basic physical graph is carried out accessible figure and the analysis of obstacle graphic array is arranged;
Said basic physical graph is carried out left and right sides ordinal relation and ordinal relation analysis up and down.
4. the method for setting up parametrization device physics domain unit generator program as claimed in claim 3 is characterized in that, the said step that said basic physical graph is carried out accessible graphic array analysis specifically comprises:
According between the basic physical graph up and down and/or between left and right apart from consistance, basic physical graph is polymerized to one or several one dimensions or two-dimensional array figure;
According to the extension direction of said one dimension or two-dimensional array figure, confirm the figure figurate number of accessible graphic array;
Set up the spacing of said one dimension or two-dimensional array figure and the relation between design rule parameter and the device parameters.
5. the method for setting up parametrization device physics domain unit generator program as claimed in claim 4; It is characterized in that; Said extension direction according to the one-dimensional array figure confirms that the step of the figure figurate number of accessible graphic array is specially: the figure figurate number of said one-dimensional array figure extension direction=(spacing between the device parameters of corresponding extension direction-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of extension direction).
6. the method for setting up parametrization device physics domain unit generator program as claimed in claim 5; It is characterized in that the step of the relation between the said spacing of setting up said one-dimensional array figure and design rule parameter and the device parameters is specially: the distance values between the said one-dimensional array figure=(spacing-array pattern between the device parameters of corresponding extension direction-2 * array pattern and the outsourcing figure the physical dimension * counterparty of this direction to the figure figurate number)/(counterparty to figure figurate number-1).
7. the method for setting up parametrization device physics domain unit generator program as claimed in claim 4; It is characterized in that; Said extension direction according to said two-dimensional array figure; The step of confirming the figure figurate number of accessible graphic array is specially: said two-dimensional array figure is in the figure of directions X figurate number=(spacing between the device parameters of corresponding directions X-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of directions X), and said two-dimensional array figure is in the figure of Y direction figurate number=(spacing between the device parameters of corresponding Y direction-2 * array pattern and the outsourcing figure)/(array pattern is in the array pattern minimum spacing of physical dimension+design rule permission of Y direction).
8. the method for setting up parametrization device physics domain unit generator program as claimed in claim 7; It is characterized in that; The step of the relation between the said spacing of setting up the two-dimensional array figure and design rule parameter and the device parameters is specially: the distance values of directions X between the said two-dimensional array figure=(spacing-array pattern between the device parameters of corresponding directions X-2 * array pattern and the outsourcing figure is in the figure of the physical dimension * directions X of directions X figurate number)/(the figure figurate number-1 of directions X), the spacing of Y direction between the said two-dimensional array figure=(spacing-array pattern between the device parameters of corresponding Y direction-2 * array pattern and the outsourcing figure is in the figure figurate number of the physical dimension * Y direction of Y direction)/(the figure figurate number-1 of Y direction).
9. the method for setting up parametrization device physics domain unit generator program as claimed in claim 3 is characterized in that, the said step that said basic physical graph is carried out left and right sides ordinal relation analysis specifically comprises:
Confirm the alignment thereof of said basic physical graph, said alignment thereof comprises coboundary vertical line alignment, the alignment of central horizontal line, the alignment of lower boundary vertical line and does not have alignment up and down;
With the point coordinate value in its lower left corner of minimum boundary rectangle of array point figure left margin coordinate figure as this array point; Confirm the left and right sides ordinal relation between the array pattern according to the magnitude relationship of X coordinate figure in the left margin coordinate figure; The little array point of X coordinate figure is on a left side, and the big array point of X coordinate figure is on the right side.
10. the method for setting up parametrization device physics domain unit generator program as claimed in claim 3 is characterized in that, the said step that said basic physical graph is carried out up and down ordinal relation analysis specifically comprises:
Confirm the alignment thereof of said basic physical graph, said alignment thereof comprise left margin vertical line alignment, the alignment of center vertical line, the alignment of right margin vertical line and about do not have alignment;
With the point coordinate value in its lower left corner of minimum boundary rectangle of array point figure lower boundary coordinate figure as this array point; Confirm the ordinal relation up and down between the array pattern according to the magnitude relationship of Y coordinate figure in the lower boundary coordinate figure; The little array point of Y coordinate figure is down, and the big array point of Y coordinate figure is last.
11. the method for setting up parametrization device physics domain unit generator program as claimed in claim 3 is characterized in that, the step of the position dependence between said definite basic physical graph specifically comprises:
Encirclement relation according to each basic physical graph is set up the tree-like relation of father and son of stratification;
According to the left and right sides ordinal relation of basic physical graph and up and down ordinal relation set up with the fraternal tree-like relation of layer;
Set up the position dependence between root and the leaf from the bottom of tree derivation;
Set up with the position dependence between the layer leaf figure from same figure of tree derivation.
12. the method for setting up parametrization device physics domain unit generator program as claimed in claim 3 is characterized in that the step of said creation facilities program (CFP) flow process specifically comprises:
According to said graphic array analysis, the figure of graphic array and array point is generated as a sub-flow process;
Dimension and size according to graphic array in father's flow process are set up loop body, in loop body, calculate and respectively generate required reference position of each array point and input parameter;
Array pattern to generating is shifted according to RP;
Surround relation according to said basic physical graph, make up sub-process and generate besieged figure.
CN 201010285010 2010-09-17 2010-09-17 Method for establishing parameterized device physics territory unit generating program Active CN102402633B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201010285010 CN102402633B (en) 2010-09-17 2010-09-17 Method for establishing parameterized device physics territory unit generating program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201010285010 CN102402633B (en) 2010-09-17 2010-09-17 Method for establishing parameterized device physics territory unit generating program

Publications (2)

Publication Number Publication Date
CN102402633A true CN102402633A (en) 2012-04-04
CN102402633B CN102402633B (en) 2013-11-06

Family

ID=45884833

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201010285010 Active CN102402633B (en) 2010-09-17 2010-09-17 Method for establishing parameterized device physics territory unit generating program

Country Status (1)

Country Link
CN (1) CN102402633B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104423821A (en) * 2013-08-30 2015-03-18 上海博科资讯股份有限公司 Four-line aligning mode for dragging picture
CN106156381A (en) * 2015-04-02 2016-11-23 台湾积体电路制造股份有限公司 The parameter determination method of array of semiconductor devices and device
CN106649894A (en) * 2015-10-28 2017-05-10 北京华大九天软件有限公司 Method for quickly generating device array in integrated circuit layout
CN106897504A (en) * 2017-02-08 2017-06-27 上海华虹宏力半导体制造有限公司 The method to form parameterized units is developed to IP modules

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5097422A (en) * 1986-10-10 1992-03-17 Cascade Design Automation Corporation Method and apparatus for designing integrated circuits
CN1521833A (en) * 2002-11-18 2004-08-18 三洋电机株式会社 Integrated circuit designing apparatus, designing method and designing program
JP2007334549A (en) * 2006-06-14 2007-12-27 Seiko Epson Corp Manufacturing method of integrated circuit device
CN101308375A (en) * 2008-07-16 2008-11-19 四川普什宁江机床有限公司 Numerical control longitudinal cutting machine tool machining program simulated realization method and its system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5097422A (en) * 1986-10-10 1992-03-17 Cascade Design Automation Corporation Method and apparatus for designing integrated circuits
CN1521833A (en) * 2002-11-18 2004-08-18 三洋电机株式会社 Integrated circuit designing apparatus, designing method and designing program
JP2007334549A (en) * 2006-06-14 2007-12-27 Seiko Epson Corp Manufacturing method of integrated circuit device
CN101308375A (en) * 2008-07-16 2008-11-19 四川普什宁江机床有限公司 Numerical control longitudinal cutting machine tool machining program simulated realization method and its system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104423821A (en) * 2013-08-30 2015-03-18 上海博科资讯股份有限公司 Four-line aligning mode for dragging picture
CN106156381A (en) * 2015-04-02 2016-11-23 台湾积体电路制造股份有限公司 The parameter determination method of array of semiconductor devices and device
CN106156381B (en) * 2015-04-02 2019-07-05 台湾积体电路制造股份有限公司 The parameter determination method and device of array of semiconductor devices
CN106649894A (en) * 2015-10-28 2017-05-10 北京华大九天软件有限公司 Method for quickly generating device array in integrated circuit layout
CN106897504A (en) * 2017-02-08 2017-06-27 上海华虹宏力半导体制造有限公司 The method to form parameterized units is developed to IP modules

Also Published As

Publication number Publication date
CN102402633B (en) 2013-11-06

Similar Documents

Publication Publication Date Title
CN110516370B (en) Prefabricated part deepening drawing generation method and device, computer equipment and medium
Babu et al. A generic approach for nesting of 2-D parts in 2-D sheets using genetic and heuristic algorithms
CN102402633B (en) Method for establishing parameterized device physics territory unit generating program
CN110866320B (en) Automatic intelligent platform region graph generation method and system
Baldacci et al. Algorithms for nesting with defects
CN106599477A (en) revit three-dimensional platform-based pile foundation automatic generation and three-dimensional calculation method
Brown et al. Synthetic river valleys: Creating prescribed topography for form–process inquiry and river rehabilitation design
CN103366633A (en) Water conservation map data model-based flood risk map drawing method and system thereof
CN105975655B (en) A kind of imitative Tang and Song Dynasty ancient architecture abnormity roofing tile parametric modeling method based on BIM
CN108062789B (en) Core sample selection method and device
Brilakis et al. Visual pattern recognition models for remote sensing of civil infrastructure
US20120144349A1 (en) High performance drc checking algorithm for derived layer based rules
CN110189409A (en) A kind of quick true three-dimensional geological modeling method and system based on PLAXIS
Hmida et al. Knowledge base approach for 3d objects detection in point clouds using 3d processing and specialists knowledge
CN103942842A (en) Embedded type meandering river sand modeling method
CN113434928A (en) Parametric construction method of complex three-dimensional linear structure
Han et al. 4D-based automation of heavy lift planning in industrial construction projects
CN113158316A (en) Electric single-hole tunnel parametric modeling method
CN108875139A (en) A kind of three dimensional arrangement method and system based on actual environment
CN108197627A (en) A kind of method for extracting two-value graph outline along clockwise direction
CN116011061A (en) Three-dimensional reconstruction model monomer segmentation method, system and terminal for multi-target building
CN107767451A (en) A kind of 3DEC complicated landform modeling methods based on GOCAD Raster Data Models
Persky et al. The Hughes automated layout system-automated LSI/VLSI layout based on channel routing
Shih et al. An adaptive algorithm for conversion from quadtree to chain codes
CN116187663B (en) Spatial layout method, device and equipment for forest land restoration and storage medium

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant