CN102412267B - 在高压晶体管结构的端处的栅极回拉 - Google Patents

在高压晶体管结构的端处的栅极回拉 Download PDF

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CN102412267B
CN102412267B CN201110356266.6A CN201110356266A CN102412267B CN 102412267 B CN102412267 B CN 102412267B CN 201110356266 A CN201110356266 A CN 201110356266A CN 102412267 B CN102412267 B CN 102412267B
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CN102412267A (zh
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V·帕塔萨拉蒂
M·H·曼利
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Power Integrations Inc
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Abstract

本发明涉及在高压晶体管结构的端处的栅极回拉。在一个实施例中，晶体管包括设置成跑道形布局的半导体材料柱，所述半导体材料柱具有沿第一横向延伸的基本线性的部分和在基本线性的部分的每一端处的圆形部分。第一和第二介电区域设置在柱的相对侧。第一和第二场板分别设置在第一和第二介电区域中。分别设置在第一和第二介电区域中的第一和第二栅极元件通过栅极氧化物与柱分开，所述栅极氧化物在基本线性的部分中具有第一厚度。栅极氧化物在圆形部分处基本上更厚。要强调的是，提供该摘要是为了遵守需要摘要的规定以使得检索者或其他读者迅速确定本技术公开的主题。

Description

在高压晶体管结构的端处的栅极回拉
本申请是申请日为2008年2月18日、申请号为200810080747.7、题为“在高压晶体管结构的端处的栅极回拉”的发明专利申请的分案申请。
技术领域
本发明涉及用于制造高电压晶体管的半导体器件结构和工艺。
背景技术
在半导体领域中高电压场效应晶体管(HVFET)已是公知的。很多HVFET采用的器件结构包括延伸的漏极区，当器件处于“截止”状态时，该延伸的漏极区支持或阻断所施加的高电压(例如几百伏)。在常规的垂直HVFET结构中，半导体材料的台或柱形成用于导通状态中的电流的延伸的漏极或漂移区。在衬底顶部附近、与台的侧壁区域相邻地形成沟槽栅极结构，在台处将本体区设置在延伸的漏极区上方。向栅极施加适当的电压电势沿着本体区的垂直侧壁部分形成导电沟道，使得电流可以垂直流过半导体材料，即，从设置源极区的衬底顶表面向下流到设置漏极区的衬底底部。
在常规布局中，垂直HVFET由长的连续硅柱结构构成，该硅柱结构跨越半导体管芯延伸，并且该柱结构在垂直于柱长度的方向上重复。不过，该布局引起的问题在于，在高温处理步骤期间硅晶片容易产生大的翘曲。在很多工艺中，翘曲是永久性的且足够大，防碍了在下一处理步骤中用工具加工晶片。另外，在晶体管布局的圆形端部分中的栅极氧化物弱点可能导致栅极氧化物击穿电压和可靠性问题。
发明内容
根据本发明的一个实施例，提供一种晶体管，包括：设置成跑道形布局的半导体材料柱，所述半导体材料柱具有沿第一横向延伸的基本线性的部分和在跑道形布局的基本线性的部分的每一端处的圆形部分，第一导电类型的源极区被设置在所述柱的顶表面处或附近，并且第二导电类型的本体区被设置在源极区下面的柱中；分别设置在柱的相对侧的第一和第二介电区域，第一介电区域被柱横向包围，并且第二介电区域横向包围所述柱；分别设置在第一和第二介电区域中的第一和第二场板；分别设置在邻近本体区的柱的顶表面处或附近的第一和第二介电区域中的第一和第二栅极元件，所述第一和第二栅极元件通过栅极氧化物与本体区分开，所述栅极氧化物在跑道形布局的基本线性的部分中具有第一厚度，栅极氧化物在圆形部分处具有第二厚度，第二厚度基本上大于第一厚度。
根据本发明的一个实施例，提供一种晶体管，包括：设置成跑道形布局的半导体材料柱，所述半导体材料柱具有沿第一横向延伸的基本线性的部分和在跑道形布局的基本线性的部分的每一端处的圆形部分；分别设置在柱的相对侧的第一和第二介电区域，第一介电区域被柱横向包围，并且第二介电区域横向包围所述柱；分别设置在第一和第二介电区域中的第一和第二场板；分别设置在柱的顶部处或附近的第一和第二介电区域中的第一和第二栅极元件，所述第一和第二栅极元件通过栅极氧化物与本体区分开，所述栅极氧化物在跑道形布局的基本线性的部分中具有第一厚度，栅极氧化物在圆形部分处具有第二厚度，第二厚度基本上大于第一厚度。
根据本发明的一个实施例，提供一种晶体管，包括：具有均沿第一横向延伸的间隔开的第一和第二线性部分的半导体材料的跑道形柱，所述跑道形柱的第一圆形部分接合第一和第二线性部分的相应的第一端，所述跑道形柱的第二圆形部分接合第一和第二线性部分的相应的第二端；分别设置在跑道形柱的相对侧的第一和第二介电区域，第一介电区域被柱横向包围，并且第二介电区域横向包围所述柱；分别设置在第一和第二介电区域中的第一和第二场板；分别设置在跑道形柱的第一线性部分的顶部处或附近的第一和第二介电区域中的第一和第二栅极元件；分别设置在跑道形柱的第二线性部分的顶部处或附近的第一和第二介电区域中的第三和第四栅极元件；并且其中第一、第二、第三和第四栅极元件均借助栅极氧化物与跑道形柱分开，第一、第二、第三和第四栅极元件的相对端沿第一横向分别终止于第一和第二圆形部分处或附近。
附图说明
从下面的详细说明和附图将可以更全面地理解本发明，不过，详细说明和附图不应用来将本发明限制到所示的具体实施例，而是仅用于解释和理解。
图1示出了垂直HVFET结构的实例截面侧视图。
图2A示出了图1中所示的垂直HVFET结构的实例布局。
图2B为图2A中所示的实例布局的一部分的放大视图。
图3A示出了图1中所示的垂直HVFET结构的另一实例布局。
图3B为图3A中所示的实例布局的一部分的放大视图。
图4A示出了图1中所示的垂直HVFET结构的又一实例布局。
图4B为图4A中所示的实例布局的一部分的放大视图。
图5示出了具有管芯至管芯棋盘式布置的HVFET的晶片的实例布局。
图6示出了具有管芯至管芯棋盘式布置的分段的HVFET的晶片的实例布局。
图7示出了具有HVFET段的棋盘式块的矩形管芯的实例布局。
图8示出了用于图7中所示的管芯的实例栅极金属布线布局。
图9示出了用于图7中所示的管芯的实例栅极和源极金属布线布局。
图10示出了图9中所示的实例布局的展开部分。
图11示出了具有如图1中所示的结构的单个HVFET段的圆形端部分的实例布局。
图12示出了具有如图1中所示的结构的单个HVFET段的圆形端部分的另一个实例布局。
具体实施方式
在下述说明中，为了提供对本发明的透彻理解，给出了具体细节，例如材料类型、尺寸、结构特点、处理步骤等。不过，本领域的普通技术人员将理解，实施本发明可以不需要这些具体细节。还应理解，图中的元件是代表性的，为了清晰起见没有按照比例绘制。
图1示出了垂直HVFET 10的实例截面侧视图，该HVFET 10具有这样的结构，其包括形成于N+掺杂硅衬底11上的N型硅的延伸漏极区12。对衬底11进行重掺杂以使其对流经漏电极的电流的电阻最小化，在完成的器件中漏电极位于衬底的底部上。在一个实施例中，延伸漏极区12为从衬底11延伸到硅晶片的顶表面的外延层的一部分。接近外延层的顶表面形成P型本体区13以及被P型区域16横向分开的N+掺杂的源极区14a和14b。如可以看到的，P型本体区13设置于延伸漏极区12上方且垂直地将延伸漏极区12与N+源极区14a和14b以及P型区域16分开。
在一个实施例中，外延层包括延伸漏极区12的部分的掺杂浓度是线性渐变的，以产生表现出基本均匀的电场分布的延伸漏极区。线性渐变可以在外延层12的顶表面下方的某个点处停止。
在图1的实例垂直晶体管中，延伸漏极区12、本体区13、源极区14a和14b以及P型区域16共同包括硅材料的台或柱17(在本申请中两个术语作为同义词使用)。用介电材料(例如氧化物)层填充形成于柱17的相对侧上的垂直沟槽，所述介电材料形成介电区域15。可以由器件的击穿电压要求决定柱17的高度和宽度以及相邻垂直沟槽之间的间距。在各实施例中，台17的垂直高度(厚度)在大约30μm到120μm厚的范围内。例如，在尺寸大约为1mm×1mm的管芯上形成的HVFET可以具有垂直厚度为大约60μm的柱17。作为另一实例，在每一侧的大约2mm-4mm的管芯上形成的晶体管结构可以具有大约30μm厚的柱结构。在特定实施例中，柱17的横向宽度尽量窄到能可靠制造的程度(例如大约0.4μm到0.8μm宽)，以便实现非常高的击穿电压(例如600-800V)。
在另一实施例中，不是跨越柱17的横向宽度在N+源极区14a和14b之间布置P型区域16(如图1所示)，而是可以跨越柱17的横向长度在柱17的顶部交替形成N+源极区和P型区域。换句话说，诸如图1中所示的给定的截面图将具有跨越柱17的整个横向宽度延伸的N+源极区14或P型区域16，取决于该截面取自哪里。在这样的实施例中，每个N+源极区14在两侧(沿柱的横向长度)与P型区域16邻接。类似地，每个P型区域16在两侧(沿柱的横向长度)与N+源极区14邻接。
介电区域15a、15b可以包括二氧化硅、氮化硅或其他合适的介电材料。可以使用多种公知方法，包括热生长和化学汽相淀积来形成介电区域15。设置在每个介电层15中并与衬底11和柱17完全绝缘的是场板(field plate)19。用于形成场板19的导电材料可以包括重掺杂的多晶硅、金属(或金属合金)、硅化物或其他适当的材料。在完成的器件结构中，场板19a和19b通常起电容极板的作用，当HVFET处于截止状态时(即当漏极被升高至高电压电势时)所述电容极板可用于耗尽延伸漏极区的电荷。在一个实施例中，将每个场板19与柱17的侧壁分开的氧化物区域15的横向厚度大约为4μm。
垂直HVFET晶体管80的沟槽栅极结构包括栅极元件18a、18b，每个栅极元件分别设置在场板19a、19b和本体区13之间、柱17的相对侧上的氧化物区域15a和15b中。高质量的薄(例如～)栅极氧化物层将栅极元件18与和本体区13相邻的柱17的侧壁分开。栅极元件18可以包括多晶硅、或某种其他适合的材料。在一个实施例中，每个栅极元件18具有大约1.5μm的横向宽度和大约3.5μm的深度。
本领域的实践人员将会理解，柱17的顶部附近的N+源极区14和P-型本体区13均可以使用普通的淀积、扩散和/或注入处理技术形成。在形成N+源极区38之后，通过利用常规制造方法形成电连接到器件的相应区域/材料(为了清晰图中未示出)的源、漏、栅、和场板电极可以完成HVFET 10。
图2A示出了图1中所示的垂直HVFET结构的实例布局。图2A的顶视图示出了单个分立的HVFET，其包括半导体管芯21上的上部晶体管部分30a和下部晶体管部分30b。由伪硅柱32将这两部分分开。每个部分30包括多个“跑道(racetrack)”形晶体管结构或段，每个晶体管段包括细长环或椭圆，其包括在相对侧由介电区域15a和15b包围的硅柱17。柱17本身在x和y方向上横向延伸以形成连续细长的跑道形环或椭圆。设置在介电区域15a和15b中的是相应的栅极元件18a和18b以及场板19a和19b。场板19a包括单个细长元件，其在圆形指尖(fingertip)区域中终结于任一端。另一方面，场板19b包括环绕柱17的细长环或椭圆。相邻跑道结构的场板19b被示为合并的(merged)，从而它们共享在一侧的公共元件。作为参考，图1的截面图可以取自图2A的实例布局的切割线A-A’。
应当理解，在图2A的实例中，每个跑道形晶体管段在y方向上的宽度(即间距)大约为13μm，在x方向上的长度在大约400μm到1000μm的范围内，且柱高度约为60μm。换句话说，包括部分30a和30b的各个跑道形晶体管段的长宽比在大约30直到80的范围内。在一个实施例中，每个跑道形段的长度大于其间距或宽度至少20倍。
本领域的实践人员将理解，在完成的器件结构中，使用图案化金属层来互连各个晶体管段的每个硅柱17。也就是说，在实际实施例中，分别将所有的源极区、栅极元件和场板一起布线至管芯上对应的电极。在图示的实施例中，每个部分30中的晶体管段基本跨越管芯21的宽度沿y方向设置成并排关系。类似地，在x方向上，部分30a和30b的晶体管段的额外长度基本在管芯21的长度上延伸。在图2A的实例布局中，跨越半导体管芯21，分开硅柱的介电区域15的宽度以及场板的宽度是基本均匀的。以均匀的宽度和间隔距离布置晶体管段防止了在用于共形地淀积包括介电区域15和场板19的层的处理步骤之后形成空隙或孔。
图2B为图2A中所示的实例布局的一部分的放大视图。为了清晰起见，仅示出了每个晶体管段的柱17和介电区域15b。图示的伪硅柱32分开相应晶体管段部分30a和30b的介电区域15b的圆端区域。换句话说，在半导体衬底中被蚀刻来限定柱17的深垂直沟槽也限定伪硅柱32。在一个实施例中，使伪硅柱32在x方向上的宽度(即其分开晶体管段部分)小到能被可靠地制造。
将单个管芯HVFET分段成由伪硅柱32分开的部分的目的在于在细长跑道形晶体管段中引入长度方向上(x方向)的应力消除(stressrelief)。将晶体管器件结构分段或断开成两个或更多个部分减轻了跨越管芯长度的机械应力。该应力由位于柱侧面的氧化物区域引起，并且通常集中于每个跑道形段的圆形端处。由此通过将晶体管器件结构分段成两个或更多个部分来减轻机械应力防止了由应力导致的不希望有的硅柱翘曲和对硅的损伤(例如位错)。
要理解的是，在通过高度分段的布局提供的应力消除和导电区域的损失之间存在折衷。更多的分段导致更大的应力减轻，但是以导电区域为代价。通常，柱的垂直高度越大且半导体管芯越大，则需要的晶体管部分或段的数目越大。在一个实施例中，对于具有60μm高的柱的2mm×2mm的管芯，利用包括四个跑道形晶体管部分的布局在导通电阻约为1欧姆的HVFET中提供足够的应力减轻，所述四个跑道形晶体管部分由伪硅柱分开，每个伪硅柱具有大约13μm的间距(y方向)和大约450μm的长度(x方向)。
在另一个实施例中，不是用伪硅柱来分开成对的跑道形晶体管段，每一对位于不同部分中，而是可以用包括不同材料的伪柱。用于伪柱的材料应当具有接近硅的热膨胀系数或充分不同于介电区域的热膨胀系数的热膨胀系数以便减轻由位于硅柱侧面的介电区域引起的长度方向上的应力。
图3A示出了图1所示的垂直HVFET结构的另一实例布局。图3B为图3A中所示的实例布局的一部分的放大图，仅示出了柱17、氧化物区域15b和可选的伪硅柱33。类似于图2A和2B的实施例，图3A和3B示出了半导体管芯21上的单个分立的HVFET，其包括上部晶体管部分30a和下部晶体管部分30b。但是在图3A和3B的实例中，由氧化物区域15b填充的深垂直沟槽以及晶体管部分30a和30b的场板19b重叠，或者被合并，在分段的晶体管部分之间留下小的菱形伪硅柱33。在该实施例中，单个伪柱中心位于两个部分上相邻成对的晶体管段的四个圆形端之间。在所示的实例中，对于包括管芯21的晶体管部分30中的每N个(其中N为大于1的整数)跑道形段或结构，存在总共N-1个伪柱33。
图4A示出了图1所示的垂直HVFET结构的又一实例布局。图4B为图4A中所示的实例布局的一部分的放大图。在图4B的放大图中为了清晰仅示出了柱17和氧化物区域15b。在该实例中，将半导体管芯21的包括HVFET的晶体管段交替移动每个跑道形段的长度的一半，结果形成交替与上部晶体管部分40a和下部晶体管部分40b相关联的跑道形晶体管段。换句话说，一行部分40a的每个晶体管段由部分40b的一对晶体管段分开，该对晶体管段沿x方向设置成端到端的关系。
要理解的是，可以将各段交替移动段长度的任何百分数(fraction)。换句话说，段的移动不限于长度的50％或一半。多种实施例可以包括交替移动了晶体管段的长度的从大于0％到小于100％的任何百分比或百分数的段。
在图4A和4B的实例中，相应部分40a和40b中交替的晶体管段的介电区域15b被合并。在图示的具体实施例中，与不同相邻部分相关联的晶体管段的圆形端重叠或被合并，使得相邻部分的场板19b在各端处(沿x方向)被合并。而且，不同部分的交替晶体管段的场板19b的延伸的直边部分沿着每个段的基本长度被合并。要理解的是，区域15b和19b在相应部分之间有或没有伪柱(或隔离的伪硅柱)的情况下都可以被合并。
图5示出了晶片50的实例布局，其在半导体管芯21a-21d上分别具有管芯至管芯的棋盘式HVFET 10a-10d。HVFET 10的每一个包括如图1所示的多个跑道形晶体管段，它们沿着其宽度并排设置成基本方形的块。在该实例中，HVFET 10a-10d均包括长度基本跨越相应管芯21a-21d的长度延伸的晶体管段。在一个实施例中，每个段的宽度约为13μm，且长度在大约500μm到2000μm的范围内。其他实施例可以具有大于2000μm的长度。段的块或堆叠结构也基本跨越每个管芯的宽度延伸。(注意每个管芯21的有边的方形代表相邻半导体管芯之间划线区域的边缘。)虽然图5示出了两行和两列的HVFET 10，但可以理解的是，可以跨越整个晶片衬底重复所示出的管芯至管芯棋盘式布置。
在图5的实例中，行或列中相邻的管芯被取向为使得一个管芯中的晶体管段的长度在一个方向上延伸，且相邻管芯中的晶体管段的长度沿第二正交方向延伸。例如，HVFET 10a被示为其晶体管段的长度沿x方向取向，而相邻的HVFET 10b和10c。通过跨越晶片50正交地交替每单个管芯21中的晶体管段的取向(即棋盘式布置)，将由长介电区域产生的机械应力沿两个正交方向分布，由此减少了晶片50的翘曲。
图6示出了具有分段的HVFET的管芯到管芯棋盘式布置的晶片的另一实例布局。图6的实例使用了与图5相同的方法管芯到管芯地交替晶体管结构的取向；然而，在图6的实施例中，将HVFET结构分段成多个(例如两个)部分。例如，将基本跨越半导体管芯21的长度和宽度延伸的每个HVFET分段成由伪柱32分开的两个部分30a和30b。
对于基本方形的管芯而言，图6中所示的每个半导体管芯21具有与图2所示的相同的布局。类似于图5中所示的实例，相邻管芯具有跨越晶片50正交交替的晶体管段。也就是说，管芯21a和21d的部分30a和30b中的晶体管段具有在x方向上取向的长度，而管芯21b和21c的部分30a和30b中的晶体管段具有在y方向上取向的长度。
可以理解，可以用多个均由一个或多个伪柱分开的晶体管部分，例如大于2个的晶体管部分形成每个管芯21的HVFET。此外，可以将图2A-4B的实例中所示的具有多个晶体管部分的单个管芯布局中的任何一个用在图6中所示的每个管芯21中，且各段的取向跨越晶片50管芯到管芯地交替。
图7示出了管芯25的实例矩形布局，其具有以并排布置的基本方形块或部分36堆叠的跑道形HVFET段的棋盘式块。行或列中的相邻部分被取向成使得一个部分中的晶体管段的长度在一个方向上延伸，且其他相邻部分中的晶体管段的长度在第二正交方向上延伸。例如，管芯25的每个行和列包括取向为细长的晶体管段沿x方向对准(aligned)的晶体管部分36a和取向为细长的晶体管段沿y方向对准的交替的晶体管部分36b。晶体管部分36a和36b之间的空间包括伪硅柱；也就是说，形成伪柱的硅不是有源晶体管区域。
在图示的实施例中，管芯25包括三行和四列的晶体管部分36。图7的实例中所示的棋盘式布局方式可以用来在几乎任何(在可行的限度内)直线形状的管芯上生产单个分立的HVFET。
图8示出了用于图7中所示的管芯的实例栅极金属布线布局。利用单金属层工艺制作图8的栅极金属布线方案，并且源极和栅极金属被设置在相同的平坦水平面上。所示的实例包括在跑道形HVFET段的棋盘式块的每行之间延伸的水平栅极金属汇流线(bus line)41a-41d。例如，栅极金属汇流线41a和41b被示为沿图7的棋盘式部分36的第一(上部)行的顶部和底部水平延伸。(应当理解，由于汇流线41b提供到达棋盘式部分的第一和第二行的多晶硅栅极元件的共用导电路径的事实，栅极金属汇流线41b可以是汇流线41a的两倍宽。)
在每行之内，具有沿x方向对准的其晶体管段的长度的部分36具有一半耦合到顶部汇流线的多晶硅栅极元件、和第二半耦合到底部汇流线的多晶硅栅极元件。例如，图8中的上部左手边块或部分36被示为具有由线44a表示的通过接触45a连接到栅极金属汇流线41b的多晶硅栅极元件，而在相同部分中的由线44b表示的多晶硅栅极元件通过接触45b连接到栅极金属汇流线41a。注意，每个线44a或44b实际上表示单个跑道形HVFET段的两个栅极元件18a和18b(见图1)。因此，在相同部分中，线44a表示两个最左边的HVFET段的栅极元件，并且线44b表示两个最右边的HVFET段的栅极元件。进一步要注意的是，每个栅极元件仅在一端连接到汇流线(顶部或底部)。
图8中示出的栅极金属布线图案也包括垂直栅极金属短截线(stub line)42，所述垂直栅极金属短截线42跨越棋盘式块的每一行延伸大约一半长度。在其中HVFET段的长度沿y方向对准的每个部分之内，一半的多晶硅栅极元件耦合到一个短截线，并且另一半的多晶硅栅极元件耦合到另一个短截线。例如，图8的上部行中的第二部分(从左边)示出通过接触45c连接到左侧栅极金属短截线42a的底部一半的栅极元件(由线44c表示)，和通过接触45d连接到右侧栅极金属短截线42b的顶部一半的栅极元件(由线44d表示)。类似地，在图8的上部行中的第四部分(最右手边)示出连接到栅极金属短截线42c的底部一半的栅极元件和连接到栅极金属短截线42d的顶部一半的栅极元件。注意，水平对准的段的每一个栅极元件仅在一端连接到短截线(左或右侧)。
栅极金属短截线42跨越那些使其各段沿y方向(即水平地)对准的部分仅延伸一半长度的原因是允许源极金属汇流线跨越每一行延伸并且接触每个晶体管段的源极区。这通过图9的实例示出，其示出具有在顶部和底部栅极金属迹线51之间跨越晶体管部分36的每一行连续延伸的各个源极汇流线61的管芯25。(金属迹线51表示与每一行相关联的合并的金属汇流线41和短截线42。)例如，源极汇流线61a跨越管芯25上的部分的上部行连续延伸以接触在用于该行中的每一个HVFET段的硅柱17的顶部处的源极区14的每一个。在这样做的过程中，源极汇流线61a在短截线42之间和周围、以及在汇流线41之间“曲折前进”，其全部被图案化在相同的单层金属上。
本领域技术人员将理解的是，通过使短截线42跨越每行延伸大约一半长度，每个源极汇流线61的电流控制能力被最大化(即线61的最小开槽)。为了不同地安置它，由于围绕短截线42的线61的开槽，使短截线42跨越每行垂直地(沿x方向)延伸除一半长度以外的距离将不必要地抑制或限制跨越源极汇流线61流动的电流。同样地，应当理解的是，通过将部分中的栅极元件的一半连接到一个栅极金属汇流线(或短截线)，以及另一半连接到另一个栅极金属汇流线(或短截线)，电迁移和电阻问题被最小化。
图10示出了图9中所示的实例布局的展开部分，其示出用来连接栅极金属迹线51与栅极元件18a和18b的一个可能的方案。在该实例中，示出分别通过接触55a和55b连接迹线51与栅极元件18a和18b的圆形指尖部分。在柱17的顶部处位于栅极元件18a和18b之间的源极区被示为通过接触75连接到源极金属汇流排61。(应当理解，为了清楚起见，仅示出两个接触75。)在替换实施例中，不是接触栅极元件的圆形指尖部分，而是栅极金属迹线51可以沿圆形指尖部分附近的栅极元件18a和18b的直的、线性部分连接。(注意，为了清楚起见，在图10的实例中没有示出场板。)
图11示出了具有如图1中所示的结构的单个HVFET段的圆形端部分的实例布局。在所示的实施例中，栅极元件18a和18b已经从HVFET段的圆形端或指尖部分除去。换句话说，多晶硅栅极元件18a和18b的每一个在柱17的两个基本线性的部分的相对侧上沿HVFET段的全部长度横向延伸，但是终止于柱开始在所述段的端部周围弯曲的点处或附近。跑道形柱17的圆形端借助介电区域15在相对侧上邻接或在侧面相接(flanked)，并且在围绕柱17的端的区域中栅极元件被完全去除。即，图11的实施例包括四个分开的栅极元件：一对被设置在柱17的一个线性部分的相对侧的介电区域15中，并且第二对被设置在柱17的另一个线性部分的相对侧的介电区域15中。
在图11的实例中，栅极金属汇流排51被示为分别通过位于栅极元件的端附近的接触55a和55b与栅极元件18a和18b电连接。
图12示出了具有如图1中所示的结构的单个HVFET段的圆形端部分的另一个实例布局。在该实施例中，栅极元件被示为沿硅柱的圆形端部分从柱17往后移(move back)。例如，多晶硅栅极元件18a和18b被示为在HVFET段的圆形端部分处沿柱17的相对侧分别回拉了(pull back)距离d1和d2。因此在端终止结构的圆形或弯曲部分中栅极氧化物更厚得多(例如1μm)。应当理解，为了消除该布局的圆形部分中的栅极氧化物弱点同时保持栅极元件18a和18b与设置在介电区域15a和15b中的相应场板(未示出)的适当距离，通常将距离d1和d2选得足够大。栅极元件18a和18b的圆形指尖部分到栅极金属迹线/汇流排的电接触可以制作成如图10或图11中所示的。
虽然已经结合具体器件类型描述了以上实施例，但是本领域的普通技术人员将理解多种变型和改变都在本发明的范围内。例如，虽然已经描述了HVFET，但是图示的方法、布局和结构同样适用于其他结构和器件类型，包括肖特基、二极管、IGBT和双极型结构。因此，应当将说明书和附图看作是示例性的而不是限制性的。

Claims (12)

1.一种晶体管，包括：
设置成跑道形布局的半导体材料柱，所述半导体材料柱具有沿第一横向延伸的线性的部分和在跑道形布局的线性的部分的每一端处的圆形部分，其中所述半导体材料柱包括被设置在所述柱的顶表面处或附近的第一导电类型的源极区以及被设置在所述源极区下面的柱中的第二导电类型的本体区；
分别设置在柱的相对侧的第一和第二介电区域，第一介电区域被柱横向包围，并且第二介电区域横向包围所述柱；
分别设置在第一和第二介电区域中的第一和第二场板；以及
分别设置在柱的顶部处或附近的第一和第二介电区域中的第一和第二栅极元件，所述第一和第二栅极元件通过栅极氧化物与所述本体区分开，并且所述第一和第二栅极元件在所述圆形部分处沿所述半导体材料柱的相对侧从所述柱处被分别回拉第一距离和第二距离。
2.根据权利要求1所述的晶体管，其中所述栅极氧化物具有沿所述线性的部分的第一厚度以及在所述圆形部分处的更大的第二厚度。
3.根据权利要求2所述的晶体管，其中第一厚度大约是
4.根据权利要求2所述的晶体管，其中第二厚度大约是1μm。
5.根据权利要求1所述的晶体管，进一步包括：
源极区，所述本体区被设置在所述源极区下面的柱中；以及
设置在本体区下面的柱中的延伸漏极区。
6.根据权利要求1所述的晶体管，其中所述线性的部分沿第一横向的长度比跑道形布局的宽度大至少30倍，所述宽度在垂直于第一横向的第二横向上。
7.根据权利要求2所述的晶体管，其中，所述第一和第二栅极元件分别被设置在邻近所述本体区的柱的顶表面处或附近的所述第一和第二介电区域中。
8.根据权利要求7所述的晶体管，其中第一厚度大约是
9.根据权利要求7所述的晶体管，其中第二厚度大约是1μm。
10.根据权利要求7所述的晶体管，进一步包括设置在本体区下面的柱中的延伸漏极区。
11.根据权利要求7-10中任一项所述的晶体管，其中所述线性的部分沿第一横向的长度比跑道形布局的宽度大至少30倍，所述宽度在垂直于第一横向的第二横向上。
12.根据权利要求7-10中任一项所述的晶体管，其中第一和第二栅极元件与第一和第二场板完全绝缘。
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