CN102468169A - N-channel metal oxide semiconductor (NMOS) transistor and formation method thereof - Google Patents
N-channel metal oxide semiconductor (NMOS) transistor and formation method thereof Download PDFInfo
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- CN102468169A CN102468169A CN2010105326201A CN201010532620A CN102468169A CN 102468169 A CN102468169 A CN 102468169A CN 2010105326201 A CN2010105326201 A CN 2010105326201A CN 201010532620 A CN201010532620 A CN 201010532620A CN 102468169 A CN102468169 A CN 102468169A
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Abstract
The invention relates to an N-channel metal oxide semiconductor (NMOS) transistor and a formation method thereof. The formation method for the UMOS transistor comprises the following steps of: providing a semiconductor substrate, wherein an epitaxial layer is formed on the semiconductor substrate, a doping trap is formed on the surface of the epitaxial layer, and doping types of the doping trap and the epitaxial layer are opposite; forming a groove, wherein the groove passes through the doping trap, and the bottom and the side walls of the groove are exposed from the epitaxial layer; forming an inversion type doped region on the surface of the epitaxial layer at the bottom of the groove, wherein doping types of the inversion type doped region and the epitaxial layer are opposite; forming a gate dielectric layer, and covering the bottom and the side walls of the groove; forming gate electrodes on the surface of the gate dielectric layer, and filling the groove; and forming a source region in the doping trap, wherein the source region is adjacent to the gate dielectric layer, and doping types of the source region and the doping trap are opposite. By the UMOS transistor and the formation method, the gate drain capacitance is reduced, and the power consumption of circuits is lowered.
Description
Technical field
The present invention relates to semiconductor device and manufacturing field, particularly a kind of UMOS transistor and forming method thereof.
Background technology
Along with the continuous development of semiconductor technology, power device (Power Device) as a kind of new device, is widely used in like fields such as disk drive, automotive electronics.Power device needs to bear bigger voltage, electric current and power termination, and for example output rectifier requires to export about 3.3V voltage at input 20V voltage and exports about 1.5V voltage with input 10V voltage; And requirement can have the depleted voltage of 10V to 50V scope.And devices such as existing MOS transistor can't satisfy the demand, and for example the depleted voltage range of Schottky diode (Schottky diodes) is greatly about 0.5V, and therefore, in order to satisfy the needs of using, various power devices become the focus of concern.
U-shaped trench metal-oxide-semiconductor field effect transistor (UMOS; U-groove-metal-oxide-silicon transistors) is a kind of power device commonly used; The direction of its raceway groove is perpendicular to substrate; Not only good power-performance can be provided, with the MOS transistor of routine than the area that can also save about 40%.
Fig. 1 shows the transistorized cross-sectional view of a kind of UMOS of prior art.As shown in Figure 1, comprising: N
+The semiconductor-based end 10 of mixing; Be formed on the epitaxial loayer 11 at the semiconductor-based end 10, said epitaxial loayer 11 is N
-Mix; Be formed on the dopant well 12 on said epitaxial loayer 11 surfaces, said dopant well 12 mixes for the P type; The groove that runs through said dopant well 12; Gate dielectric layer 13 covers the bottom and the sidewall of said groove; Gate electrode 14 is formed on the said gate dielectric layer 13, fills up said groove; Source region 15 and source region 17 are formed in the dopant well 12 of said groove both sides, and be adjacent with said gate dielectric layer 13, is N
+Mix; Tagma 16 and tagma 18 are formed in the said dopant well 12, are P
+Mix.
The UMOS transistor that has comprised 2 symmetries among Fig. 1; Concrete, epitaxial loayer 11, dopant well 12, source region 15, gate dielectric layer 13 and gate electrode 14 have constituted one of them UMOS transistor, and wherein epitaxial loayer 11 is as drain electrode; Source region 15 is as source electrode; The part of the dopant well 12 adjacent with gate dielectric layer 13 is as channel region between epitaxial loayer 11 and the source region 15, and tagma 16 is identical with the doping type of dopant well 12, as the body electrode; Epitaxial loayer 11, dopant well 12, source region 17, gate dielectric layer 13 and gate electrode 14 have constituted another UMOS transistor; Wherein epitaxial loayer 11 is as drain electrode; Source region 17 is as source electrode; The part of the dopant well 12 adjacent with gate dielectric layer 13 is as channel region between epitaxial loayer 11 and the source region 17, and tagma 18 is identical with the doping type of dopant well 12, as the body electrode.Because the shape of epitaxial loayer 11 and gate dielectric layer 13 is " U " shape, so called after UMOS transistor.The structures shape of transistorized gate dielectric layer of UMOS 13 and gate electrode 14 its MOS transistor than routine have higher input impedance, thereby can be used as power device.
The area over against overlap (overlap) between transistorized gate electrode 14 of the UMOS of prior art and the drain electrode (being epitaxial loayer 11) is bigger, makes that the gate leakage capacitance between gate electrode 14 and the drain electrode is bigger.And along with the continuous rising of channel frequency, big gate leakage capacitance can cause circuit power consumption to raise.
About the transistorized more detailed contents of UMOS, please refer to the patent No. and be 6551881 United States Patent (USP).
Summary of the invention
The problem that the present invention solves provides a kind of UMOS transistor and forming method thereof, reduces gate leakage capacitance, reduces power consumption.
For addressing the above problem, the invention provides the transistorized formation method of a kind of UMOS, comprising:
The semiconductor-based end is provided, is formed with epitaxial loayer at said the semiconductor-based end, the surface of said epitaxial loayer is formed with dopant well, and the doping type of said dopant well and said epitaxial loayer is opposite;
Form groove, said groove runs through said dopant well, and bottom and sidewall expose said epitaxial loayer;
In the surface portion of the epitaxial loayer of said channel bottom, form the transoid doped region, the doping type of said transoid doped region and said epitaxial loayer is opposite;
Form gate dielectric layer, cover the bottom and the sidewall of said groove;
Surface at said gate dielectric layer forms gate electrode, fills up said groove;
In said dopant well, form the source region, said source region is adjacent with said gate dielectric layer, and its doping type is opposite with said dopant well.
Optional, form the transoid doped region in the surface portion of said epitaxial loayer at said channel bottom and comprise: the epitaxial loayer of said channel bottom is carried out ion inject, the ionic type that said ion injects is opposite with the doping type of said epitaxial loayer.
Optional; Forming the transoid doped region in the surface portion of said epitaxial loayer at said channel bottom comprises: to said channel bottom and carry out ion with the epitaxial loayer of bottom adjacent grooves sidewall and inject, the ionic type that said ion injects is opposite with the doping type of said epitaxial loayer.
Optional, the injection energy that said ion injects is 20 to 30KeV, and implantation dosage is 1e13 to 5e13/cm
2
Optional, the degree of depth of said transoid doped region account for said beneath trenches epitaxial loayer the degree of depth 10% to 20%.
Optional, the doping type of the said semiconductor-based end and epitaxial loayer is the N type, and the doping type of said dopant well is the P type, and the doping type of said transoid doped region is the P type, and the doping type in said source region is the N type.
Optional, the transistorized formation method of said UMOS also comprises: in said dopant well, form the tagma, its doping type is identical with said dopant well.
For addressing the above problem, the invention provides a kind of UMOS transistor, comprising:
The semiconductor-based end;
Epitaxial loayer is formed at at said the semiconductor-based end;
Dopant well is formed at the surface of said epitaxial loayer, and doping type is opposite with said epitaxial loayer;
Groove runs through said dopant well, and bottom and sidewall expose said epitaxial loayer;
The transoid doped region is formed in the surface portion of epitaxial loayer of said channel bottom, and doping type is opposite with said epitaxial loayer;
Gate dielectric layer covers the bottom and the sidewall of said groove;
Gate electrode is formed at the surface of said gate dielectric layer and fills up said groove;
The source region is positioned at said dopant well and adjacent with said gate dielectric layer.
Optional, said transoid doped region extends to the epitaxial loayer with said channel bottom adjacent grooves sidewall.
Optional, the degree of depth of said transoid doped region account for said beneath trenches epitaxial loayer the degree of depth 10% to 20%.
Optional, the doping type of the said semiconductor-based end and epitaxial loayer is the N type, and the doping type of said dopant well is the P type, and the doping type of said transoid doped region is the P type, and the doping type in said source region is the N type.
Optional, said UMOS transistor also comprises the tagma, is formed in the said dopant well, its doping type is with identical with said dopant well.
Compared with prior art, technical scheme of the present invention has following advantage:
The present technique scheme forms the transoid doped region in the surface portion of the epitaxial loayer of the transistorized channel bottom of UMOS, its doping type and epitaxial loayer are opposite, has reduced the overlapping area of gate electrode and epitaxial loayer, thereby has reduced gate leakage capacitance, is beneficial to reduce power consumption.
Description of drawings
Fig. 1 is the transistorized cross-sectional view of a kind of UMOS of prior art;
Fig. 2 is the schematic flow sheet of the transistorized formation method of the UMOS of the embodiment of the invention;
Fig. 3 to Fig. 8 is the cross-sectional view of the transistorized formation method of the UMOS of the embodiment of the invention;
Fig. 9 is the comparison diagram of the transistorized voltage of the UMOS-gate leakage capacitance curve of the transistorized voltage of the UMOS of the embodiment of the invention-gate leakage capacitance curve and prior art;
Figure 10 is the comparison diagram of the transistorized voltage-to-current curve of UMOS of transistorized voltage-to-current curve of the UMOS of the embodiment of the invention and prior art.
Embodiment
Gate leakage capacitance parasitic between transistorized gate electrode of the UMOS of prior art and the drain electrode is bigger, makes that the power consumption of circuit is corresponding bigger.
The present technique scheme forms the transoid doped region in the surface of the epitaxial loayer of the transistorized channel bottom of UMOS; Its doping type and epitaxial loayer are opposite; Reduced the overlapping area of gate electrode and epitaxial loayer; Be equivalent between gate electrode and drain electrode, be connected in series a junction capacitance, thereby reduced gate leakage capacitance, be beneficial to and reduce circuit power consumption.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed embodiment.
Fig. 2 shows the schematic flow sheet of the transistorized formation method of UMOS of the embodiment of the invention, comprising:
Step S21 provides the semiconductor-based end, is formed with epitaxial loayer at said the semiconductor-based end, and the surface of said epitaxial loayer is formed with dopant well, and the doping type of said dopant well and said epitaxial loayer is opposite;
Step S22 forms groove, and said groove runs through said dopant well, and bottom and sidewall expose said epitaxial loayer;
Step S23 forms the transoid doped region in the surface portion of the epitaxial loayer of said channel bottom, the doping type of said transoid doped region and said epitaxial loayer is opposite;
Step S24 forms gate dielectric layer, covers the bottom and the sidewall of said groove;
Step S25 forms gate electrode on the surface of said gate dielectric layer, fills up said groove;
Step S26 forms the source region in said dopant well, said source region is adjacent with said gate dielectric layer, and its doping type is opposite with said dopant well.
Below in conjunction with Fig. 2 and Fig. 3 to Fig. 8 the transistorized formation method of the UMOS of the embodiment of the invention is elaborated.
Referring to figs. 2 and 3, execution in step S21 provides the semiconductor-based end, is formed with epitaxial loayer at said the semiconductor-based end, and the surface of said epitaxial loayer is formed with dopant well, and the doping type of said dopant well and said epitaxial loayer is opposite.Concrete; The semiconductor-based end 20 is provided, and the said semiconductor-based end 20 is a semi-conducting material, can be monocrystalline silicon; Also can be also can be silicon, germanium, GaAs or silicon Germanium compound; Can also be epitaxial layer structure on silicon-on-insulator (SOI, Silicon On Insulator) structure or the silicon, the semiconductor-based end 20 be N described in the present embodiment
+Type mixes.Be formed with epitaxial loayer 21, said epitaxial loayer 21 can adopt epitaxial growth technology to form at said the semiconductor-based end 20, and its doping type is identical with the said semiconductor-based end 20 in the present embodiment, is specially N
-Type mixes.The surface of said epitaxial loayer 21 is formed with dopant well 22; The doping type of the doping type of said dopant well 22 and said epitaxial loayer 21 is opposite; Being specially the P type in the present embodiment mixes; Its formation method can be injected for said epitaxial loayer 21 being carried out ion, thereby forms dopant well 22 on the surface of epitaxial loayer 21.Those skilled in the art can select the doping content of said epitaxial loayer 21 and dopant well 22 as required.
With reference to figure 2 and Fig. 4, execution in step S22 forms groove, and said groove runs through said dopant well, and bottom and sidewall expose said epitaxial loayer.Concrete, forming groove 22a, said groove 22a runs through said dopant well 22, and its bottom and sidewall expose said epitaxial loayer 21.The formation method of said groove 22a comprises: form photoresist and graphical on the surface of said dopant well 22, define the figure of said groove 22a; With said photoresist figure is that mask carries out etching, carve and wear said dopant well 22, and the part of the said epitaxial loayer 21 of etching, bottom and the sidewall of the feasible groove 22a that forms expose said epitaxial loayer 21.Those skilled in the art can confirm concrete etching depth according to the transistorized parameter of UMOS of need preparation.
Referring to figs. 2 and 5, execution in step S23, in the surface portion of the epitaxial loayer of said channel bottom, form the transoid doped region, the doping type of said transoid doped region and said epitaxial loayer is opposite.Concrete, forming transoid doped region 23 in the surface portion of the epitaxial loayer 21 bottom said groove 22a, the doping type of the doping type of said transoid doped region 23 and said epitaxial loayer 21 is opposite, is specially the P type in the present embodiment and mixes.
The forming process of said transoid doped region 23 comprises: the epitaxial loayer 21 of said groove 22a bottom is carried out ion inject, the doping type of the ionic type of injection and epitaxial loayer 21 is opposite, and the energy of ion injection is 20 to 30KeV, and dosage is 1e13 to 5e13/cm
2Thereby form transoid doped region 23 in the surface portion of the epitaxial loayer 21 bottom said groove 22a.The depth d of said transoid doped region 23 account for said groove 22a below epitaxial loayer 21 depth D 10% to 20%.
As a preferred embodiment; The forming process of said transoid doped region 23 comprises: to the bottom of said groove 22a and carry out ion with the epitaxial loayer 21 of bottom adjacent grooves 22a sidewall and inject; The ionic type that injects is opposite with the doping type of epitaxial loayer 21; The energy that ion injects is 20 to 30KeV, and dosage is 1e13 to 5e13/cm
2, can change the scope of injection through regulating implant angle.Thereby form transoid doped region 23 bottom said groove 22a and in the surface of the epitaxial loayer 21 of the sidewall adjacent with the bottom, promptly said transoid doped region 23 surrounds the bottom of said groove 22a and the partial sidewall adjacent with the bottom.The depth d of said transoid doped region 23 account for said groove 22a below epitaxial loayer 21 depth D 10% to 20%.
Referring to figs. 2 and 6, execution in step S24 forms gate dielectric layer, covers the bottom and the sidewall of said groove.Concrete, forming gate dielectric layer 24, said gate dielectric layer 24 covers bottom and the sidewall of said groove 22a.The material of said gate dielectric layer 24 can be silica, and its formation method is a chemical vapor deposition (CVD).
With reference to figs. 2 and 7, execution in step S25 forms gate electrode on the surface of said gate dielectric layer, fills up said groove.Concrete, forming gate electrode 25, said gate electrode 25 is positioned on the surface of gate dielectric layer 24, fills up said groove.
In conjunction with Fig. 6, in one embodiment, the formation method of said gate dielectric layer 24 and gate electrode 25 can comprise: on the surface of bottom, sidewall and the dopant well 22 of said groove 22a, form gate dielectric membrane; On said gate dielectric membrane, form the gate electrode film; Said gate electrode film fills up said groove 22a, afterwards, said gate dielectric membrane and gate electrode film is carried out planarization; To the surface that exposes said dopant well 22, thereby form said gate dielectric layer 24 and gate electrode 25.
With reference to figure 2 and Fig. 8, in said dopant well, form the source region, said source region is adjacent with said gate dielectric layer, and its doping type is opposite with said dopant well.Concrete, in said dopant well 22, forming source region 26 and source region 29, said source region 26 is adjacent with said gate dielectric layer 24 with source region 29, and its doping type is opposite with said dopant well 22, is specially N in the present embodiment
+Type mixes.In addition, also comprise: in said dopant well 22, form tagma 27 and tagma 28, its doping type is identical with said dopant well 22, is specially P in the present embodiment
+Type mixes.
Need to prove that what form in the present embodiment is the UMOS transistor of N type, according to actual needs, each rete can also adopt opposite doping type in above-mentioned each step, thereby forms the UMOS transistor of P type, repeats no more here.
So far, the transistorized structure of the UMOS of formation is as shown in Figure 8, comprising: the semiconductor-based end 20; Epitaxial loayer 21 is formed at at said the semiconductor-based end 21; Dopant well 22 is formed at the surface of said epitaxial loayer 21, and doping type is opposite with said epitaxial loayer 21; Groove runs through said dopant well 22, and bottom and sidewall expose said epitaxial loayer 21; Transoid doped region 23 is formed in the surface portion of epitaxial loayer 21 of said channel bottom, and doping type is opposite with said epitaxial loayer 21; Gate dielectric layer 24 covers the bottom and the sidewall of said groove; Gate electrode 25 is formed at the surface of said gate dielectric layer 24 and fills up said groove; Source region 26 and source region 29 are positioned at said dopant well 22 and adjacent with said gate dielectric layer 24.In addition, also comprise tagma 27 and tagma 28, be formed in the said dopant well 22 that its doping type is identical with said dopant well.
The UMOS transistor that has comprised 2 symmetries in the said structure, one of them UMOS transistor comprises: epitaxial loayer 21 (as drain electrode), dopant well 22, source region 26 (as source electrode), tagma 27 (as the body electrode), gate dielectric layer 24 and gate electrode 25; Another one UMOS transistor comprises: epitaxial loayer 21 (as drain electrode), dopant well 22, source region 29 (as source electrode), tagma 28 (as the body electrode), gate dielectric layer 24 and gate electrode 25.
Owing in the surface portion of the epitaxial loayer 21 of said channel bottom, formed the opposite transoid doped region 23 of doping type and epitaxial loayer 21; Therefore reduced the overlapping area of gate electrode 24 and epitaxial loayer 21; Be equivalent between gate electrode 24 and epitaxial loayer 21, be connected in series a knot (PN junctions of transoid doped region 23 and epitaxial loayer 21 formations) electric capacity; Thereby reduced gate leakage capacitance, be beneficial to the reduction circuit power consumption.As a preferred embodiment, said transoid doped region 23 also extends in the epitaxial loayer with said channel bottom adjacent grooves sidewall, thereby has further reduced the overlapping area of gate electrode 24 and epitaxial loayer 21, has reduced gate leakage capacitance.
The inventor has carried out software simulation emulation to the UMOS transistor that present embodiment forms, and contrasts in the UMOS transistor of the same size of prior art, sees Fig. 9 and Figure 10.
Among Fig. 9; Curve 31 is the transistorized voltage of the UMOS of prior art-gate leakage capacitance curve; The transistorized voltage of UMOS-gate leakage capacitance curve that curve 32 forms for present embodiment; Visible by simulation result, the transistorized gate leakage capacitance of the UMOS of present embodiment is significantly less than the UMOS transistor of prior art.
Among Figure 10; Curve 41 is the transistorized voltage-to-current curve of the UMOS of prior art; The transistorized voltage-to-current curve of UMOS that curve 42 forms for present embodiment, visible by simulation result, the transistorized puncture voltage (Vbd of the UMOS of present embodiment; Voltage Break Down) obviously greater than the UMOS transistor of prior art, has better device performance.
To sum up, the present technique scheme has formed the transoid doped region opposite with the epitaxial loayer doping type in the surface portion of the epitaxial loayer of channel bottom, reduced the transistorized gate leakage capacitance of UMOS, is beneficial to the reduction circuit power consumption.
In addition, the present technique scheme also is beneficial to and improves the transistorized puncture voltage of UMOS, improves device performance.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (12)
1. the transistorized formation method of UMOS is characterized in that, comprising:
The semiconductor-based end is provided, is formed with epitaxial loayer at said the semiconductor-based end, the surface of said epitaxial loayer is formed with dopant well, and the doping type of said dopant well and said epitaxial loayer is opposite;
Form groove, said groove runs through said dopant well, and bottom and sidewall expose said epitaxial loayer;
In the surface portion of the epitaxial loayer of said channel bottom, form the transoid doped region, the doping type of said transoid doped region and said epitaxial loayer is opposite;
Form gate dielectric layer, cover the bottom and the sidewall of said groove;
Surface at said gate dielectric layer forms gate electrode, fills up said groove;
In said dopant well, form the source region, said source region is adjacent with said gate dielectric layer, and its doping type is opposite with said dopant well.
2. the transistorized formation method of UMOS according to claim 1; It is characterized in that; Forming the transoid doped region in the surface portion of said epitaxial loayer at said channel bottom comprises: the epitaxial loayer of said channel bottom is carried out ion inject, the ionic type that said ion injects is opposite with the doping type of said epitaxial loayer.
3. the transistorized formation method of UMOS according to claim 1; It is characterized in that; Forming the transoid doped region in the surface portion of said epitaxial loayer at said channel bottom comprises: to said channel bottom and carry out ion with the epitaxial loayer of bottom adjacent grooves sidewall and inject, the ionic type that said ion injects is opposite with the doping type of said epitaxial loayer.
4. according to claim 2 or the transistorized formation method of 3 described UMOS, it is characterized in that the injection energy that said ion injects is 20 to 30KeV, implantation dosage is 1e13 to 5e13/cm
2
5. the transistorized formation method of UMOS according to claim 1 is characterized in that, the degree of depth of said transoid doped region account for said beneath trenches epitaxial loayer the degree of depth 10% to 20%.
6. the transistorized formation method of UMOS according to claim 1; It is characterized in that the doping type of the said semiconductor-based end and epitaxial loayer is the N type, the doping type of said dopant well is the P type; The doping type of said transoid doped region is the P type, and the doping type in said source region is the N type.
7. the transistorized formation method of UMOS according to claim 1 is characterized in that, also comprises: in said dopant well, form the tagma, its doping type is identical with said dopant well.
8. a UMOS transistor is characterized in that, comprising:
The semiconductor-based end;
Epitaxial loayer is formed at at said the semiconductor-based end;
Dopant well is formed at the surface of said epitaxial loayer, and doping type is opposite with said epitaxial loayer;
Groove runs through said dopant well, and bottom and sidewall expose said epitaxial loayer;
The transoid doped region is formed in the surface portion of epitaxial loayer of said channel bottom, and doping type is opposite with said epitaxial loayer;
Gate dielectric layer covers the bottom and the sidewall of said groove;
Gate electrode is formed at the surface of said gate dielectric layer and fills up said groove;
The source region is positioned at said dopant well and adjacent with said gate dielectric layer.
9. UMOS transistor according to claim 8 is characterized in that, said transoid doped region extends to the epitaxial loayer with said channel bottom adjacent grooves sidewall.
10. UMOS transistor according to claim 8 is characterized in that, the degree of depth of said transoid doped region account for said beneath trenches epitaxial loayer the degree of depth 10% to 20%.
11. UMOS transistor according to claim 8; It is characterized in that the doping type of the said semiconductor-based end and epitaxial loayer is the N type, the doping type of said dopant well is the P type; The doping type of said transoid doped region is the P type, and the doping type in said source region is the N type.
12. UMOS transistor according to claim 8 is characterized in that, also comprises the tagma, is formed in the said dopant well, its doping type is identical with said dopant well.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104409334A (en) * | 2014-11-06 | 2015-03-11 | 中航（重庆）微电子有限公司 | Method for preparing super junction device |
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| CN104409334A (en) * | 2014-11-06 | 2015-03-11 | 中航（重庆）微电子有限公司 | Method for preparing super junction device |
| CN104409334B (en) * | 2014-11-06 | 2017-06-16 | 中航（重庆）微电子有限公司 | A kind of preparation method of superjunction devices |
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