CN102522996B - Decoding method and decoding device of FM0 coded data - Google Patents
Decoding method and decoding device of FM0 coded data Download PDFInfo
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Abstract
The invention discloses a decoding method and a decoding device of FM0 coded data, aiming to reduce demand on performances of hardware chips. The method comprises the steps of obtaining to-be-decoded data in a buffer memory area, wherein the to-be-decoded data are obtained by inputting waveforms for capturing and collecting the FM0 coded data by a timer; comparing the to-be-decoded data with threshold values; and determining decoded data according to comparison results.
Description
Technical field
The present invention relates to communication technical field, particularly a kind of coding/decoding method of FM0 coded data and device.
Background technology
Electronic charging system without parking (Electronic Toll Collection system, ETC system) adopt Dedicated Short Range Communications, (Dedicated ShortRange Communication, DSRC) technology, complete roadside unit (Roadside Unit, RSU) with board units (On Board Unit, OBU) two-way communication between, wirelessly carry out safety certification and consumption is withholdd, realize non-parking charge, greatly accelerate vehicle pass-through speed, decrease the congestion of charge ring road mouth, improve the transport power of highway.
All carry out ETC system construction throughout the country at present, in order to realize interconnecting of ETC equipment, RSU and the OBU equipment in ETC system must meet the technical requirement of GB GB/T20851-2007.The physical layer of GB/T20851.1-2007 to this professional junction service has done clear and definite regulation, in the coded system of communication, domestic most equipment manufacturer adopts category-A FM0 to encode, and RSU sends to the bit rate of OBU to be 256kbit/s, and bit clock precision is ± 100 × 10
-5; OBU sends to the bit rate of RSU to be 512kbit/s, and bit clock precision is ± 100 × 10
-6.
In order to ensure that vehicle completes whole transaction flow at the volley, need to complete transaction with the shortest time.Therefore, the speed of data decode speed affects the length of whole exchange hour.
The full name of FM0 coding is two-phase space code coding, is characterized in that in a position window, adopt level to change carrys out presentation logic.If level overturns from the section start of position window, then presentation logic " 1 ".If level overturns except the section start of window in place, also window intermediate flipped in place then presentation logic " 0 ".Fig. 1 is the level waveforms of data flow " 01100101 " after FM0 coding.
According to FM0 coding rule, the duration in the cycle of the pulse that " 1 " is corresponding is greater than the duration in the cycle of pulse corresponding to " 0 ".Therefore, in the decode procedure of FM0 coded data, measure the duration of each pulse period, by time grow up and be defined as " 1 ", be defined as little for duration half " 0 ", two continuous print half " 0 " merged into a data " 0 ".Such as: for 256kbps speed data, the pulse period being 3.9us lasting duration is defined as 1, and lasting duration is the pulse period of 1.95us be defined as half 0; For 512kbps speed data, the pulse period being 1.95us lasting duration is defined as 1, and lasting duration is the pulse period of 0.977us be defined as half 0.
At present, gathered the duration of each pulse period in FM0 coded data by the mode of timer count, specifically comprise: namely each hopping edge gathers the count value of a timer, be saved in corresponding register; Then current count value is deducted a upper count value, the duration of current period can be obtained.
Because needs go image data in each hopping edge, for the FM0 coded data of 256kbps speed, timer can collect data every 1.95us or 3.9us, and data are saved in corresponding register; For 512Kbps speed FM0 coded data, timer can collect data every 0.977us or 1.95us, and data are saved in corresponding register.So, data in the register that timer is corresponding are when decoding 256kbps data, understand 1.95us the soonest to upgrade once, and when decoding 512kbps data, understand 0.977us the soonest to upgrade once, this just needs microprocessor (Mirco Control Unit, MCU) to have enough fast speed, can complete decoding before the update.
Suppose that the decode time that MCU completes 1bit FM0 coded data needs 30 clock cycle, enter to gather and interrupt reading and collect data and need 25 clock cycle, then real-time decoding 256kbps waved theory needs dominant frequency 28M IPs (Instructions per second, the instruction number of execution per second) above MCU to realize real-time decoding; Real-time decoding 512kbps waveform, the theoretical minimum above MCU of dominant frequency 56M IPs that needs could realize real-time decoding.In practical implementation, RF transceiver is not all desirable transceiver, before packet, there will be a lot of clutter after bag, need MCU to process, want reliable decoding in true environment for use, need MCU to process these interference, just need the MCU of more high primary frequency to realize.
Special for 512kbps speed data, its Data Update is spaced apart 0.977us, and data rate fast like this, beyond the disposal ability of single-chip microcomputer, therefore, needs to use FPGA or two-forty chip to gather decoding FM0 coded data.
During decoding FM0 coded data, most of resource of chip is used for image data, only has little part resource for decoding, and this just requires that single-chip microcomputer provides a large buffer zone to preserve the data of collection, simultaneously can not in real time data decode out; Further, for 512kbps speed FM0 coded data, chip is costly needed to realize gathering and decoding.
Therefore, in existing FM0 coded data decode procedure, the frequency ratio of image data is very fast, and namely Data Update is than very fast, higher to the performance requirement of hardware chip.Further, once decoding can only be determined one " 1 " or half " 0 ", and like this, whole decode procedure is slow, and the decode rate of high performance hardware chip is not high yet.
Summary of the invention
The embodiment of the present invention provides a kind of coding/decoding method and device of FM0 coded data, in order to reduce the requirement to the performance of hardware chip.
The embodiment of the present invention provides a kind of coding/decoding method of FM0 coded data, comprising:
Obtain the data to be decoded in buffer area, wherein, described data to be decoded gather the waveform acquisition of described FM0 coded data by timer input capture;
Described data to be decoded and threshold value are compared, according to comparative result determination decoded data.
The embodiment of the present invention provides a kind of decoding device of FM0 coded data, comprising:
Acquiring unit, for obtaining the data to be decoded in buffer area, wherein, described data to be decoded gather the waveform acquisition of described FM0 coded data by timer input capture;
Decoding unit, for described data to be decoded and threshold value being compared, according to comparative result determination decoded data.
In the embodiment of the present invention, obtain the data to be decoded in buffer area, and described data to be decoded and threshold value are compared, according to comparative result determination decoded data, wherein, data to be decoded gather the waveform acquisition of described FM0 coded data by timer input capture.Data to be decoded are obtained owing to adopting the mode of timer input capture, like this, when only collecting the specific hopping edge of the waveform of FM0 coded data, just obtain data to be decoded, and be not obtain data to be decoded in each hopping edge of the waveform collecting FM0 coded data, thus, reduce the frequency of image data, reduce the performance requirement to hardware chip, reduce further the resources costs in decode procedure.
Accompanying drawing explanation
Fig. 1 is the level waveforms schematic diagram in prior art after FM0 coding;
Fig. 2 is the block diagram of PWM input capture hardware in the embodiment of the present invention one;
Fig. 3 is PWM real work sequential chart in the embodiment of the present invention one;
Fig. 4 is the flow chart of the decoding of FM0 coded data in the embodiment of the present invention one;
Fig. 5 is the decoding process figure of the first data to be decoded in the embodiment of the present invention one;
Fig. 6 is PWM input capture sequential chart in the specific embodiment of the invention one embody rule;
Fig. 7 is the block diagram of PWM input capture hardware in the embodiment of the present invention two;
Fig. 8 is PWM real work sequential chart in the embodiment of the present invention two;
Fig. 9 is the flow chart of the decoding of FM0 coded data in the embodiment of the present invention two;
Figure 10 is the decoding process figure of the first data to be decoded in the embodiment of the present invention two;
Figure 11 is PWM input capture sequential chart in the specific embodiment of the invention two embody rule;
Figure 12 is the structure chart of the decoding device of FM0 coded data in the embodiment of the present invention.
Embodiment
In the embodiment of the present invention, in the process that FM0 coded data is decoded, the waveform being gathered FM0 coded data by timer input capture obtains data to be decoded, then these data to be decoded and threshold value is compared, according to comparative result determination decoded data.Like this, when only collecting the specific hopping edge of the waveform of FM0 coded data, just obtain data to be decoded, thus, add the cycle gathering data to be decoded, reduce the frequency of image data, reduce the performance requirement to hardware chip.
In the embodiment of the present invention, timer has multiple input capture pattern, such as: single register input capture pattern, PWM input capture pattern.Like this, after timer is pre-configured certain input capture pattern, the waveform of FM0 coded data can be gathered by the input capture pattern of configuration, data to be decoded can be obtained.
Embodiment one, in the present embodiment, timer is single register input capture pattern, and this single register input capture pattern is an expansion of timer function, corresponding with timer only has a register, and an input is set to rising edge or trailing edge detection port.Input capture hardware as shown in Figure 2, timer is with to catch register corresponding.Like this, outer wave enters into MCU by CH2, at internal links to marginal detector.When CH2 detects corresponding edge, the value of timer is saved in automatically and catches in register, juxtaposition interrupt flag bit, and reset timer at timer edge subsequently.If open this timer interruption, then enter interrupt function at once process.
In single register input capture pattern, the effective or trailing edge of rising edge is effectively by being configured acquisition to MCU, therefore, before the decoding carrying out FM0 coded data, also need to be configured, comprise: timer is configured to single register input capture pattern and according to the speed of FM0 coded data, and the count frequency of the frequency division determination timer of setting.Wherein, can be that the first hopping edge or the second hopping edge are effective by the catch register configuration corresponding with timer, interrupt enable.Here, the first hopping edge is rising edge or trailing edge.And the second hopping edge is for falling edge or rising edge.Namely the first hopping edge is contrary with the second hopping edge.
Generally be configured to by timer in single register input capture mode process, can by the clock source configuration-system clock of timer, and be configured to by timer upwards count, configuration timer input channel 2 is single register input input capture mode.And configure interrupt is enable comprises configure interrupt vector.
After completing the configuration to input capture by said process, input capture real work sequential can see Fig. 3, and wherein, timer is single register input input capture pattern, and it is effective that passage 2 (CH2) is configured to rising edge, interrupts enable.
When catching waveform A point (rising edge), CH2 passage triggers, and the value 0004 of timer is saved in and catches in register, put interrupt flag bit triggered interrupts, in the D moment point that timer count changes, timer resets, namely still from 0000.
When C point (rising edge), CH2 passage triggers, and timer value 0004 is saved in catches in register, puts interrupt flag bit triggered interrupts, and at the F point that timer count changes, timer resets.
Single register input capture, only produces at the rising edge of waveform and interrupts, in interruption, the value of register is defined as data to be decoded, and is read in buffer area, for decoding.Such as: when C point, produce and interrupt, the value 0004 of register is defined as data to be decoded, and is read in buffer area.
Data to be decoded will be obtained stored in after in buffer area by single register input capture pattern by interrupt mode, to the process of the decoding of FM0 coded data see Fig. 4, comprise:
Step 401: obtain the data to be decoded in buffer area, wherein, these data to be decoded gather the waveform acquisition of FM0 coded data by timer input capture.
Due to data to be decoded by interrupt mode stored in buffer area, the data to be decoded that the waveform by single register input capture type collection FM0 coded data obtains are deposited into buffer area here.Like this, when decoding, in buffer area, data to be decoded are stored.
Here, data to be decoded can be obtained according to the mode of first in first out from buffer area.Certainly, also data to be decoded can be obtained according to other order from buffer area, like this, also need according to the order of setting when exporting decoded data.
Step 402: the data to be decoded obtained and threshold value are compared, according to comparative result determination decoded data.
Owing to being obtain data to be decoded by the waveform of FM0 coded data described in single register input capture type collection, like this, when only collecting rising edge or the trailing edge of the waveform of FM0 coded data, just obtain data to be decoded, therefore, in the value of data to be decoded, minimum value corresponds to the duration corresponding to two continuous print half " 0 ", maximum corresponds to duration corresponding to two continuous print " 1 ", between maximum and minimum value, correspond to one " 1 " and the duration corresponding to half " 0 ".Therefore, in the invention process, first according to the value of data to be decoded whether within the scope of minimum value, determine that decoded data is two continuous print half " 0 "; Then according to the value of data to be decoded whether in maximum range, determine that decoding is according to being two continuous print " 1 "; The number of times finally occurred in the threshold space be made up of maximum and minimum value according to the value of data to be decoded determines " 1 " data in front or half " 0 " data front.Detailed process comprises:
When the value of data to be decoded is less than or equal to first threshold, determine that decoded data is one 0; When the value of data to be decoded is more than or equal to Second Threshold, determine that decoded data is two 1; When the value of data to be decoded is between first threshold and Second Threshold, according to the number of times that the value of data to be decoded occurs in the threshold space be made up of first threshold and Second Threshold, to determine in decoded data " 1 " data in front still " 0 " data front.Wherein,
In the embodiment of the present invention, first threshold being set as providing a wrong redundancy, and increase certain error by the duration that two continuous print half " 0 " are corresponding, such as, increasing by the error of 10% or 5%; Second Threshold is set as the duration that two continuous print " 1 " are corresponding, and reduces certain error, such as, reduce by the error of 10% or 5%.
The concrete decode procedure of each data to be decoded see Fig. 5, can comprise:
Step 501: judge whether the value of data to be decoded is less than or equal to first threshold, if so, determines that decoded data is one 0; Otherwise, perform step 502.
Step 502: judge whether the value of data to be decoded is more than or equal to Second Threshold, if so, determines that decoded data is two 1; Otherwise, perform step 503.
Step 503: the number of times that the value of data to be decoded occurs in the threshold space be made up of first threshold and Second Threshold is added 1, obtains the number of times after upgrading.
Carrying out in decode procedure, a variable can be set, the number of times that the value in order to record data to be decoded occurs in the threshold space be made up of first threshold and Second Threshold.Before decoding, the value of this variable is zero, and then the value of data to be decoded often occurs once in the threshold space be made up of first threshold and Second Threshold, just the value of this variable is added 1.
Like this, when decoding first, the number of times that the value of these data to be decoded occurs in the threshold space be made up of first threshold and Second Threshold is zero.Along with decoding one by one, the number of times that the value of data to be decoded occurs in the threshold space be made up of first threshold and Second Threshold can increase.After all decodings terminate, this variable can be reset, the number of times that the value by these data to be decoded occurs in the threshold space be made up of first threshold and Second Threshold can be reset to zero.
Step 504: judge after upgrading to number of times whether be odd number, if so, determine that decoded data is 1 add half 0; Otherwise, determine that decoded data is add 1 half 0.
Certainly, step 501 and 502 sequencings can be exchanged, and first can judge whether the value of data to be decoded is more than or equal to Second Threshold, then judge whether the value of data to be decoded is less than or equal to first threshold, and detailed process has just been not repeated.
In an embody rule of the present embodiment, the speed of FM0 coded data is 256kbps when being configured, and timer clock source is system clock, the frequency division of clock is 32, like this, be configured to input capture trailing edge pattern, the count frequency of timer is 256*32*2=16384khz.
As shown in Figure 6, the waveform of input capture FM0 coded data has 4 kinds of situations to input capture trailing edge sequential chart, and be A, B, D and F respectively, here, C, E and A are identical.
Due to, the data of catching have three kinds of length, and, suppose that timer count frequency is 8192KHz, decoding 256kbps speed FM0 coding, then:
A section count value is 64;
B section count value is 128;
C section count value is 64;
D section count value is 96;
E section count value is 64;
F section count value is 96.
Therefore, in the present embodiment, first threshold is defined as 64* (1+10%)=70, Second Threshold is defined as 128* (1-10%)=115 so the decode procedure of every section comprise:
Count value C2=64 < 70, namely corresponding decoded data is two continuous print half 0.
Count value C2=128 > 115, namely corresponding decoded data is two continuous print 1.
Count value C2=64 < 70, namely corresponding decoded data is two continuous print half 0.
Count value C2=96, due to 70 < C2=96 < 115, occurrence number is 1, is odd number, and namely corresponding decoded data is 1 add half 0.
Count value C2==64 < 70, namely corresponding decoded data is two continuous print half 0.
Count value C2C2=96, due to 70 < C2=96 < 115, occurrence number is 2, is even number, and namely corresponding decoded data is add 1 half 0.
Two continuous print half 0, are one 0, thus obtaining decoded data is " 01101001 ".
In the above-described embodiments, trailing edge, along effectively, interrupt enable, but the embodiment of the present invention is not limited thereto, also can by rising edge along being configured to effectively, and interrupt enable, embody rule has been not repeated.
In embodiment two, the present embodiment, timer is PWM (Pulse Width Modulation, pulse width modulation) input capture pattern.
The PWM input capture pattern of MCU is an expansion of the different input capture of timer, and same input is mapped to two hopping edge detection port of timer, i.e. corresponding two registers of timer.PWM input capture hardware as shown in Figure 7, outer wave enters into MCU by CH2, at the hopping edge detector of internal links to CH1 and CH2.CH1 and CH2 hopping edge detector polarity is contrary, when CH1 hopping edge detector detects corresponding hopping edge, the value of timer is saved in CC1 register automatically; When CH2 detects corresponding hopping edge, the value of timer is saved in CC2 register automatically, juxtaposition interrupt flag bit, and resets timer in timer hopping edge subsequently.If open this timer interruption, then enter interrupt function at once process.
PWM input capture pattern is by being configured acquisition to MCU timer, therefore, before the decoding carrying out FM0 coded data, also need to be configured, comprising: timer is configured to PWM input capture pattern, and according to the speed of FM0 coded data, and the count frequency of the frequency division determination timer of setting, wherein, be that the second hopping edge is effective by the second register configuration corresponding with timer, interrupt enable; And be that the first hopping edge is effective by the first register configuration corresponding with timer.
Generally be configured to by timer in PWM input capture mode process, by the clock source configuration-system clock of timer, and be configured to by timer upwards count, configuration timer input channel 1 and 2 is PWM input capture mode.
And configurating terminal is enable comprises configure interrupt vector.
After completing the configuration to PWM input capture by said process, PWM real work sequential can see Fig. 8, and wherein, timer is PWM input capture pattern, and it is effective that passage 2 (CH2) is configured to rising edge, interrupts enable.
When catching waveform A point (rising edge), CH2 passage triggers, and the value 0004 of timer is saved in CC2 register, puts interrupt flag bit triggered interrupts, and in the D moment point that timer count changes, timer resets, namely still from 0000.
When B point (trailing edge), CH1 passage triggers, and timer value 0002 is saved in CC1 register;
When C point (rising edge), CH2 passage triggers, and timer value 0004 is saved in CC2 register, puts interrupt flag bit triggered interrupts, and at the F point that timer count changes, timer resets.
During PWM input capture, only produce at the rising edge of waveform and interrupt, in interruption, the value of CC1 and CC2 is defined as data to be decoded simultaneously, and is read in buffer area, for decoding.Such as: when C point, produce and interrupt, simultaneously by the value 0002 of CC1, and the value 0004 of CC2 is defined as data to be decoded, and is read in buffer area.
As can be seen here, the process that the waveform that PWM input capture mode gathers FM0 coded data obtains data to be decoded comprises: when being collected the second hopping edge in the waveform of FM0 coded data by PWM input capture, be worth first of the first register, and second second value of register be defined as data to be decoded, and be read in buffer area, wherein, the value of the first register is value when collecting the first hopping edge in the waveform of FM0 coded data by PWM input capture in timer, the value of the second register is value when collecting the second hopping edge in the waveform of FM0 coded data by PWM input capture in timer, second hopping edge is contrary with the first hopping edge.
By interrupt mode by data to be decoded stored in after in buffer area, to the process of the decoding of FM0 coded data see Fig. 9, comprising:
Step 901: obtain the data to be decoded in buffer area, wherein, these data to be decoded gather the waveform acquisition of FM0 coded data by PWM input capture.
Due to data to be decoded by interrupt mode stored in buffer area, the data to be decoded that the waveform being about to gather FM0 coded data by PWM input capture obtains are deposited into buffer area.Like this, when decoding, in buffer area, data to be decoded are stored.
Here, data to be decoded can be obtained according to the mode of first in first out from buffer area.Certainly, also data to be decoded can be obtained according to other order from buffer area, like this, also need according to the order of setting when exporting decoded data.
Step 902: the data to be decoded obtained and threshold value are compared, according to comparative result determination decoded data.
Owing to being that the waveform gathering described FM0 coded data by PWM input capture obtains data to be decoded, like this, when only collecting the specific hopping edge of the waveform of FM0 coded data, just obtain data to be decoded, therefore, in data to be decoded second register the second value in minimum value should correspond to duration corresponding to two continuous print half " 0 ", and the maximum in the second value should correspond to duration corresponding to two continuous print " 1 ".And in data to be decoded first register the first value in maximum should correspond to duration corresponding to half " 0 ", and the maximum in the first value should correspond to duration corresponding to one " 1 ".Therefore, in the invention process, first determine decoded data according to the second value, if decoded data can not be determined according to the second value, then determine decoded data according to the first value.Detailed process comprises:
When second value of the second register is less than or equal to the 3rd threshold value in data to be decoded, determine that decoded data is one 0; When the second value is more than or equal to the 4th threshold value, determine that decoded data is two 1; When the second value is between the 3rd threshold value and the 4th threshold value, the first value of the first register in data to be decoded and the 5th threshold value are compared, according to comparative result determination decoded data, wherein, the 5th threshold value is less than the 3rd threshold value, and the 3rd threshold value is less than the 4th threshold value.
Namely first the second value and the 3rd threshold value are compared, if according to comparative result, decoded data can not be determined, then the second value and the 4th threshold value are compared, if according to comparative result, decoded data can not be determined, finally, decoded data is determined according to the first value, compare by the first value and the 5th threshold value, according to comparative result determination decoded data, wherein, when the first value is greater than the 5th threshold value, determine that decoded data is 1 add half 0; When the first value is less than or equal to the 5th threshold value, determine that decoded data is add 1 half 0.
In the embodiment of the present invention, the 3rd threshold value being set as providing a wrong redundancy, and increase certain error by the duration that two continuous print half " 0 " are corresponding, such as, increasing by the error of 10% or 5%; 4th threshold value is set as the duration that two continuous print " 1 " are corresponding, and reduces certain error, such as, reduce by the error of 10% or 5%; 5th threshold value is set between duration corresponding to half " 0 " duration corresponding with " 1 ", and error corresponding to certain wrong redundancy can gives.As can be seen here, in the present embodiment, the 3rd threshold value can be equal with the first threshold in embodiment one, and the 4th threshold value can be equal with the Second Threshold in embodiment one.
The concrete decode procedure of each data to be decoded see Figure 10, can comprise:
Step 1001: judge whether the second value of the second register in data to be decoded is less than or equal to the 3rd threshold value, if so, determines that decoded data is one 0; Otherwise, perform step 1002.
Step 1002: judge whether the second value of the second register in data to be decoded is more than or equal to the 4th threshold value, if so, determines that decoded data is two 1; Otherwise, perform step 1003.
Step 1003: judge whether the first value of the first register in data to be decoded is greater than the 5th threshold value, if so, determines that decoded data is 1 add half 0; Otherwise, determine that decoded data is add 1 half 0.
Certainly, step 1001 and 1002 sequencings can be exchanged, and first can judge whether the second value is more than or equal to the 4th threshold value, then judge whether the second value is less than or equal to the 3rd threshold value, and detailed process has just been not repeated.
In an embody rule of the present embodiment, the speed of FM0 coded data is 256kbps when being configured, and timer clock source is system clock, the frequency division of clock is 32, like this, will be configured to PWM input capture pattern, the count frequency of timer is 256*32*2=16384khz.And configure, second register corresponding with timer is that trailing edge is effective, and terminal is enable, thus first register corresponding with timer is that rising edge is effective.
As shown in figure 11, the waveform of PWM input capture FM0 coded data has 4 kinds of situations to PWM input capture sequential chart, and be A, B, C and E respectively, here, D, F and A are identical.
Second value C2 value of the second register has three kinds of situations, be respectively C2, B section of A section C2 and, the C2 of C or E section.First value C1 value of the first register only has two kinds, is the C1 of A or E section respectively, and, the C1 of B or C section.Enter interruption when being located at each trailing edge outside PWM input capture, in interrupt routine, the value of these two registers of CC1 and CC2 is read in buffer area as data to be decoded, then decode according to two values of this in data to be decoded.
Due to, the C2 segment data of catching has three kinds of length, and C1 segment data has two kinds of length, and, suppose that timer count frequency is 8192KHz, decoding 256kbps speed FM0 coding, then:
G section C2 count value is 64, C1 count value is 32;
H section C2 count value is 128, C1 count value is 64;
I section C2 count value is 96, C1 count value is 64;
J section C2 count value is 64, C1 count value is 32;
K section C2 count value is 96, C1 count value is 32;
L section C2 count value is 64, C1 count value is 32.
Therefore, in the present embodiment, 3rd threshold value is defined as 64* (1+10%)=70,4th threshold value is defined as 128* (1-10%)=115,5th threshold value is defined as 32* (1+10%)=35, and any one number between 64* (1-10%)=58, here, can say that the 5th threshold value is defined as (32+64) ÷ 2=48, so the decode procedure of every section comprises:
C2=64 < 70, namely corresponding decoded data is two continuous print half 0.
C2=128 > 115, namely corresponding decoded data is two continuous print 1.
70 < C2=96 < 115, C1=64 > 48, namely corresponding decoded data is 1 add half 0.
C2=64 < 70, namely corresponding decoded data is two continuous print half 0.
70 < C2=96 < 115, C1=32 < 48, namely corresponding decoded data is add 1 half 0.
C2=64 < 70, namely corresponding decoded data is two continuous print half 0.
Two continuous print half 0, are one 0, thus obtaining decoded data is " 01110010 ".
In the above-described embodiments, the second hopping edge is trailing edge, but the embodiment of the present invention is not limited thereto, and the second hopping edge can be set as rising edge.
According to the coding/decoding method of above-mentioned FM0 coded data, a kind of decoding device of FM0 coded data can be built, see Figure 12, acquiring unit 100 and decoding unit 200, wherein,
Acquiring unit 100, for obtaining the data to be decoded in buffer area, wherein, described data to be decoded gather the waveform acquisition of described FM0 coded data by timer input capture.
Decoding unit 200, for described data to be decoded and threshold value being compared, according to comparative result determination decoded data.
This acquiring unit 100, for being configured to single register input capture pattern when timer, and by described single register input capture type collection to the waveform of described FM0 coded data when the first hopping edge or the second hopping edge, the value of catching in the timer of register acquisition is defined as described data to be decoded, and is read in described buffer area;
When timer is configured to PWM input capture pattern, and when being collected the second hopping edge in the waveform of described FM0 coded data by PWM input capture, be worth first of the first register, and second second value of register be defined as described data to be decoded, and be read in described buffer area, wherein, the value of described first register is value when collecting the first hopping edge in the waveform of described FM0 coded data by PWM input capture in timer, the value of described second register is value when collecting the second hopping edge in the waveform of described FM0 coded data by PWM input capture in timer, described second hopping edge is contrary with described first hopping edge.
This acquiring unit 100, also for being reset by described timer.
When timer is configured to single register input capture pattern, decoding unit 200 specifically for:
When the value of described data to be decoded is less than or equal to first threshold, determine that decoded data is one 0; When the value of described data to be decoded is more than or equal to Second Threshold, determine that decoded data is two 1; When the value of described data to be decoded is between first threshold and Second Threshold, according to the number of times that the value of described data to be decoded occurs in the threshold space be made up of first threshold and Second Threshold, determine described decoded data, wherein, described first threshold is less than described Second Threshold.
When the value of described data to be decoded is between first threshold and Second Threshold, this decoding unit 200, adds 1 specifically for the number of times value of described data to be decoded occurred in the threshold space be made up of first threshold and Second Threshold, obtains the number of times after upgrading; When the number of times after described renewal is odd-times, determine that decoded data is 1 add half 0; When the number of times after described renewal is even-times, determine that decoded data is add 1 half 0.
When timer is configured to PWM input capture pattern, decoding unit 200, specifically for:
When described second value is less than or equal to the 3rd threshold value, determine that decoded data is one 0; When described second value is more than or equal to the 4th threshold value, determine that decoded data is two 1; When described second value is between the 3rd threshold value and the 4th threshold value, determine decoded data according to described first value, wherein, described 5th threshold value is less than described 3rd threshold value, and described 3rd threshold value is less than described 4th threshold value.
When described second value is between the 3rd threshold value and the 4th threshold value, this decoding unit 200, specifically for when described first value is greater than the 5th threshold value, determines that decoded data is 1 add half 0; When described first value is less than or equal to the 5th threshold value, determine that decoded data is add 1 half 0.
This device also comprises: dispensing unit, and for described timer being configured to single register input capture pattern or PWM input capture pattern, and according to the speed of described FM0 coded data, and the frequency division of setting determines the count frequency of described timer; Wherein, when described timer is configured to single register input capture pattern, is that the first hopping edge or the second hopping edge are effective by the register configuration of catching corresponding with described timer, interrupts enable; When described timer is configured to PWM input capture pattern, is that the second hopping edge is effective by the second register configuration corresponding with described timer, interrupts enable; And be that the first hopping edge is effective by the first register configuration corresponding with described timer.
The coding/decoding method of the FM0 coded data in the embodiment of the present invention may be used for utilizing FM0 coded data to carry out in the system communicated, such as: in ETC.Certainly, in the embodiment of the present invention, before relevant title, described " first ", " second " are only for distinguishing each title, and wherein, first, second can exchange.
The embodiment of the present invention also provides a kind of communication equipment, such as OBU, RSU etc., and this equipment comprises the decoding device of FM0 coded data as above, and the decoding device of this equipment utilization FM0 coded data as above is decoded to FM0 coded data.
In the embodiment of the present invention, obtain the data to be decoded in buffer area, and described data to be decoded and threshold value are compared, according to comparative result determination decoded data, wherein, data to be decoded gather the waveform acquisition of described FM0 coded data by timer input capture.Because the mode of the input capture adopting timer obtains data to be decoded, like this, when only collecting the specific hopping edge of the waveform of FM0 coded data, just obtain data to be decoded, and be not obtain data to be decoded in each hopping edge of the waveform collecting FM0 coded data, thus, reduce the frequency of image data, reduce the performance requirement to hardware chip, reduce further the resources costs in decode procedure.Namely use the decoding of PWM input capture, make same speed data of decoding, relatively cheap chip can be used, and use same chip, can decode more high speed data or more these data of fast decoding.
Further, in the embodiment of the present invention, treat decoded data decoding and once can decode two data, such as: two continuous print, 1, two continuous print half 0, one 1 and half 0, or half 0 and one 1.Like this, improve decode rate, namely use existing PWM input capture hardware can realize the waveform of decoding FM0 coded data at a high speed.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (6)
1. a coding/decoding method for FM0 coded data, is characterized in that, comprising:
Obtain the data to be decoded in buffer area, wherein, described data to be decoded are by PWM input capture type collection to the waveform of described FM0 coded data during the second hopping edge, be worth first of the first register, and second second value of register determine, and by interrupt mode stored in buffer area, described interruption produces at the rising edge of FM0 coded data waveform or trailing edge, the value of described first register is by the value in PWM input capture type collection to the waveform of described FM0 coded data during the first hopping edge in timer, the value of described second register is by the value in PWM input capture type collection to the waveform of described FM0 coded data during the second hopping edge in timer, described second hopping edge is contrary with described first hopping edge,
Described data to be decoded and threshold value are compared;
When described second value is less than or equal to the 3rd threshold value, determine that decoded data is one 0;
When described second value is more than or equal to the 4th threshold value, determine that decoded data is two 1;
When described second value is between the 3rd threshold value and the 4th threshold value, described first value and the 5th threshold value are compared;
When described first value is greater than the 5th threshold value, determines that decoded data is 1 add half 0, when described first value is less than or equal to the 5th threshold value, determine that decoded data is add 1 half 0;
Wherein, described 5th threshold value is less than described 3rd threshold value, and described 3rd threshold value is less than described 4th threshold value.
2. the method for claim 1, is characterized in that, described in be deposited into after in described buffer area, also comprise: described timer is reset.
3. the method for claim 1, is characterized in that, in described acquisition buffer area data to be decoded before, also comprise:
Described timer is configured to PWM input capture pattern, and according to the speed of described FM0 coded data, and the frequency division of setting determines the count frequency of described timer;
Be that the second hopping edge is effective by the second register configuration corresponding with described timer, interrupt enable, and be that the first hopping edge is effective by the first register configuration corresponding with described timer.
4. a decoding device for FM0 coded data, is characterized in that, comprising:
Acquiring unit, for obtaining the data to be decoded in buffer area, wherein, described data to be decoded are by PWM input capture type collection to the waveform of described FM0 coded data during the second hopping edge, be worth first of the first register, and second second value of register determine, and by interrupt mode stored in buffer area, described interruption produces at the rising edge of FM0 coded data waveform or trailing edge, the value of described first register is by the value in PWM input capture type collection to the waveform of described FM0 coded data during the first hopping edge in timer, the value of described second register is by the value in PWM input capture type collection to the waveform of described FM0 coded data during the second hopping edge in timer, described second hopping edge is contrary with described first hopping edge,
Decoding unit, for described data to be decoded and threshold value are compared, when described second value is less than or equal to the 3rd threshold value, determine that decoded data is one 0, when described second value is more than or equal to the 4th threshold value, determine that decoded data is two 1, when described second value is between the 3rd threshold value and the 4th threshold value, described first value and the 5th threshold value are compared, when described first value is greater than the 5th threshold value, determine that decoded data is 1 add half 0, when described first value is less than or equal to the 5th threshold value, determine that decoded data is add 1 half 0, wherein, described 5th threshold value is less than described 3rd threshold value, described 3rd threshold value is less than described 4th threshold value.
5. device as claimed in claim 4, is characterized in that,
Described acquiring unit, also for being reset by described timer.
6. device as claimed in claim 4, is characterized in that, also comprise:
Dispensing unit, for described timer is configured to PWM input capture pattern, and according to the speed of described FM0 coded data, and the frequency division of setting determines the count frequency of described timer; Be that the second hopping edge is effective by the second register configuration corresponding with described timer, interrupt enable; And be that the first hopping edge is effective by the first register configuration corresponding with described timer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102522997B (en) * | 2011-12-08 | 2015-09-02 | 北京握奇数据系统有限公司 | The coding/decoding method of FM0 coded data and device |
| CN102938197A (en) * | 2012-10-26 | 2013-02-20 | 合肥移瑞通信技术有限公司 | Method for decoding infrared remote control by means of input capture interrupt mode |
| CN103731237B (en) * | 2012-12-07 | 2017-03-15 | 深圳市金溢科技股份有限公司 | Coding/decoding method, device, equipment and communication system towards two-phase space code |
| CN104639176B (en) * | 2013-11-08 | 2018-02-13 | 上海华虹集成电路有限责任公司 | The asynchronous decoder and method of BMC signals |
| CN105224481A (en) * | 2015-10-22 | 2016-01-06 | 福州瑞芯微电子股份有限公司 | PWM transmits the implementation of data in input mode |
| CN106921462B (en) * | 2015-12-25 | 2019-11-29 | 航天信息股份有限公司 | The method and apparatus being decoded are encoded to FM0 |
| CN106921466B (en) * | 2015-12-25 | 2019-11-29 | 航天信息股份有限公司 | The method and apparatus being decoded are encoded to FM0 |
| CN106921463B (en) * | 2015-12-28 | 2020-03-13 | 航天信息股份有限公司 | Anti-interference decoding method and system |
| CN106372553B (en) * | 2016-08-30 | 2019-03-01 | 成都九洲电子信息系统股份有限公司 | Flowing water matrix matching technique based on GJB Radio Frequency Identification Technology |
| CN106789517A (en) * | 2017-01-08 | 2017-05-31 | 易晓云 | CAN data link and its by turn loss arbitration method |
| CN110138501B (en) * | 2018-02-08 | 2021-09-24 | 北京万集科技股份有限公司 | Decoding method and device for FM0 codes |
| CN111327333B (en) * | 2020-03-02 | 2023-07-18 | 华润微集成电路(无锡)有限公司 | Decoding circuit |
| CN112633023B (en) * | 2020-12-18 | 2022-03-01 | 中国电子科技集团公司第五十四研究所 | Decoding method and device for national military standard RFID (radio frequency identification) tag |
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