CN102709308A - MOS (Metal Oxide Semiconductor) transistor structure integrated with resistive random access memory and manufacturing method of MOS transistor structure - Google Patents
MOS (Metal Oxide Semiconductor) transistor structure integrated with resistive random access memory and manufacturing method of MOS transistor structure Download PDFInfo
- Publication number
- CN102709308A CN102709308A CN2012102065105A CN201210206510A CN102709308A CN 102709308 A CN102709308 A CN 102709308A CN 2012102065105 A CN2012102065105 A CN 2012102065105A CN 201210206510 A CN201210206510 A CN 201210206510A CN 102709308 A CN102709308 A CN 102709308A
- Authority
- CN
- China
- Prior art keywords
- resistance
- storing device
- mos transistor
- effect transistor
- field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention belongs to the technical field of semiconductor memories and more particularly relates to an MOS (Metal Oxide Semiconductor) transistor structure integrated with a resistive random access memory and a manufacturing method of the MOS transistor structure. The MOS transistor structure integrated with the resistive random access memory, provided by the invention, comprises an MOS transistor and the resistive random access memory which are formed on a substrate, wherein a gate dielectric layer of the MOS transistor extends onto the surface of a drain region of the MOS transistor, and a resistive random access memory layer of the resistive random access memory is formed on the gate dielectric layer part which extends onto the surface of the drain region of the MOS transistor. According to the invention, the high-quality gate dielectric layer of the MOS transistor and the resistive random access memory layer of the resistive random access memory are obtained by a primary atomic layer deposition process, the resistive random access memory and the MOS transistor are integrated together, and the process steps are simple; and in addition, the manufacturing method can be compatible with a shallow trench isolation process, or a field oxide layer isolation process and a source/drain ion implantation or diffusion process and is convenient for process integration.
Description
Technical field
The invention belongs to the semiconductor memory technologies field, be specifically related to a kind of field-effect transistor structure and manufacturing approach thereof of integrated resistance-variable storing device.
Background technology
The Card read/write of resistance-variable storing device is to rely on to read or change the resistance that hinders the change material to realize.The resistance value of resistance-variable storing device can have high-impedance state and two kinds of different state of low resistance state under the applied voltage effect, it can be used for characterizing " 0 " and " 1 " two states respectively.Under different applied voltage conditions, but the resistance value of resistance-variable storing device can realize inverse conversion between high-impedance state and low resistance state, realizes the storage of information with this.Resistance-variable storing device has that preparation is simple, storage density is high, operating voltage is low, read or write speed is fast, the retention time is long, non-destructive reads, low-power consumption, and traditional cmos (be complementary metal oxide semiconductors (CMOS); CMOS is the abbreviation of Complementary Metal Oxide Semiconductor) advantage such as processing compatibility is good, be considered to one of strong candidate that becomes by next generation's " general " memory.
At present, the drive circuit of resistance-variable storing device adopts MOS transistor (be field-effect transistor, MOS is the abbreviation of Metal-Oxide-Semiconductor) structure usually, and resistance-variable storing device forms after the post-channel interconnection technology of MOS transistor is accomplished usually.The resistance-variable storing device of conventional art and the integrated morphology of MOS transistor are as shown in Figure 1, are included in and form mos transistor structure, metal interconnect structure and resistance variation memory structure on the Semiconductor substrate 100.Wherein, mos transistor structure comprises source region 101, drain region 102, gate dielectric layer 103, gate electrode 104 and insulating barrier 105, and insulating barrier 105 is isolated other conductor layer of grid region and device.Metal interconnect structure comprises zone isolation layer 106, the diffusion impervious layer 107 in the contact hole and the copper interconnecting line 108 in the ground floor interconnection, and diffusion impervious layer 111 and copper interconnecting line 112 in the etching barrier layer 109 in the second layer interconnection, zone isolation layer 110, second layer through-hole interconnection.Resistance variation memory structure comprises resistance change material layer 113 and conductive material layer 114, and insulating barrier 115 is isolated other conductor layer of resistance-variable storing device and device.
The integrated morphology of aforesaid resistance-variable storing device and MOS transistor is complicated, is unfavorable for the development of the integrated and device of the technology of device to miniaturization.
Summary of the invention
In view of this, the objective of the invention is to propose to simplify resistance-variable storing device and the integrated morphology of MOS transistor and preparation method thereof of the integrated technique step of resistance-variable storing device and MOS transistor.
For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of mos transistor structure of integrated resistance-variable storing device, this structure comprises:
A Semiconductor substrate;
MOS transistor that on said Semiconductor substrate, forms and resistance-variable storing device;
The gate dielectric layer of described MOS transistor extends on the surface, drain region of described MOS transistor;
Gate dielectric layer on the described surface, drain region that extends to MOS transistor partly forms the resistance-change memory layer of described resistance-variable storing device.
Further, described Semiconductor substrate is silicon or is the silicon on the insulator.The gate dielectric layer of described field-effect transistor is that the resistance with high dielectric constant value becomes material.
Simultaneously, the invention allows for the manufacturing approach of the mos transistor structure of above-mentioned integrated resistance-variable storing device, concrete steps comprise:
Form the ground floor insulation film at semiconductor substrate surface with first kind of doping type;
Deposit one deck photoresist on said ground floor insulation film, and mask, exposure, development define source region, the position, drain region of MOS transistor;
The said ground floor insulation film of the source region of the said MOS transistor of etching, position, drain region exposes Semiconductor substrate;
In said Semiconductor substrate, form source region and drain region through ion implantation technology or diffusion technology with second kind of doping type;
Divest photoresist;
Etch away remaining said ground floor insulation film;
Adopt atomic layer deposition technology at semiconductor substrate surface growth second layer insulation film;
Deposit forms the ground floor conductive film on said second layer insulation film;
Deposit one deck photoresist and photoetching form figure on said ground floor conductive film, and the grid region of MOS transistor is protected with photoresist;
Etch away the said ground floor conductive film that exposes, remaining said ground floor conductive film forms the grid of MOS transistor;
Divest photoresist;
Etch away the second layer insulation film of top, said source region and keep the second layer insulation film of top, said drain region, the second layer insulation film of top, said drain region forms the resistance-change memory layer of resistance-variable storing device.
Further, described ground floor insulation film is a silica.Described second layer insulation film is that the resistance with high dielectric constant value becomes material, such as being Al
2O
3Perhaps be HfO
2The polysilicon of described ground floor conductive film for mixing, its doping type can also can mix for the p type for the n type mixes.
Further, described first kind of doping type mixes for the n type, and described second kind of doping type mixes for the p type; Perhaps, described first kind of doping type mixes for the p type, and described second kind of doping type mixes for the n type.
The present invention obtains the gate dielectric layer of high-quality MOS transistor and the resistance-change memory layer of resistance-variable storing device through an atomic layer deposition technology; Under the prerequisite that does not increase extra processing step; Resistance-variable storing device and MOS transistor are integrated; Processing step is simple, and can compatible shallow ditch groove separation process or the ion of field oxide isolation technology and source, leakage inject or diffusion technology, it is integrated to be convenient to technology.
Description of drawings
Fig. 1 is a kind of sectional view of mos transistor structure of integrated resistance-variable storing device of conventional art.
Fig. 2 is the sectional view of an embodiment of the mos transistor structure of the disclosed integrated resistance-variable storing device of the present invention.
Fig. 3 to Figure 11 is the process chart of an embodiment of the manufacturing approach of the mos transistor structure of the disclosed integrated resistance-variable storing device of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation, in the drawings, explanation is for ease amplified or has been dwindled the thickness of layer with the zone, shown in size do not represent actual size.Although the actual size that reflects device that these figure can not entirely accurate, their zones that still has been complete reflection and form the mutual alignment between the structure, particularly form between the structure up and down and neighbouring relations.
Fig. 2 is an embodiment of the mos transistor structure of the disclosed integrated resistance-variable storing device of the present invention, and it is the sectional view along this device channel length direction.As shown in Figure 2, this device forms in the trap 20 of a Semiconductor substrate or doping usually, and the trap 20 of described Semiconductor substrate or doping is generally by the n type of low concentration or p type doping impurity mistake.The doping type of source region 21, drain region 22 and substrate or trap 20 is opposite.Source region 21 can directly perhaps be connected through a contact with outer electrode 31 as the source electrode of MOS transistor, and the grid 25 of MOS transistor can directly perhaps be connected through a contact with outer electrode 32.The gate dielectric layer 24 of MOS transistor exceeds grid and extends on the drain region 22; Wherein extend to the resistance-change memory layer that gate dielectric layer 24a on the drain region 22 partly forms resistance-variable storing device, resistance-change memory layer 24a and outer electrode 33 are directly or be connected through a contact.
The mos transistor structure of integrated resistance-variable storing device proposed by the invention can be through a lot of method manufacturings, the following stated narration be the embodiment of manufacturing approach of n type mos transistor structure of the integrated resistance-variable storing device of the disclosed a kind of structure as shown in Figure 2 of the present invention.Fig. 3-11 has described the operation of the part in the integrated circuit of being made up of the n type mos transistor structure of the integrated resistance-variable storing device of the disclosed structure as shown in Figure 2 of the present invention, is example with the silicon substrate.
If prepare the p type mos transistor structure of integrated resistance-variable storing device, only need n type doping type in following description the and the exchange of p type doping type be got final product.
Like Fig. 3, in the silicon substrate 201 of the light dope p type foreign ion that provides, form shallow trench isolation from (STI) structure or field oxide isolation structure, this technical process is that industry is known, and illustrates with sti structure 202 in embodiments of the present invention.Then, at surface of silicon growth one deck silicon oxide film 203.
Next; Deposit one deck photoresist 301 and mask, exposure, development define the source region of MOS transistor and the position in drain region on silicon oxide film 203; Etch away the silicon oxide film 203 that exposes again and expose substrate surface; In silicon substrate 201, form the n type source region 204 and n type drain region 205 of device then through ion implantation technology, as shown in Figure 4.
Next, divest photoresist 301 and etch away remaining silicon oxide film 203, then sample is put into atomic layer deposition equipment, adopt atomic layer deposition technology at substrate surface growth one deck HfO
2Gate dielectric layer 206, as shown in Figure 5.
Next, the polysilicon that first deposit one deck mixes on gate dielectric layer 206, its doping type can also can mix for the n type for the p type mixes.Deposit one deck photoresist 302 and mask, exposure, development form figure on polysilicon membrane again; The grid region of MOS transistor is protected with photoresist; Etch away the polysilicon membrane that exposes then; Remaining polysilicon membrane forms the grid 207 of MOS transistor, and grid 207 is on the substrate between source region 204 and the drain region 205, and is as shown in Figure 6.
Next; Divest photoresist 302 earlier, cover said grid 207 deposit one deck insulation films again, such as being silicon nitride; And then deposit one deck photoresist and mask, exposure, development form figure; Then etch away the silicon nitride film that exposes, the residual silicon nitride film forms the grid curb wall 208 of MOS transistor, divests behind the photoresist as shown in Figure 7.
Next; Deposit one deck photoresist and mask, exposure, development define the position in source region 204 on said structure; Etch away the gate dielectric layer part of 204 tops, source region that expose then; Wherein keep the resistance-change memory layer of the gate dielectric layer part of 205 tops, drain region, divest behind the photoresist as shown in Figure 8 as resistance-variable storing device.
Next; Cover the passivation layer of said structure deposit one deck insulation film 209 as device; Passivation layer 209 is such as being boron-phosphorosilicate glass; Deposit one deck photoresist 303 and mask, exposure, development define the position of contact hole on said passivation layer then, etch away the passivation layer 209 that exposes afterwards and form contact holes, and be as shown in Figure 9.
Next, divest photoresist 303, in the contact hole that said etching forms, form metal plug then, such as being tungsten plug.Be to strengthen the adhesion of tungsten metal, deposit one deck adhesion coating 210 in contact hole earlier usually such as being TiN, and then deposition tungsten metal 211, carries out after the chemico-mechanical polishing device shown in figure 10.
At last; Deposit layer of metal layer 212 on formed device architecture; Such as being aluminium, deposit one deck photoresist and mask, exposure, development form figure on metal level 212 then, etch away the metal level that exposes afterwards; Remaining metal level forms source electrode, gate electrode and drain electrode, divests behind the photoresist shown in figure 11.
As stated, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except like enclosed claim limited, the invention is not restricted at the instantiation described in the specification.
Claims (9)
1. the field-effect transistor structure of an integrated resistance-variable storing device comprises:
A Semiconductor substrate;
Field-effect transistor that on said Semiconductor substrate, forms and resistance-variable storing device;
It is characterized in that,
The gate dielectric layer of described field-effect transistor extends on the surface, drain region of described field-effect transistor;
Gate dielectric layer on the described surface, drain region that extends to field-effect transistor partly forms the resistance-change memory layer of said resistance-variable storing device.
2. the field-effect transistor structure of integrated resistance-variable storing device according to claim 1 is characterized in that, described Semiconductor substrate is silicon or is the silicon on the insulator.
3. the field-effect transistor structure of integrated resistance-variable storing device according to claim 1 is characterized in that, the gate dielectric layer of described field-effect transistor is that the resistance with high dielectric constant value becomes material.
4. the manufacturing approach of the field-effect transistor structure of an integrated resistance-variable storing device is characterized in that concrete steps comprise:
Form the ground floor insulation film at semiconductor substrate surface with first kind of doping type;
Deposit one deck photoresist on said ground floor insulation film, and mask, exposure, development define source region, the position, drain region of MOS transistor;
The said ground floor insulation film of the source region of the said MOS transistor of etching, position, drain region exposes Semiconductor substrate;
In said Semiconductor substrate, form source region and drain region through ion implantation technology or diffusion technology with second kind of doping type;
Divest photoresist;
Etch away remaining said ground floor insulation film;
Adopt atomic layer deposition technology at semiconductor substrate surface growth second layer insulation film;
Deposit forms the ground floor conductive film on said second layer insulation film;
Deposit one deck photoresist and photoetching form figure on said ground floor conductive film, and the grid region of MOS transistor is protected with photoresist;
Etch away the said ground floor conductive film that exposes, remaining said ground floor conductive film forms the grid of MOS transistor;
Divest photoresist;
Etch away the second layer insulation film of top, said source region and keep the second layer insulation film of top, said drain region, the second layer insulation film of top, said drain region forms the resistance-change memory layer of resistance-variable storing device.
5. the manufacturing approach of the field-effect transistor structure of integrated resistance-variable storing device according to claim 4 is characterized in that, described ground floor insulation film is a silica.
6. the manufacturing approach of the field-effect transistor structure of integrated resistance-variable storing device according to claim 4 is characterized in that, described second layer insulation film is that the resistance with high dielectric constant value becomes material.
7. the manufacturing approach of the field-effect transistor structure of integrated resistance-variable storing device according to claim 4 is characterized in that, the polysilicon of described ground floor conductive film for mixing, and its doping type can also can mix for the p type for the n type mixes.
8. the manufacturing approach of the field-effect transistor structure of integrated resistance-variable storing device according to claim 4 is characterized in that, described first kind of doping type mixes for the n type, and described second kind of doping type mixes for the p type.
9. the manufacturing approach of the field-effect transistor structure of integrated resistance-variable storing device according to claim 4 is characterized in that, described first kind of doping type mixes for the p type, and described second kind of doping type mixes for the n type.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012102065105A CN102709308A (en) | 2012-06-21 | 2012-06-21 | MOS (Metal Oxide Semiconductor) transistor structure integrated with resistive random access memory and manufacturing method of MOS transistor structure |
| US13/663,077 US9054303B2 (en) | 2012-06-21 | 2012-10-29 | Metal-oxide-semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM) and the manufacturing methods thereof |
| US14/702,228 US9431506B2 (en) | 2012-06-21 | 2015-05-01 | Metal-oxide-semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM) and the manufacturing methods thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012102065105A CN102709308A (en) | 2012-06-21 | 2012-06-21 | MOS (Metal Oxide Semiconductor) transistor structure integrated with resistive random access memory and manufacturing method of MOS transistor structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102709308A true CN102709308A (en) | 2012-10-03 |
Family
ID=46901959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012102065105A Pending CN102709308A (en) | 2012-06-21 | 2012-06-21 | MOS (Metal Oxide Semiconductor) transistor structure integrated with resistive random access memory and manufacturing method of MOS transistor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102709308A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103441135A (en) * | 2013-08-21 | 2013-12-11 | 北京大学 | 1T1R and 1R resistive random access memory integrated structure and implement method thereof |
| CN110620128A (en) * | 2019-08-29 | 2019-12-27 | 浙江省北大信息技术高等研究院 | Resistive random access memory device and writing method, erasing method and reading method thereof |
| CN112466902A (en) * | 2019-09-06 | 2021-03-09 | 爱思开海力士有限公司 | Nonvolatile memory device having resistance change memory layer |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5646438A (en) * | 1994-11-12 | 1997-07-08 | Deutsche Itt Industries Gmbh | Programmable semiconductor memory |
| CN101179095A (en) * | 2007-11-13 | 2008-05-14 | 北京大学 | Field-effect tranisistor realizing memory function and method of producing the same |
| CN102104110A (en) * | 2010-11-16 | 2011-06-22 | 复旦大学 | Resistance change memory with optimized resistance change characteristic and preparation method thereof |
| CN102185105A (en) * | 2011-04-22 | 2011-09-14 | 复旦大学 | Semiconductor memory structure and manufacturing method thereof |
| CN102222763A (en) * | 2011-06-03 | 2011-10-19 | 复旦大学 | RRAM (resistive random access memory) with electric-field enhancement layer and manufacturing method thereof |
-
2012
- 2012-06-21 CN CN2012102065105A patent/CN102709308A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5646438A (en) * | 1994-11-12 | 1997-07-08 | Deutsche Itt Industries Gmbh | Programmable semiconductor memory |
| CN101179095A (en) * | 2007-11-13 | 2008-05-14 | 北京大学 | Field-effect tranisistor realizing memory function and method of producing the same |
| CN102104110A (en) * | 2010-11-16 | 2011-06-22 | 复旦大学 | Resistance change memory with optimized resistance change characteristic and preparation method thereof |
| CN102185105A (en) * | 2011-04-22 | 2011-09-14 | 复旦大学 | Semiconductor memory structure and manufacturing method thereof |
| CN102222763A (en) * | 2011-06-03 | 2011-10-19 | 复旦大学 | RRAM (resistive random access memory) with electric-field enhancement layer and manufacturing method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103441135A (en) * | 2013-08-21 | 2013-12-11 | 北京大学 | 1T1R and 1R resistive random access memory integrated structure and implement method thereof |
| CN103441135B (en) * | 2013-08-21 | 2016-03-16 | 北京大学 | 1T1R and 1R resistance-variable storing device integrated morphology and its implementation |
| CN110620128A (en) * | 2019-08-29 | 2019-12-27 | 浙江省北大信息技术高等研究院 | Resistive random access memory device and writing method, erasing method and reading method thereof |
| CN112466902A (en) * | 2019-09-06 | 2021-03-09 | 爱思开海力士有限公司 | Nonvolatile memory device having resistance change memory layer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI695488B (en) | Non-volatile split gate memory cells with integrated high k metal control gates and method of making same | |
| US9425206B2 (en) | Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology | |
| US8334560B2 (en) | Reverse disturb immune asymmetrical sidewall floating gate devices | |
| CN103915384B (en) | Semiconductor structure and forming method thereof | |
| TWI566301B (en) | Integrated circuit and method for manufacturing the same | |
| CN103928402B (en) | The semiconductor structure of common grid and the forming method of correspondence | |
| KR102596378B1 (en) | Semiconductor device structure | |
| US20090236685A1 (en) | Embedded interconnects, and methods for forming same | |
| KR20090015861A (en) | Nonvolatile semiconductor memory and manufacturing method thereof | |
| US9147835B2 (en) | Tunnel transistor structure integrated with a resistance random access memory (RRAM) and a manufacturing method thereof | |
| US7875913B2 (en) | Transistor with contact over gate active area | |
| CN102709192A (en) | Manufacturing method of MOS (Metal Oxide Semiconductor) transistor structure integrated with resistive random access memory | |
| CN102709308A (en) | MOS (Metal Oxide Semiconductor) transistor structure integrated with resistive random access memory and manufacturing method of MOS transistor structure | |
| US8598004B2 (en) | Self aligned MOS structure with polysilicon contact | |
| US9431506B2 (en) | Metal-oxide-semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM) and the manufacturing methods thereof | |
| US8470702B2 (en) | Semiconductor device and method for forming the same | |
| US8129816B2 (en) | Semiconductor device and method of manufacturing the same | |
| KR20110001136A (en) | Method for manufacturing semiconductor device | |
| US20080001188A1 (en) | SOI devices and methods for fabricating the same | |
| US11444095B2 (en) | Semiconductor device with integrated memory devices and MOS devices and process of making the same | |
| US8097505B2 (en) | Method of forming isolation layer in semiconductor device | |
| TWI336939B (en) | Flash memory cell | |
| US9269583B1 (en) | Method for fabricating memory device | |
| US8415217B2 (en) | Patterning a gate stack of a non-volatile memory (NVM) with formation of a capacitor | |
| US8426263B2 (en) | Patterning a gate stack of a non-volatile memory (NVM) with formation of a metal-oxide-semiconductor field effect transistor (MOSFET) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20121003 |