CN102891137A - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- CN102891137A CN102891137A CN2011102192765A CN201110219276A CN102891137A CN 102891137 A CN102891137 A CN 102891137A CN 2011102192765 A CN2011102192765 A CN 2011102192765A CN 201110219276 A CN201110219276 A CN 201110219276A CN 102891137 A CN102891137 A CN 102891137A
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- CN
- China
- Prior art keywords
- packaging
- base plate
- semiconductor
- package part
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000004806 packaging method and process Methods 0.000 claims abstract description 48
- 230000004308 accommodation Effects 0.000 claims description 13
- 239000013078 crystal Substances 0.000 claims description 11
- 239000000084 colloidal system Substances 0.000 claims description 4
- 238000012856 packing Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
Abstract
A semiconductor package, comprising: a package substrate; a plurality of semiconductor chips stacked on the packaging substrate in a staggered manner, so that an accommodating space is formed between the packaging substrate and the stacked semiconductor chips; and a control chip which is combined on the packaging substrate in a flip-chip manner and is positioned in the accommodating space. The control chip is placed in the accommodating space, so that the thickness of the whole packaging piece is reduced, and the aim of thinning is fulfilled.
Description
Technical field
The present invention relates to a kind of semiconductor package part, espespecially a kind of semiconductor package part of tool control chip.
Background technology
Common multichip packaging structure is to adopt side-by-side (side-by-side), a plurality of chips being arranged side by side in the putting on the crystal face an of substrate, and the electric connection mode between the conducting wire is generally routing mode (wire bonding) on those chips and the substrate.Yet, because the area of this substrate can increase along with the increase of core number, so to be packaging cost too high and the encapsulating structure size is too large for the shortcoming of this side-by-side multichip packaging structure.
For addressing the above problem, in recent years by using rectilinear stacking method increasing the quantity of chip, and the mode of its storehouse is had nothing in common with each other according to the design of chip and routing processing procedure.For example: set flash chip (flash memory chip) or DRAM (Dynamic Random Access Memory) chip (Dynamic Random Access Memory in the electronic installation of memory card, DRAM) etc., the weld pad of this chip concentrates on one side, so its storehouse mode is step structure, so that routing and can reduce the area of putting memory chip.
Figure 1A and Figure 1B are United States Patent (USP) the 6th, 538, the semiconductor package part of the multi-chip stack of the memory card that discloses for No. 331, it is a plurality of semiconductor chip 11a of storehouse on a base plate for packaging 10,11b, and under the principle that does not hinder the routing operation, top semiconductor chip 11b is offset a preset distance and is located on the lower semiconductor chip 11a with stepped structure, one control chip (controller) 12 with a plurality of weld pads 120 is set on the semiconductor chip 11b of this top again, and making those semiconductor chips 11a by bonding wire 13, the weld pad 120 of 11b and this control chip 12 is electrically connected these base plate for packaging 10.
Yet, compared to side-by-side (side-by-side) multichip packaging structure, though aforesaid semiconductor package part can dwindle the usable floor area of base plate for packaging 10, the thickness of overall package volume is increased, thereby be difficult to meet the demand of thinning.
In addition, this control chip 12 is electrically connected this base plate for packaging 10 in the routing mode, make those weld pads 120 only can be located at this control chip 12 edges, thereby the quantity of minimizing electrical contact, cause the usefulness of this control chip 12 to promote, so that can't meet the now required high-effect demand of end product.
Therefore, how overcoming the variety of problems of existing semiconductor package part, is an important topic in fact.
Summary of the invention
In view of the shortcoming of above-mentioned prior art, main purpose of the present invention is to propose a kind of semiconductor package part, reducing the thickness of overall package part, and reaches the purpose of thinning.
Semiconductor package part proposed by the invention comprises: base plate for packaging; Sequentially be stacked over mutually a plurality of semiconductor chips on this base plate for packaging in the dislocation mode, make between the semiconductor chip of this base plate for packaging and this phase storehouse and form an accommodation space; And being placed in control chip on the base plate for packaging in this accommodation space, it is electrically connected this base plate for packaging to cover crystal type.
Aforesaid semiconductor package part of the present invention, on the base plate for packaging that control chip is placed in this accommodation space, to replace as in the prior art control chip being placed on the semiconductor chip of the top, so the present invention effectively reduces the thickness of overall package part, to meet the demand of thinning.
In addition, control chip of the present invention is electrically connected this base plate for packaging by covering crystal type, to replace the routing mode such as prior art, so those weld pads of control chip of the present invention can be laid in the surface of this control chip, and be not limited to the edge, to increase the quantity of electrical contact, the usefulness of this control chip is promoted, to meet the now required high-effect demand of end product.
In addition, according to the embodiment of aforesaid semiconductor package part of the present invention, the present invention also provides its concrete technology, and the details will be described later.
Description of drawings
Figure 1A is the generalized section of existing semiconductor package part;
Figure 1B looks schematic diagram on the part for existing semiconductor package part;
Fig. 2 is the generalized section of semiconductor package part of the present invention; And
Fig. 3 is the generalized section of another embodiment of semiconductor package part of the present invention.
The primary clustering symbol description
10,20 base plate for packaging
11a, 11b, 210a, 210b, 210a ', 210b ' semiconductor chip
12,22 control chips
120 weld pads
13,23 bonding wires
21 step structures
220 soldered balls
24 packing colloids
The S accommodation space.
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.
Notice, the appended graphic structure that illustrates of this specification, ratio, size etc., equal contents in order to cooperate specification to disclose only, understanding and reading for those skilled in the art, be not to limit the enforceable qualifications of the present invention, so technical essential meaning of tool not, the adjustment of the modification of any structure, the change of proportionate relationship or size, lower in the day that does not affect the effect that the present invention can produce and can reach all should still drop on disclosed technology contents and get in the scope that can contain.Simultaneously, quote in this specification as " on ", " below " reach terms such as " one ", also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, under without essence change technology contents, when also being considered as the enforceable category of the present invention.
Fig. 2 is the generalized section that illustrates semiconductor package part of the present invention.Described semiconductor package part is used for the electronic installation of tool memory card, and this semiconductor package part comprises: a base plate for packaging 20, a plurality of semiconductor chip 210a, 210b, a control chip 22 and packing colloid 24.
Described base plate for packaging 20 of a great variety can be designed on demand, and there is no particular restriction, and it is not the technical characterictic of this case, so repeat no more.
Described a plurality of semiconductor chip 210a, 210b sequentially are stacked into mutually a step structure 21 in the dislocation mode and are located on this base plate for packaging 20, make and form an accommodation space S between this base plate for packaging 20 and this step structure 21.This at least two semiconductor chip 210a, mutually to be electrically connected in the routing mode by bonding wire 23 between the 210b, in present embodiment, these whole semiconductor chip 210a, mutually be electrically connected in the routing mode by bonding wire 23 between the 210b, and the semiconductor chip 210a of the bottom also is electrically connected this base plate for packaging 20 by bonding wire 23.
In addition, aforesaid stacked semiconductor chip 210a, 210b, respectively this semiconductor chip 210a has the adhesion material between the 210b, and this is commonly used by the personage who has the knack of this technical field, does not illustrate so do not add in addition.Again, those semiconductor chips 210a, 210b has at least one memory chip.
In another embodiment, as shown in Figure 3, except the semiconductor chip 210a of this bottom, respectively this semiconductor chip 210b ' also can be electrically connected this base plate for packaging 20 in the routing mode individually.In addition, the semiconductor chip 210a ' of the bottom also can cover crystal type and is electrically connected to base plate for packaging 20.
On the base plate for packaging 20 that described control chip (controller Die) 22 is placed among this accommodation space S, and be electrically connected this base plate for packaging 20 by soldered ball 220 to cover crystal type.The electronic installation of and high power capacity high-effect because of tool more, control chip size in its packaging part is usually larger, so control chip 22 of the present invention is placed among this accommodation space S, not only can put the larger control chip of width or thickness 22, and the thickness of overall package part need not to consider the thickness of control chip 22 because of the height that only need consider step structure 21, with the thickness of effective reduction overall package part.
In addition, if the size of the control chip of putting is larger or usefulness is higher, then the quantity demand of the electrical contact of this control chip is more, so control chip 22 of the present invention is electrically connected this base plate for packaging 20 to cover crystal type, can make those soldered balls 220 (or weld pad of this control chip 22) arrange the surface that is laid in this control chip 22 with matrix form, and be not limited to the routing type chip, its electrical contact is distributed in the edge or is scattered in annular aspect, so can satisfy required electrical contact quantity to cover the crystal type electric connection, the usefulness of this control chip 22 is promoted.
In addition, the width of relevant controlling chip 22, length and thickness all can design on demand, as long as this control chip 22 is accommodated among this accommodation space S, there is no particular restriction.
Described packing colloid 24 is formed on this base plate for packaging 20, to coat those semiconductor chips 210a, 210b, bonding wire 23, soldered ball 220 and control chip 22.
So the invention provides a kind of semiconductor package part, comprising: base plate for packaging 20; A plurality of semiconductor chip 210a, 210b, it sequentially is stacked on this base plate for packaging 20 mutually in the dislocation mode, makes the semiconductor chip 210a of this base plate for packaging 20 and this phase storehouse, forms an accommodation space S between the 210b; And control chip 22, it is located on this base plate for packaging 20, and is arranged in this accommodation space S, and is electrically connected this base plate for packaging 20 to cover crystal type.
In sum, semiconductor package part of the present invention, mainly by control chip is accommodated between this base plate for packaging and this step structure in the formed accommodation space to cover crystal type, reaching the purpose of thinning packaging part, and this semiconductor package part has dynamical advantage concurrently.
Above-described embodiment is only in order to illustrative principle of the present invention and effect thereof, but not is used for restriction the present invention.Any those skilled in the art all can under spirit of the present invention and category, make amendment to above-described embodiment.So the scope of the present invention, should be listed such as claims.
Claims (8)
1. semiconductor package part, it comprises:
Base plate for packaging;
A plurality of semiconductor chips, it sequentially is stacked on this base plate for packaging mutually in the dislocation mode, makes between the semiconductor chip of this base plate for packaging and this phase storehouse and forms an accommodation space; And
Control chip, it is located on this base plate for packaging, and is arranged in this accommodation space, and is electrically connected this base plate for packaging to cover crystal type.
2. semiconductor package part according to claim 1 is characterized in that, mutually is electrically connected in the routing mode between at least two semiconductor chips in those semiconductor chips.
3. semiconductor package part according to claim 1 is characterized in that, the semiconductor chip of this bottom is electrically connected this base plate for packaging in the routing mode.
4. semiconductor package part according to claim 1 is characterized in that, the semiconductor chip of this bottom is electrically connected this base plate for packaging to cover crystal type.
5. semiconductor package part according to claim 1 is characterized in that, respectively this semiconductor chip on the semiconductor chip of this bottom is to be electrically connected this base plate for packaging in the routing mode individually.
6. semiconductor package part according to claim 1 is characterized in that, those semiconductor chips are each other with the step structure storehouse.
7. semiconductor package part according to claim 1 is characterized in that, those halfbody chips have at least one memory chip.
8. semiconductor package part according to claim 1 is characterized in that, this semiconductor package part also comprises packing colloid, and it is formed on this base plate for packaging to coat those semiconductor chips and control chip.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100125398A TWI455280B (en) | 2011-07-19 | 2011-07-19 | Semiconductor package structure |
| TW100125398 | 2011-07-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102891137A true CN102891137A (en) | 2013-01-23 |
Family
ID=47534599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011102192765A Pending CN102891137A (en) | 2011-07-19 | 2011-07-27 | Semiconductor package |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102891137A (en) |
| TW (1) | TWI455280B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109755182A (en) * | 2017-11-07 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | Chip stack package structure and forming method thereof |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019057575A (en) * | 2017-09-20 | 2019-04-11 | 東芝メモリ株式会社 | Method of manufacturing semiconductor device and semiconductor device |
| JP7293142B2 (en) | 2020-01-07 | 2023-06-19 | 東芝デバイス＆ストレージ株式会社 | semiconductor equipment |
| JP2023086480A (en) * | 2021-12-10 | 2023-06-22 | キオクシア株式会社 | Semiconductor device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091138A (en) * | 1998-02-27 | 2000-07-18 | Advanced Micro Devices, Inc. | Multi-chip packaging using bump technology |
| CN1516898A (en) * | 2001-06-07 | 2004-07-28 | ��ʽ���������Ƽ� | Semconductor device and mfg. method thereof |
| CN101232008A (en) * | 2007-01-03 | 2008-07-30 | 育霈科技股份有限公司 | Multi-chips package and method of forming the same |
| CN101236962A (en) * | 2007-01-31 | 2008-08-06 | 矽品精密工业股份有限公司 | Multi-chip stacking structure and its making method |
| CN101355040A (en) * | 2007-07-23 | 2009-01-28 | 矽品精密工业股份有限公司 | Stacking structure for multiple chips and manufacturing method thereof |
| CN101667545A (en) * | 2008-09-02 | 2010-03-10 | 矽品精密工业股份有限公司 | Multi-chip stacked structure and manufacturing method thereof |
| CN101826501A (en) * | 2009-03-06 | 2010-09-08 | 李同乐 | Leadless integrated circuit package having high density contacts |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI255492B (en) * | 2005-05-25 | 2006-05-21 | Siliconware Precision Industries Co Ltd | Multi-chip stack structure |
| TWI249772B (en) * | 2005-06-07 | 2006-02-21 | Siliconware Precision Industries Co Ltd | Semiconductor device for accommodating large chip, fabrication method thereof, and carrier used in the semiconductor device |
| TW201123320A (en) * | 2009-12-29 | 2011-07-01 | Powertech Technology Inc | Making method and device of outer lead type semiconductor package for reducing thickness of die pad |
-
2011
- 2011-07-19 TW TW100125398A patent/TWI455280B/en active
- 2011-07-27 CN CN2011102192765A patent/CN102891137A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091138A (en) * | 1998-02-27 | 2000-07-18 | Advanced Micro Devices, Inc. | Multi-chip packaging using bump technology |
| CN1516898A (en) * | 2001-06-07 | 2004-07-28 | ��ʽ���������Ƽ� | Semconductor device and mfg. method thereof |
| CN101232008A (en) * | 2007-01-03 | 2008-07-30 | 育霈科技股份有限公司 | Multi-chips package and method of forming the same |
| CN101236962A (en) * | 2007-01-31 | 2008-08-06 | 矽品精密工业股份有限公司 | Multi-chip stacking structure and its making method |
| CN101355040A (en) * | 2007-07-23 | 2009-01-28 | 矽品精密工业股份有限公司 | Stacking structure for multiple chips and manufacturing method thereof |
| CN101667545A (en) * | 2008-09-02 | 2010-03-10 | 矽品精密工业股份有限公司 | Multi-chip stacked structure and manufacturing method thereof |
| CN101826501A (en) * | 2009-03-06 | 2010-09-08 | 李同乐 | Leadless integrated circuit package having high density contacts |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109755182A (en) * | 2017-11-07 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | Chip stack package structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI455280B (en) | 2014-10-01 |
| TW201306224A (en) | 2013-02-01 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130123 |