CN103050468A - Flat multichip encapsulation piece of stamping framework with trapezoidal holes - Google Patents
Flat multichip encapsulation piece of stamping framework with trapezoidal holes Download PDFInfo
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- CN103050468A CN103050468A CN2012105434559A CN201210543455A CN103050468A CN 103050468 A CN103050468 A CN 103050468A CN 2012105434559 A CN2012105434559 A CN 2012105434559A CN 201210543455 A CN201210543455 A CN 201210543455A CN 103050468 A CN103050468 A CN 103050468A
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- chip
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- bonding wires
- bonding line
- die glue
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Abstract
The invention discloses a flat multichip encapsulation piece of a stamping framework with trapezoidal holes. The flat multichip encapsulation piece of the stamping framework with the trapezoidal holes mainly consists of lead frameworks, the trapezoidal holes, a lower chip, an upper chip, a lower chip adhesive, an upper chip adhesive, lower bonding wires, middle bonding wires, upper bonding wires and a plastic package body, wherein the trapezoidal holes are formed in the lead frameworks; the lead frameworks are adhered with the lower chip through the lower chip adhesive; the lower chip is adhered with the upper chip through the upper chip adhesive; the lower bonding wires are connected with the lead frameworks and the lower chip; the middle bonding wires are connected with the lower chip adhesive and the upper chip adhesive; the upper bonding wires are connected with the upper chip adhesive and the lead frameworks; and the plastic package body surrounds the lead frameworks, the lower chip, the upper chip, the lower chip adhesive, the upper chip adhesive, the lower bonding wires, the middle bonding wires and the upper bonding wires; particularly, the plastic package body fills the trapezoidal holes; and the lead frameworks, the lower chip, the upper chip, the lower bonding wires, the middle bonding wires and the upper bonding wires form a power source and a signal passage of a circuit. With the adoption of the trapezoidal holes for the flat multichip encapsulation piece of the stamping framework with the trapezoidal holes, relative to through holes and square concave grooves, the connection between the plastic package body and the lead frameworks is firmer and the delamination resistance effect is better.
Description
Technical field
The invention belongs to the integrated antenna package technical field, specifically a kind of flat Multi-chip packages of the ram frame with trapezoidal hole.
Background technology
The QFN(flat-four-side is without pin package) and the dual flat non-leaded encapsulation of DFN() encapsulation grows up, is applicable to high frequency, broadband, low noise, high heat conduction, small size in the in recent years generation (digital camera, mobile phone, PC, MP3) along with communication and portable small-sized digital electronic goods, the high-speed encapsulation that waits the middle small scale integrated circuit that electrically requires.We know that the QFN/DFN encapsulation has effectively utilized the encapsulated space of terminal pin, thereby have improved significantly packaging efficiency.But all face some difficult problems for selecting of framework in the manufacture process of present most of semiconductor packages QFN/DFN of manufacturer, available frame is two kinds of ram frame and etched frame, ram frame, its mould adopts the Mechanical Method worker to form, production efficiency is high, single product cost is lower, but the lead frame for some special graphs, can't select pressing processing, the framework that exposes such as carriers such as QFN/DFN/QFP, between carrier and the interior pin certain difference in height is arranged, form certain step, pressing is difficult to realization and controls this step well; The chemical etching framework, its die cost is low, and the construction cycle is short, can reach 2 week～1 month, and plastic packaging, cutting die can share during encapsulation, and input cost is low, but its production efficiency is low, and single product cost is higher.
In the plastic packaging operation of existing QFN/DFN technique, because the limitation of frame structure causes the QFN/DFN encapsulation to have the following disadvantages:
1. the adhesion of integrated circuit (IC) chip and carrier is bad, when be subjected to that external environment changes affect the time, can cause interiors of products to produce lamination defect, cause taking off of performance, even lost efficacy;
2. the adhesion of the carrier back side and plastic packaging material is bad, when the impact that is subjected to external environment, can cause product to produce defective (layering); Or expose on the carrier (Ji Dao) thicker flash is arranged.
Summary of the invention
For the defective of appeal conventional ram frame, etched frame, the invention provides a kind of flat Multi-chip packages of the ram frame with trapezoidal hole, the combination of its plastic-sealed body and lead frame is more firm, and anti-layered effect is better.。
Technical scheme of the present invention is: a kind of flat Multi-chip packages of the ram frame with trapezoidal hole mainly is comprised of lead frame, trapezoidal hole, lower chip, upper chip, lower bonding die glue, upper bonding die glue, lower bonding line, middle bonding line, upper bonding line and plastic-sealed body; Described lead frame has trapezoidal hole, described lead frame is by lower bonding die glue and lower die bonding, described lower chip is by upper bonding die glue and upper die bonding, described lower bonding line connecting lead wire framework and lower chip, described middle bonding line connects lower bonding die glue and upper bonding die glue, described upper bonding line connects upper bonding die glue and lead frame, described plastic-sealed body surrounds lead frame, lower chip, upper chip, lower bonding die glue, upper bonding die glue, lower bonding line, middle bonding line, upper bonding line, particularly plastic-sealed body is filled trapezoidal hole, lead frame, lower chip, upper chip, lower bonding line, middle bonding line, the power supply of upper bonding line forming circuit and signalling channel.
The present invention adopts a kind of novel framework, this framework adopts pressing to process, and adopt the method for punching press or boring to form trapezoidal hole at framework, thereby etch the effect that step plays anti-layering in order to substitute etching method at framework, plastic-sealed body is inserted in the trapezoidal hole in the integrated antenna package process, thereby between framework and plastic packaging material, form effectively anti-traction structure, with respect to through hole and square groove, trapezoidal hole makes the faying face between plastic-sealed body and framework larger, adhesion is better, greatly reduce the possibility of layering, significantly improve product reliability.Solved simultaneously and ground framework in the past and partly corrode the high defective of framework expense, greatly reduced cost.
Figure of description
Fig. 1 is the lead frame profile;
Fig. 2 is the multi-chip package profile.
Among the figure, lead frame 1, lower bonding die glue 2, lower chip 3, lower bonding line 4, trapezoidal hole 5, plastic-sealed body 6, upper bonding die glue 7, upper chip 8, middle bonding line 9, upper bonding line 10.
Embodiment
As shown in the figure, a kind of flat Multi-chip packages of the ram frame with trapezoidal hole mainly is comprised of lead frame 1, trapezoidal hole 5, lower chip 3, upper chip 8, lower bonding die glue 2, upper bonding die glue 7, lower bonding line 4, middle bonding line 9, upper bonding line 10 and plastic-sealed body 6; Described lead frame 1 has trapezoidal hole 5, described lead frame 1 is bonding by lower bonding die glue 2 and lower chip 3, described lower chip 3 is bonding by upper bonding die glue 7 and upper chip 8, described lower bonding line 4 connecting lead wire frameworks 1 and lower chip 3, described middle bonding line 9 connects lower bonding die glue 2 and upper bonding die glue 7, described upper bonding line 10 connects upper bonding die glue 7 and lead frame 1, described plastic-sealed body 6 surrounds lead frame 1, lower chip 3, upper chip 8, lower bonding die glue 2, upper bonding die glue 7, lower bonding line 4, middle bonding line 9, upper bonding line 10, particularly plastic-sealed body 6 is filled trapezoidal hole 5, lead frame 1, lower chip 3, upper chip 8, lower bonding line 4, middle bonding line 9, power supply and the signalling channel of upper bonding line 10 forming circuits.
The present invention also can be used for single-chip package.
The ram frame different from the past that the present invention adopts, after opening trapezoidal hole 5 with the method for punching or boring on the lead frame 1, plastic-sealed body 6 can be inserted trapezoidal hole 5 automatically during plastic packaging, between lead frame 1 and plastic-sealed body 6, form effectively anti-traction structure, greatly reduce the occurrence probability of packaging part layering situation, greatly improve product reliability, be better than the plastic packaging effect that tradition etches partially ram frame.
Claims (1)
1. the flat Multi-chip packages with the ram frame of trapezoidal hole is characterized in that: mainly be comprised of lead frame (1), trapezoidal hole (5), lower chip (3), upper chip (8), lower bonding die glue (2), upper bonding die glue (7), lower bonding line (4), middle bonding line (9), upper bonding line (10) and plastic-sealed body (6); Described lead frame (1) has trapezoidal hole (5), described lead frame (1) is bonding by lower bonding die glue (2) and lower chip (3), described lower chip (3) is bonding by upper bonding die glue (7) and upper chip (8), described lower bonding line (4) connecting lead wire framework (1) and lower chip (3), described middle bonding line (9) connects lower bonding die glue (2) and upper bonding die glue (7), bonding die glue (7) and lead frame (1) in described upper bonding line (10) connection, described plastic-sealed body (6) surrounds lead frame (1), lower chip (3), upper chip (8), lower bonding die glue (2), upper bonding die glue (7), lower bonding line (4), middle bonding line (9), upper bonding line (10), particularly plastic-sealed body (6) is filled trapezoidal hole (5), lead frame (1), lower chip (3), upper chip (8), lower bonding line (4), middle bonding line (9), power supply and the signalling channel of upper bonding line (10) forming circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105434559A CN103050468A (en) | 2012-12-17 | 2012-12-17 | Flat multichip encapsulation piece of stamping framework with trapezoidal holes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105434559A CN103050468A (en) | 2012-12-17 | 2012-12-17 | Flat multichip encapsulation piece of stamping framework with trapezoidal holes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103050468A true CN103050468A (en) | 2013-04-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012105434559A Pending CN103050468A (en) | 2012-12-17 | 2012-12-17 | Flat multichip encapsulation piece of stamping framework with trapezoidal holes |
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| Country | Link |
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| CN (1) | CN103050468A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050142694A1 (en) * | 2003-12-24 | 2005-06-30 | Super Talent Electronics Inc. | Stacking memory chips using flat lead-frame with breakaway insertion pins and pin-to-pin bridges |
| CN101075598A (en) * | 2007-04-29 | 2007-11-21 | 江苏长电科技股份有限公司 | Method for improving device lamination inside semiconductor plastic packer efficiently |
| CN101131938A (en) * | 2006-08-25 | 2008-02-27 | 先进半导体物料科技有限公司 | Ram lead frame and its manufacturing method |
| CN202259243U (en) * | 2011-06-13 | 2012-05-30 | 西安天胜电子有限公司 | Package with frame subjected to film coating after ball bonding |
-
2012
- 2012-12-17 CN CN2012105434559A patent/CN103050468A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050142694A1 (en) * | 2003-12-24 | 2005-06-30 | Super Talent Electronics Inc. | Stacking memory chips using flat lead-frame with breakaway insertion pins and pin-to-pin bridges |
| CN101131938A (en) * | 2006-08-25 | 2008-02-27 | 先进半导体物料科技有限公司 | Ram lead frame and its manufacturing method |
| CN101075598A (en) * | 2007-04-29 | 2007-11-21 | 江苏长电科技股份有限公司 | Method for improving device lamination inside semiconductor plastic packer efficiently |
| CN202259243U (en) * | 2011-06-13 | 2012-05-30 | 西安天胜电子有限公司 | Package with frame subjected to film coating after ball bonding |
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Application publication date: 20130417 |