CN103606540A - Frame-based small-distance multi-device SMT package and manufacturing process thereof - Google Patents
Frame-based small-distance multi-device SMT package and manufacturing process thereof Download PDFInfo
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- CN103606540A CN103606540A CN201310527917.2A CN201310527917A CN103606540A CN 103606540 A CN103606540 A CN 103606540A CN 201310527917 A CN201310527917 A CN 201310527917A CN 103606540 A CN103606540 A CN 103606540A
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- chip
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- lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Abstract
The invention discloses a frame-based small-distance multi-device SMT package and a manufacturing process thereof. The package mainly includes a lead-wire frame, an insulating adhesive, a chip, bonding wires, an inductor, a resistor, a capacitor, a packaged finished product and a plastic sealing body. The lead-wire frame is connected with the chip through the insulating adhesive. The lead-wire frame is connected with the inductor, the resistor, the capacitor and the packaged finished product through pins of the inductor, the resistor, the capacitor and the packaged finished product. The bonding wires connect the chip and the lead-wire frame directly. The plastic sealing body surrounds the lead-wire frame, the insulating adhesive, the chip, the bonding wires and the inductor. The inductor, the resistor, the capacitor and the packaged finished product are combined to form the whole of a circuit. The package is applied to SMT products with distances of 0.3mm to 0.5mm. The procedures of the manufacturing process are that tin pick-up of the pins of the inductor, the resistor, the capacitor and the packaged finished product, wafer thinning, wafer sawing, chip loading (chip bonding), press welding, plastic packaging, post curing, tinning, printing, product separating, testing, packaging and warehousing. The frame-based small-distance multi-device SMT package and the manufacturing process thereof are capable of reducing the size and weight effectively, improving reliability of the package, high in shock resistance capability and low in welding-spot defect rate.
Description
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Technical field
The invention belongs to integrated antenna package technical field, specifically a kind of little many devices of spacing SMT packaging part and manufacture craft thereof based on framework.
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Background technology
Electronic circuit surface installation technique (Surface Mount Technology, SMT), is called surface mount or surface mounting technology.It is a kind ofly will without pin or short leg surface-assembled components and parts, (be called for short SMC/SMD, Chinese title sheet components and parts) be arranged on printed circuit board (Printed Circuit Board, PCB) on surface or the surface of other substrate, by the methods such as Reflow Soldering or the immersed solder circuit load technology of welding assembly in addition.
Packaging density is high, electronic product volume is little, lightweight, and the volume and weight of surface mount elements only has 1/10 left and right of traditional inserting element, after generally adopting SMT, and electronic product volume-diminished 40% ~ 60%, weight saving 60% ~ 80%; Reliability is high, shock resistance is strong; Welding point defect rate is low; High frequency characteristics is good; Electromagnetism and radio frequency interference have been reduced; Easily be automated, enhance productivity; Reduce costs and reach 30% ~ 50%, save material, the energy, equipment, manpower, time etc.
QFN(flat-four-side is without pin package) and the dual flat non-leaded encapsulation of DFN() encapsulation grows up, is applicable to high frequency, broadband, low noise, high heat conduction, small size in the generation (digital camera, mobile phone, PC, MP3) along with communication and portable small-sized digital electronic goods in recent years, the high-speed encapsulation that waits the middle small scale integrated circuit electrically requiring.We know that QFN/DFN encapsulation has effectively utilized the encapsulated space of terminal pin, thereby have improved significantly packaging efficiency.
And along with electronic product function is increasingly more complete, the integrated circuit adopting (IC)
Without punctured element, particularly extensive, high integrated IC, has to adopt surface patch element.And along with product mass, the production automation, manufacturer will, with low-cost high yield, produce quality product to cater to customer demand and to strengthen the market competitiveness.Due to the various restrictions of technology, SMT technology is only for substrate class encapsulating products at present, I take charge of a kind of new production method of existing use, make shell frame products realize closely spaced many devices SMT encapsulation technology, on framework, connect inductance, resistance, electric capacity, on the basis of the devices such as encapsulation finished product, SMT product was owing to will avoiding short circuit in the past, spacing is all in 0.5mm ~ 1.0mm left and right, but the development along with electronic technology, it is less that electronic product more tends to volume, I/O is more, for terminal client provides the more electronic product of small size of more I/O, this patent is used closely spaced special process, can realize at the technical I/O of realization that guarantees circuit integrity more, many devices SMT packaging part that volume is less.
Summary of the invention
The problem existing with regard to above-mentioned prior art, the invention provides a kind of little many devices of spacing SMT packaging part and manufacture craft thereof based on framework, have effectively reduced volume, weight reduction also improves packaging part reliability, shock resistance is strong, the advantage that welding point defect rate is low.
Little many devices of spacing SMT packaging part based on framework is mainly by a lead frame, insulating cement, and chip, bonding line, inductance, resistance, electric capacity and encapsulation finished product, plastic-sealed body forms.Described lead frame is connected with chip by insulating cement, lead frame and inductance, resistance, electric capacity and encapsulation finished product pass through inductance, resistance, electric capacity is connected with the pin of encapsulation finished product, described bonding line directly connects chip and lead frame, plastic-sealed body has surrounded lead frame, insulating cement, chip, bonding line, inductance, inductance, resistance, electric capacity and encapsulation finished product have also formed the integral body of circuit, plastic-sealed body has played support and protective effect to chip and bonding line, chip, bonding line, inductance, resistance, electric capacity and encapsulation finished product, lead frame has formed power supply and the signalling channel of circuit.Described this packaging part is applied to spacing at the SMT of 0.3mm ~ 0.5mm product.
A kind of flow process of manufacture craft of little many devices of the spacing SMT packaging part based on framework: pin tin sticky → wafer attenuate → scribing of inductance, resistance, electric capacity and encapsulation finished product → upper core (bonding die) → pressure welding → plastic packaging → rear solidify → tin → printing → separation of products → check → packing → warehouse-in.
Accompanying drawing explanation
Fig. 1 lead frame profile;
Product profile after the bonding inductance of Fig. 2, resistance, electric capacity and encapsulation finished product;
Product profile after core on Fig. 3;
Product profile after Fig. 4 pressure welding;
Fig. 5 plastic packaged products profile;
Fig. 6 finished product profile;
Fig. 7 is that spacing is at the STM of 0.5mm ~ 1.0mm product;
Fig. 8 is that spacing is at the SMT of 0.3mm ~ 0.5mm product.
In figure, 1 is lead frame, and 2 is insulating cement, and 3 is chip, and 4 is bonding line, and 5 is inductance, resistance, electric capacity and encapsulation finished product, and 6 is plastic-sealed body.
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Embodiment
below in conjunction with accompanying drawing, the present invention is described further.
As shown in Figure 6, a kind of little many devices of spacing SMT packaging part based on framework is mainly by lead frame 1, insulating cement 2, and chip 3, bonding line 4, inductance, resistance, electric capacity and encapsulation finished product 5, plastic-sealed body 6 forms.Described lead frame 1 is connected with chip 3 by insulating cement 2, lead frame 1 and inductance, resistance, electric capacity and encapsulation finished product 5 pass through inductance, resistance, electric capacity is connected with the pin of encapsulation finished product 5, described bonding line 4 directly connects chip 3 and lead frame 1, plastic-sealed body 6 has surrounded lead frame 1, insulating cement 2, chip 3, bonding line 4, inductance, inductance, resistance, electric capacity and encapsulation finished product 5 have also formed the integral body of circuit, 6 pairs of chips 3 of plastic-sealed body and bonding line 4 have played support and protective effect, chip 3, bonding line 4, inductance, resistance, electric capacity and encapsulation finished product 5, lead frame 1 has formed power supply and the signalling channel of circuit.Described this packaging part is applied to spacing at the SMT of 0.3mm ~ 0.5mm product.
A kind of flow process of manufacture craft of little many devices of the spacing SMT packaging part based on framework: pin tin sticky → wafer attenuate → scribing of inductance, resistance, electric capacity and encapsulation finished product → upper core (bonding die) → pressure welding → plastic packaging → rear solidify → tin → printing → separation of products → check → packing → warehouse-in.
If Fig. 1 is to as shown in Fig. 8, a kind of key step of manufacture craft of little many devices of the spacing SMT packaging part based on framework is as follows:
1, select spacing at the SMT of 0.3mm ~ 0.5mm product;
2, inductance, resistance, electric capacity and the 5 pin tin sticky of encapsulation finished product, be connected with lead frame 1;
3, attenuate, scribing: thickness thinning 50 μ m～200 μ m, the above wafer of 150 μ m is with common Q FN scribing process, but thickness is at the following wafer of 150 μ m, uses double-pole scribing machine and technique thereof;
4, upper core (bonding die): adopt insulating cement 2 that chip 3 is connected with lead frame 1;
5, pressure welding: pressure welding is identical with conventional QFN/DFN technique;
6, plastic packaging, solidify afterwards, mill glue, tin, printing, separation of products, check, packing etc. are all identical with conventional QFN/DFN technique.
Claims (2)
1. little many devices of the spacing SMT packaging part based on framework, is characterized in that: mainly by lead frame (1), and insulating cement (2), chip (3), bonding line (4), inductance, resistance, electric capacity and encapsulation finished product (5), plastic-sealed body (6) forms, described lead frame (1) is connected with chip (3) by insulating cement (2), lead frame (1) and inductance, resistance, electric capacity and encapsulation finished product (5) pass through inductance, resistance, electric capacity is connected with the pin of encapsulation finished product (5), described bonding line (4) directly connects chip (3) and lead frame (1), plastic-sealed body (6) has surrounded lead frame (1), insulating cement (2), chip (3), bonding line (4), inductance, inductance, resistance, electric capacity and encapsulation finished product (5) have also formed the integral body of circuit, chip (3), bonding line (4), inductance, resistance, electric capacity and encapsulation finished product (5), lead frame (1) has formed power supply and the signalling channel of circuit, described this packaging part is applied to spacing at the SMT of 0.3mm ~ 0.5mm product.
2. a manufacture craft for little many devices of the spacing SMT packaging part based on framework, is characterized in that: it carries out according to following key step:
(1), select spacing at the SMT of 0.3mm ~ 0.5mm product;
(2), inductance, resistance, electric capacity and encapsulation finished product (5) pin tin sticky, be connected with lead frame (1);
(3), attenuate, scribing: thickness thinning 50 μ m～200 μ m, the above wafer of 150 μ m is with common Q FN scribing process, but thickness is at the following wafer of 150 μ m, uses double-pole scribing machine and technique thereof;
(4), upper core (bonding die): adopt insulating cement (2) that chip (3) is connected with lead frame (1);
(5), pressure welding: pressure welding is identical with conventional QFN/DFN technique;
(6), plastic packaging, solidify afterwards, mill glue, tin, printing, separation of products, check, packing etc. are all identical with conventional QFN/DFN technique.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310527917.2A CN103606540A (en) | 2013-10-31 | 2013-10-31 | Frame-based small-distance multi-device SMT package and manufacturing process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310527917.2A CN103606540A (en) | 2013-10-31 | 2013-10-31 | Frame-based small-distance multi-device SMT package and manufacturing process thereof |
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| Publication Number | Publication Date |
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| CN103606540A true CN103606540A (en) | 2014-02-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310527917.2A Pending CN103606540A (en) | 2013-10-31 | 2013-10-31 | Frame-based small-distance multi-device SMT package and manufacturing process thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050142694A1 (en) * | 2003-12-24 | 2005-06-30 | Super Talent Electronics Inc. | Stacking memory chips using flat lead-frame with breakaway insertion pins and pin-to-pin bridges |
| CN102231372A (en) * | 2011-06-30 | 2011-11-02 | 天水华天科技股份有限公司 | Multi-turn arranged carrier-free IC (Integrated Circuit) chip packaging component and manufacturing method thereof |
| CN103325756A (en) * | 2013-05-16 | 2013-09-25 | 华天科技（西安）有限公司 | Multi-device SMT flat packaging piece based on frame and manufacturing process of multi-device SMT flat packaging piece |
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2013
- 2013-10-31 CN CN201310527917.2A patent/CN103606540A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050142694A1 (en) * | 2003-12-24 | 2005-06-30 | Super Talent Electronics Inc. | Stacking memory chips using flat lead-frame with breakaway insertion pins and pin-to-pin bridges |
| CN102231372A (en) * | 2011-06-30 | 2011-11-02 | 天水华天科技股份有限公司 | Multi-turn arranged carrier-free IC (Integrated Circuit) chip packaging component and manufacturing method thereof |
| CN103325756A (en) * | 2013-05-16 | 2013-09-25 | 华天科技（西安）有限公司 | Multi-device SMT flat packaging piece based on frame and manufacturing process of multi-device SMT flat packaging piece |
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Application publication date: 20140226 |