CN103714008A - Method for memorizing data, memory controller and memorizing device of memory - Google Patents
Method for memorizing data, memory controller and memorizing device of memory Download PDFInfo
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- CN103714008A CN103714008A CN201210378097.0A CN201210378097A CN103714008A CN 103714008 A CN103714008 A CN 103714008A CN 201210378097 A CN201210378097 A CN 201210378097A CN 103714008 A CN103714008 A CN 103714008A
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Abstract
The invention discloses a method for memorizing data, a memory controller and a memorizing device of a memory. The method includes logically grouping physical erasing units of a rewritable non-volatile memory module into data areas and spare areas; selectively using first physical erasing units in the spare areas as first data searching units; selectively using second physical erasing units in the spare areas as second data searching units; writing write data received by a host system into the first data searching units; executing data reduction operation to migrate valid data in third physical erasing units of the data areas to the first data searching unit and associating the third physical erasing units with the spare areas. The method, the memory controller and the memorizing device have the advantage that the write operation efficiency can be effectively improved by the aid of the method.
Description
Technical field
The present invention relates to Memory Controller and the memory storage apparatus of a kind of date storage method for duplicative non-volatile memory module and use the method.
Background technology
Digital camera, mobile phone and MP3 are very rapid in growth over the years, and consumer is also increased rapidly to the demand of storage medium.Because duplicative nonvolatile memory (rewritable non-volatile memory) has that data are non-volatile, the characteristic such as little, the machinery-free structure of power saving, volume, read or write speed be fast, be suitable for most portable type electronic product, for example mobile computer.Solid state hard disc is exactly a kind of memory storage of flash memory module as storage medium of usining.Therefore, flash memory industry becomes a ring quite popular in electronic industry in recent years.
Flash memory module has a plurality of physical blocks (physical block), and each physical blocks has a plurality of physical pages (physical page), wherein must be according to the order of physical page (physical page) data writing in order during data writing in physical blocks (physical blocks).In addition the physical page that, has been written into data could be again for data writing after must first being erased.Particularly, physical blocks is the least unit of erasing, and physical page is the programming minimum unit of (also claiming to write).Therefore, in general, in the management of flash memory module, physical blocks is divided into data field (data area) and idle district (spare area) to I haven't seen you for ages.
The physical blocks of data field (being also called data physical blocks) is the data of storing in order to host system.Specifically, the memory management circuitry of flash memory device can map to the logical address of host computer system institute access the physical page of the physical blocks of data field.That is to say, in the management of flash memory module, the physical blocks of data field is to be regarded as the physical blocks (data that for example, host system writes) used.For example, memory management circuitry can be recorded the mapping relations between the physical page of physical blocks of logical address and data field by logical address-physical address mapping table, in order to access.
The physical blocks (being also called idle physical blocks) in idle district is the physical blocks of rotating in data field.Specifically, as mentioned above, the physical blocks of written data must be by just can be again for data writing after being erased, and the physical page of the physical blocks in idle district is to be designed to write more new data to replace the physical page of original mapping logic address.Base this, the physical blocks in idle district be sky or spendable physical blocks, i.e. no record data or be labeled as invalid data useless.
Specifically, when host computer system wish is upgraded the data in a logical address, the memory management circuitry of flash memory device is extracted an empty physical blocks from idle district can be as temporary transient physical blocks, new data is more write to a physical page of this temporary transient physical blocks, this logical address is remapped and so far writes the more physical page of new data, and the physical page that originally shone upon this logical address is labeled as invalid.When temporary transient physical blocks is fully written data, the empty physical blocks that this physical blocks as this temporary transient physical blocks can be associated to data field and another sky can be extracted as temporary transient physical blocks from idle district.Particularly, when the physical blocks in idle district exhausts soon, the memory management circuitry of flash memory device just must reclaim the physical blocks of storage invalid data from data field.Yet because host computer system is to write with logical address, and host computer system data writing often can not write according to the order of logical address during to logical address.Therefore, how from data field, moving rapidly valid data to vacate available physical blocks, is the target that these those skilled in the art endeavour.
Summary of the invention
The invention provides a kind of date storage method, Memory Controller and memory storage apparatus, it can promote the usefulness that data write running effectively.
The present invention's one exemplary embodiment proposes a kind of date storage method, for duplicative non-volatile memory module, this duplicative non-volatile memory module has a plurality of physics unit (entity erase unit) and each physics unit of erasing of erasing and has a plurality of physics programming units.Notebook data storage means comprises: these at least part of physics are erased to cellular logic and be grouped into data field and idle district; From erasing unit, the physics in idle district select the first physics to erase unit as the first data collection unit; And from erasing unit, the physics in idle district select the second physics to erase unit as the second data collection unit.Notebook data storage means also comprises: from host computer system, receive data writing; This data writing is write in the first physics of the first data collection unit is erased the physics programming unit of unit.Notebook data storage means also comprises that executing data arranges running, wherein this data preparation running comprises and from data field, selects the 3rd physics unit of erasing, the valid data that the 3rd physics is erased in unit are moved to physics (entity) programming (sequencing) unit of the unit of erasing as the second physics of cold the first data collection unit, and the 3rd physics unit of erasing is associated to this idle district.At this, the physics programming unit of the second data collection unit is written into the data that belong to a plurality of discontinuous logical addresses.
In one embodiment of this invention, above-mentioned date storage method, also comprise: when the first data collection unit is fully written data, the unit of erasing is associated to data field and reselects another physics from the physics in idle district is erased unit erase unit as the first data collection unit as the first physics of the first data collection unit.
In one embodiment of this invention, above-mentioned date storage method, also comprise: when the second data collection unit is fully written data, the unit of erasing is associated to data field and reselects another physics from the physics in idle district is erased unit erase unit as the second data collection unit as the 3rd physics of the second data collection unit.
In one embodiment of this invention, above-mentioned date storage method also comprises: whether the erase number of unit of the physics in the idle district of judgement is less than a predetermined threshold value, and wherein the step of this data preparation running of above-mentioned execution is to erase when the number of unit is less than predetermined threshold value and be performed at the physics in idle district.
In one embodiment of this invention, above-mentioned data preparation running also comprises: the erase effective data rate of unit of each physics of calculation data area, wherein the erase effective data rate of unit of above-mentioned the 3rd physics is less than the erase effective data rate of unit of other physics in data field.
In one embodiment of this invention, the physics programming unit of the first above-mentioned data collection unit is written into the data that belong to a plurality of discontinuous logical addresses.
The present invention's one exemplary embodiment proposes a kind of Memory Controller, be used for controlling a duplicative non-volatile memory module, this duplicative non-volatile memory module has a plurality of physics unit and each physics unit of erasing of erasing and has a plurality of physics programming units.This Memory Controller comprises host interface, memory interface and memory management circuitry.Host interface is in order to be coupled to host computer system.Memory interface is in order to be coupled to duplicative non-volatile memory module.Memory management circuitry is coupled to host interface and memory interface.Memory management circuitry is grouped into data field and idle district in order at least part of physics is erased to cellular logic, select the first physics unit of erasing to select the second physics to erase unit as the second data collection unit as the first data collection unit and from the physics in idle district is erased unit from the physics in idle district is erased unit.In addition, memory management circuitry is also in order to receive data writing from host computer system, and this data writing is write in the first physics of the first data collection unit is erased the physics programming unit of unit.Moreover, memory management circuitry also arranges running to select the 3rd physics unit of erasing from data field in order to executing data, the valid data that the 3rd physics is erased in unit are moved to the physics programming unit of the unit of erasing as the second physics of the second data collection unit, and the 3rd physics unit of erasing is associated to this idle district.At this, the physics programming unit of the second data collection unit is written into the data that belong to a plurality of discontinuous logical addresses.
In one embodiment of this invention, above-mentioned memory management circuitry also in order to, when the first data collection unit is fully written data, the unit of erasing is associated to data field and reselects another physics from the physics in idle district is erased unit erase unit as the first data collection unit as the first physics of the first data collection unit.
In one embodiment of this invention, above-mentioned memory management circuitry also in order to, when the second data collection unit is fully written data, the unit of erasing is associated to data field and reselects another physics from the physics in idle district is erased unit erase unit as the second data collection unit as the 3rd physics of the second data collection unit.
In one embodiment of this invention, above-mentioned memory management circuitry is also in order to judge whether the erase number of unit of the physics in this idle district is less than predetermined threshold value, and above-mentioned memory management circuitry is to erase and when the number of unit is less than predetermined threshold value, carry out above-mentioned data preparation running at the physics in idle district.
In one embodiment of this invention, in above-mentioned data preparation running, memory management circuitry is also in order to an erase effective data rate of unit of each physics of calculation data area, and wherein the erase effective data rate of unit of above-mentioned the 3rd physics is less than the erase effective data rate of unit of other physics in data field.
The present invention's one exemplary embodiment proposes a kind of memory storage apparatus, and it comprises connector, duplicative non-volatile memory module and Memory Controller.Connector is in order to be coupled to host computer system.Duplicative non-volatile memory module has a plurality of physics unit and each physics unit of erasing of erasing and has a plurality of physics programming units.Memory Controller is coupled to connector and duplicative non-volatile memory module.Memory Controller is grouped into data field and idle district in order at least part of physics is erased to cellular logic, select the first physics unit of erasing to select the second physics to erase unit as the second data collection unit as the first data collection unit and from the physics in idle district is erased unit from the physics in idle district is erased unit.In addition, Memory Controller is also in order to receive data writing from host computer system, and this data writing is write in the first physics of the first data collection unit is erased the physics programming unit of unit.Moreover, Memory Controller also arranges running to select the 3rd physics unit of erasing from data field in order to executing data, the valid data that the 3rd physics is erased in unit are moved to the physics programming unit of the unit of erasing as the second physics of the second data collection unit, and the 3rd physics unit of erasing is associated to this idle district.At this, the physics programming unit of the second data collection unit is written into the data that belong to a plurality of discontinuous logical addresses.
In one embodiment of this invention, above-mentioned Memory Controller also in order to, when the first data collection unit is fully written data, the unit of erasing is associated to data field and reselects another physics from the physics in idle district is erased unit erase unit as the first data collection unit as the first physics of the first data collection unit.
In one embodiment of this invention, above-mentioned Memory Controller also in order to, when the second data collection unit is fully written data, the unit of erasing is associated to data field and reselects another physics from the physics in idle district is erased unit erase unit as the second data collection unit as the 3rd physics of the second data collection unit.
In one embodiment of this invention, above-mentioned Memory Controller is also in order to judge whether the erase number of unit of the physics in this idle district is less than predetermined threshold value, and above-mentioned Memory Controller is to erase and when the number of unit is less than predetermined threshold value, carry out above-mentioned data preparation running at the physics in idle district.
In one embodiment of this invention, in above-mentioned data preparation running, Memory Controller is also in order to an erase effective data rate of unit of each physics of calculation data area, and wherein the erase effective data rate of unit of above-mentioned the 3rd physics is less than the erase effective data rate of unit of other physics in data field.
The date storage method of exemplary embodiment of the present invention, Memory Controller and memory storage apparatus can effectively shorten executing data and arrange the required time of running, promote thus the usefulness that data write running.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is host computer system and the memory storage apparatus illustrating according to an exemplary embodiment.
Fig. 2 is the schematic diagram of the computing machine, input/output device and the memory storage apparatus that illustrate according to an exemplary embodiment.
Fig. 3 is the host computer system that illustrates according to an exemplary embodiment and the schematic diagram of memory storage apparatus.
Fig. 4 is the summary calcspar that illustrates the memory storage apparatus shown in Fig. 1.
Fig. 5 is the summary calcspar of the Memory Controller that illustrates according to an exemplary embodiment.
Fig. 6 and Fig. 7 are the example schematic of the management duplicative non-volatile memory module that illustrates according to an exemplary embodiment.
Fig. 8 is the example that exemplary embodiment illustrates logical address-physics programming unit mapping table according to the present invention.
Fig. 9 ~ Figure 18 is that exemplary embodiment illustrates to carry out and writes running and an example of new logical addresses-physical address mapping table more according to the present invention.
Figure 19 is the schematic diagram of the physical address store status table that illustrates according to this exemplary embodiment.
Figure 20 ~ Figure 21 is that the executing data that one exemplary embodiment illustrates according to the present invention arranges the schematic diagram operating.
Figure 22 is the process flow diagram of the date storage method that exemplary embodiment illustrates according to the present invention.
Figure 23 is that the execution that the date storage method of the exemplary embodiment according to the present invention illustrates writes the process flow diagram operating with data preparation running.
[main element symbol description]
1000: host computer system
1100: computing machine
1102: microprocessor
1104: random access memory
1106: input/output device
1108: system bus
1110: data transmission interface
1202: mouse
1204: keyboard
1206: display
1252: printer
1256: Portable disk
1214: storage card
1216: solid state hard disc
1310: digital camera
1312:SD card
1314:MMC card
1316: memory stick
1318:CF card
1320: embedded memory storage
100: memory storage apparatus
102: connector
104: Memory Controller
106: duplicative non-volatile memory module
304 (0) ~ 304 (R): the physics unit of erasing
202: memory management circuitry
206: memory interface
252: memory buffer
254: electric power management circuit
256: bug check and correcting circuit
402: memory block
412: data field
414: idle district
404: system region
406: replace district
LSA (0) ~ LSA (L): sector
LBA (0) ~ LBA (H): logical address
PBA (0-1) ~ PBA (N-K): physics programming unit
800: logical address-physical address mapping table
802: logical address field
804: physical address field
1900: physical address store status table
1902: physical address index field
1904: state field
S2201, S2203, S2205, S2207, S2209, S2211, S2213, S2215, S2217: the step of date storage method
Embodiment
Generally speaking, memory storage apparatus (also claiming storage system) comprises duplicative non-volatile memory module and controller (also claiming control circuit).Conventionally memory storage apparatus is to use together with host computer system, so that host computer system can write to data memory storage apparatus or reading out data from memory storage apparatus.
Fig. 1 is host computer system and the memory storage apparatus illustrating according to an exemplary embodiment.
Please refer to Fig. 1, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1252 as Fig. 2.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Fig. 2, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memory storage apparatus 100 is to couple by data transmission interface 1110 and other elements of host computer system 1000.By microprocessor 1102, random access memory 1104, data can be write to memory storage apparatus 100 or reading out data from memory storage apparatus 100 with the running of input/output device 1106.For example, memory storage apparatus 100 can be the duplicative nonvolatile memory memory storage of Portable disk 1256, storage card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 as shown in Figure 2 etc.
Generally speaking, host computer system 1000 is for can coordinate to store substantially any system of data with memory storage apparatus 100.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, yet host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.For example, in host computer system, be digital camera (video camera) 1310 o'clock, duplicative nonvolatile memory memory storage is its SD card 1312 using, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded memory storage 1320 (as shown in Figure 3).Embedded memory storage 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is to be directly coupled on the substrate of host computer system.
Fig. 4 is the summary calcspar that illustrates the memory storage apparatus shown in Fig. 1.
Please refer to Fig. 4, memory storage apparatus 100 comprises connector 102, Memory Controller 104 and duplicative non-volatile memory module 106.
In this exemplary embodiment, connector 102 is to be compatible to advanced annex (Serial Advanced Technology Attachment, the SATA) standard of serial.Yet, it must be appreciated, the invention is not restricted to this, connector 102 can be also to meet parallel advanced annex (Parallel Advanced Technology Attachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, USB (universal serial bus) (Universal Serial Bus, USB) standard, secure digital (Secure Digital, SD) interface standard, a hypervelocity generation (Ultra High Speed-I, UHS-I) interface standard, hypervelocity two generations (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, multimedia storage card (Multi Media Card, MMC) interface standard, down enters formula multimedia storage card (Embedded Multimedia Card, eMMC) interface standard, general flash memory (Universal Flash Storage, UFS) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other applicable standards.
Duplicative non-volatile memory module 106 is to be coupled to Memory Controller 104, and the data that write in order to host system 1000.Duplicative non-volatile memory module 106 has the physics unit 304 (0) ~ 304 (R) of erasing.For example, the physics unit 304 (0) ~ 304 (R) of erasing can belong to same memory crystal grain (die) or belong to different memory crystal grain.Each physics unit of erasing has respectively a plurality of physics programming units, and belongs to the erase physics programming unit of unit of same physics and can be write independently and side by side be erased.For example, each physics unit of erasing is comprised of 128 physics programming units.Yet, it must be appreciated, the invention is not restricted to this, each physics erase unit also can by 64 physics programming units, 256 physics programming units or other arbitrarily a physics programming unit be formed.
In more detail, the physics unit of erasing is the least unit of erasing.That is, each physics memory cell of being erased in the lump that unit contains minimal amount of erasing.Physics programming unit is the minimum unit of programming.That is the minimum unit that, physics programming unit is data writing.Each physics programming unit generally includes data bit district and redundant digit district.Data bit district comprises a plurality of physics access address in order to store user's data, and redundant digit district for example, in order to the data (, controlling information and error correcting code) of storage system.In this exemplary embodiment, in the data bit district of each physics programming unit, can comprise 4 physics access addresses, and the size of a physics access address is 512 bytes (byte).Yet, in other exemplary embodiment, in data bit district, also can comprise the more or less physics access address of number, the present invention does not limit size and the number of physics access address.For example, in an exemplary embodiment, the physics unit of erasing is physical blocks, and physics programming unit is physical page or physical sector, but the present invention is not as limit.
In this exemplary embodiment, duplicative non-volatile memory module 106 is multistage memory cell (Multi Level Cell, MLC) NAND type flash memory module, in a memory cell, can store at least 2 bit data.Yet, the invention is not restricted to this, duplicative non-volatile memory module 106 also multistage memory cell (Trinary Level Cell, TLC) NAND type flash memory module, other flash memory module or other has the memory module of identical characteristics.
Fig. 5 is the summary calcspar of the Memory Controller that illustrates according to an exemplary embodiment.It must be appreciated, the structure of the Memory Controller shown in Fig. 5 is only an example, and the present invention is not as limit.
Please refer to Fig. 5, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.
In this exemplary embodiment, the steering order of memory management circuitry 202 is to carry out implementation with firmware pattern.For example, memory management circuitry 202 has microprocessor unit (not illustrating) and ROM (read-only memory) (not illustrating), and these a little steering orders are to be burned onto in this ROM (read-only memory).When memory storage apparatus 100 running, these a little steering orders can be carried out to carry out by microprocessor unit the runnings such as writing, read and erase of data.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can program code pattern for example be stored in, in the specific region (, being exclusively used in the system region of storage system data in memory module) of duplicative non-volatile memory module 106.In addition, memory management circuitry 202 has microprocessor unit (not illustrating), ROM (read-only memory) (not illustrating) and random access memory (not illustrating).Particularly, this ROM (read-only memory) has the code of driving, and when Memory Controller 104 is enabled, microprocessor unit can first be carried out this and drive code section that the steering order being stored in duplicative non-volatile memory module 106 is loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can turn round these a little steering orders to carry out the runnings such as writing, read and erase of data.
In addition,, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can a hardware pattern be carried out implementation.For example, memory management circuitry 202 comprises microcontroller, memory cell management circuit, storer write circuit, memory reading circuitry, storer erase circuit and data processing circuit.Erase circuit and data processing circuit of memory cell management circuit, storer write circuit, memory reading circuitry, storer is to be coupled to microcontroller.Wherein, memory cell management circuit is in order to manage the physics of duplicative non-volatile memory module 106 unit of erasing; Storer write circuit writes instruction data are write in duplicative non-volatile memory module 106 in order to duplicative non-volatile memory module 106 is assigned; Memory reading circuitry is in order to assign reading command with reading out data from duplicative non-volatile memory module 106 to duplicative non-volatile memory module 106; Storer is erased circuit in order to duplicative non-volatile memory module 106 is assigned to the instruction of erasing so that data are erased from duplicative non-volatile memory module 106; And data processing circuit wants to write to the data of duplicative non-volatile memory module 106 and the data that read from duplicative non-volatile memory module 106 in order to process.
In the present invention's one exemplary embodiment, Memory Controller 104 also comprises memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.
Electric power management circuit 254 is to be coupled to memory management circuitry 202 and in order to the power supply of control store memory storage 100.
Bug check and correcting circuit 256 be coupled to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives while writing instruction from host computer system 1000, bug check can produce corresponding bug check and correcting code (Error Checking and Correcting Code for the corresponding data that this writes instruction with correcting circuit 256, ECC Code), and memory management circuitry 202 corresponding these data that write instruction can be write in duplicative non-volatile memory module 106 with corresponding bug check and correcting code.Afterwards, when memory management circuitry 202 can read bug check corresponding to these data and correcting code during reading out data from duplicative non-volatile memory module 106 simultaneously, and bug check and correcting circuit 256 can be according to this bug check and correcting code to read data execution error inspection and correction programs.
Fig. 6 and Fig. 7 are the example schematic of the management duplicative non-volatile memory module that illustrates according to an exemplary embodiment.
It must be appreciated, when the physics of describing duplicative non-volatile memory module 106 at this is erased the running of unit, with words such as " extraction ", " exchange ", " grouping ", " rotating ", coming the operating physical unit of erasing is concept in logic.That is to say, the erase physical location of unit of the physics of duplicative non-volatile memory module is not changed, but in logic the physics of the duplicative non-volatile memory module unit of erasing is operated.
Please refer to Fig. 6, Memory Controller 104 (or memory management circuitry 202) unit 304 (0) ~ 304 (R) of the physics of duplicative non-volatile memory module 106 can being erased is logically grouped into memory block 402, system region 404 and replaces district 406.
The physics that belongs in logic memory block 402 unit of erasing is the data that write in order to host system 1000.That is to say, memory storage apparatus 100 can carry out the data that host system 1000 writes practically with the physics that is grouped into memory block 402 unit of erasing.In more detail, Memory Controller 104 (or memory management circuitry 202) can be grouped into memory block 402 data field 412 and idle district 414, wherein the physics of data field 412 unit (be also called data physics erase unit) of erasing is the physics of the having stored data unit of erasing, and the physics in idle district 414 unit (be also called idle physics erase unit) of erasing is in order to the physics in replacement data district 412 unit of erasing.Therefore, the physics in idle district 414 is erased unit for empty or the spendable physics unit of erasing, i.e. no record data or be labeled as invalid data useless.That is to say, the unit of erasing of the physics in idle district 414 has been performed the running of erasing, or the unit of erasing of the physics in idle district 414 is extracted for storing physics that data extract the before unit of erasing and can be performed the running of erasing.Therefore, the physics in idle district 414 is erased unit for the physics that can the be used unit of erasing.Specifically, when a physics is erased unit while being selected to store valid data from idle district 414, this physics unit of erasing can be associated to data field 412.And, erase operation for use is carried out in the physics that Memory Controller 104 (or memory management circuitry 202) can be all invalid data to the data that all physics programming units are stored in data field 412 unit of erasing, and the unit of erasing of the physics after erasing is associated to idle district 414, thus the physics data that unit can come host system 1000 to write with rotating of erasing.For example, in this exemplary embodiment, in memory storage apparatus 100 initialization when (being also called out card), all physics of memory block 402 unit of erasing all can be associated to idle district 411 (that is, the storage space of memory block 402 is all available).
The physics that belongs in logic system region 404 unit of erasing is in order to register system data, and wherein this system data comprises about the physics of the manufacturer of memory chip and model, memory chip unit number, each physics physics programming unit number of unit etc. of erasing of erasing.
Belonging in logic the physics replacing in district 406 unit of erasing is the alternate physical unit of erasing.For example, duplicative non-volatile memory module 106 can be reserved 4% the physics unit of erasing and uses as changing when dispatching from the factory.That is to say, when the physics in data field 412,414Yu system region, idle district 404 is erased unit damage, reserving physics in replacing district 406 unit of erasing is in order to the replacing damaged physics unit (that is, bad physics erase unit (bad block)) of erasing.Therefore, if replace, still have erase unit and when physics occurring erasing unit damage of normal physics in district 406, Memory Controller 104 can extract normal physics physics that unit the changes damage unit of erasing of erasing from replace district 406.If replace in district 406 without erase unit and when physics occurring erasing unit damage, Memory Controller 104 can be declared as write protection (write protect) state by whole memory storage apparatus 100 of normal physics, and data writing again.
Particularly, memory block 402, system region 404 and the physics that replaces district 406 erase the quantity of unit can be different according to different storer specifications.In addition, it must be appreciated, in the running of memory storage apparatus 100, physics is erased, and unit is associated to memory block 402, system region 404 can dynamically change with the grouping relation that replaces district 406.For example, the physics in memory block 402 erases that unit damages and the physics that is substituted district 406 is erased when unit replaces, and the physics that originally replaces district 406 unit of erasing can be associated to memory block 402.
Please refer to Fig. 7, as mentioned above, data field 412 and the physics in idle district 414 unit of erasing is the data that the mode of rotating comes host system 1000 to write.In this exemplary embodiment, Memory Controller 104 (or memory management circuitry 202) can give host computer system 1000 to carry out the access of data by configuration logic address LBA (0) ~ LBA (H).
Each logical address is comprised of several sectors (sector).For example, in this exemplary embodiment, each logical address is comprised of 4 sectors, and for example, sector LSA (0) ~ LSA (3) belongs to logical address LBA (0); Sector LSA (4) ~ LSA (7) belongs to logical address LBA (1); Sector LSA (8) ~ LSA (11) belongs to logical address LBA (2) ... etc.But the invention is not restricted to this, in another exemplary embodiment of the present invention, logical address is also formed or is comprised of 16 sectors by 8 sectors.
For example, Memory Controller 104 (or memory management circuitry 202) can service logic address-physical address mapping table record the mapping relations between logical address and physics programming unit.That is to say, when host computer system 1000 is wanted in sector access data, Memory Controller 104 (or memory management circuitry 202) can be confirmed the logical address under this sector, and carrys out access data in the physics programming unit shining upon in this logical address.
In this exemplary embodiment, before execution writes instruction, Memory Controller 104 (or memory management circuitry 202) can select a physics to erase unit as the first data collection unit from idle district 414, and data are write so far in the first data collection unit.Until erase unit while being fully written as the physics of the first data collection unit, Memory Controller 104 (or memory management circuitry 202) unit of this physics can being erased is associated to data field 412 and from idle district 414, selects another physics to erase unit as the first data collection unit again.
For example, Memory Controller 104 (or memory management circuitry 202) brings into use physics to erase unit 304 (0) while carrying out as the first data collection unit data that host system 1000 wants to write, no matter host computer system 1000 is to write that logical address, Memory Controller 104 (or memory management circuitry 202) can write to data the erase physics programming unit of unit 304 (0) of physics in order; And bring into use physics when Memory Controller 104 (or memory management circuitry 202), erase unit 304 (1) while carrying out as the first data collection unit data that host system 1000 wants to write, no matter host computer system 1000 is to write that logical address, Memory Controller 104 (or memory management circuitry 202) can write to data in order physics and erase in the physics programming unit of unit 304 (1).That is to say, when writing the data that host computer system 1000 wants to write, the physics programming unit that Memory Controller 104 (or memory management circuitry 202) can be used as the physics of the first data collection unit to erase in unit in order carrys out data writing, and the physics programming unit in this physics is erased unit just can select after being used up another physics without storage data unit of erasing to continue data writing in order as the first data collection unit again.In this exemplary embodiment, at Memory Controller 104 (or memory management circuitry 202), data are write to after physics programming unit, Memory Controller 104 (or memory management circuitry 202) can be more new logical addresses-physical address mapping table correctly to record the mapping relations of logical address and physics programming unit.
Fig. 8 is the example that exemplary embodiment illustrates logical address-physics programming unit mapping table according to the present invention.
Please refer to Fig. 8, logical address-physical address mapping table 800 comprises logical address field 802 and physical address (physical address) field 804.Numbering and the physical address field 804 of each logical address that logical address field 802 records configure record the physics programming unit of each logical address mapping.At memory storage apparatus 100 for completely newly and to be not used to store under the state of data, the physics unit 304 (0) ~ 304 (N) of erasing can be associated to idle district 414, and the field of the entity program element that corresponding each logical address of record is shone upon in logical address-physical address mapping table 800 can be marked as null value (for example, NULL).
Fig. 9 ~ Figure 18 is that exemplary embodiment illustrates to carry out and writes running and an example of new logical addresses-physical address mapping table more according to the present invention.For convenience of description, below by the storage space of the unit of erasing with a physics, be to be described by 5 physics examples that programming unit is configured to, but it must be appreciated, the invention is not restricted to this.
Please refer to Fig. 9, if when under the state shown in Fig. 8, host computer system 1000 wish storage data are to logical address LBA (1), Memory Controller 104 (or memory management circuitry 202) can select a physics (for example to erase unit from idle district 414, the physics unit 304 (0) of erasing) as the first data collection unit, and the data that host computer system 1000 is wanted to write write to the erase physics programming unit PBA (0-1) of unit 304 (0) of physics.After completing the writing of data, Memory Controller 104 (or memory management circuitry 202) can map to physics programming unit PBA (0-1) by logical address LBA (1) in logical address-physical address mapping table 800.
Please refer to Figure 10, if when under the state of Fig. 9, host computer system 1000 wish storage data are to logical address LBA (8), the data that Memory Controller 104 (or memory management circuitry 202) can be wanted host computer system 1000 to write write in physics programming unit PBA (0-2).And Memory Controller 104 (or memory management circuitry 202) can map to physics programming unit PBA (0-2) by logical address LBA (8) in logical address-physical address mapping table 800.
Please refer to Figure 11, if when under the state of Figure 10, host computer system 1000 wish storage data are to logical address LBA (3), the data that Memory Controller 104 (or memory management circuitry 202) can be wanted host computer system 1000 to write write in physics programming unit PBA (0-3).And Memory Controller 104 (or memory management circuitry 202) can map to physics programming unit PBA (0-3) by logical address LBA (3) in logical address-physical address mapping table 800.
Please refer to Figure 12, if when under the state of Figure 11, host computer system 1000 wish storage data are to logical address LBA (10), the data that Memory Controller 104 (or memory management circuitry 202) can be wanted host computer system 1000 to write write in physics programming unit PBA (0-4).Memory Controller 104 (or memory management circuitry 202) can map to physics programming unit PBA (0-4) by logical address LBA (10) in logical address-physical address mapping table 800.
Please refer to Figure 13, if when under the state of Figure 12, host computer system 1000 wish storage data are to logical address LBA (6), the data that Memory Controller 104 (or memory management circuitry 202) can be wanted host computer system 1000 to write write in physics programming unit PBA (0-5).Memory Controller 104 (or memory management circuitry 202) can map to physics programming unit PBA (0-5) by logical address LBA (6) in logical address-physical address mapping table 800.Particularly, as the physics of the first data collection unit unit 304 (0) of erasing, be fully written at present, therefore, Memory Controller 104 (or memory management circuitry 202) unit 304 (0) of physics can being erased is associated to data field 412.
Please refer to Figure 14, if when under the state of Figure 13, host computer system 1000 wish storage data are to logical address LBA (5), owing to being originally fully written and being associated to data field 412 as the physics of the first data collection unit unit 304 (0) of erasing, therefore, Memory Controller 104 (or memory management circuitry 202) can select another physics (for example to erase unit from idle district 414, the physics unit 304 (1) of erasing) as the first data collection unit and data that host computer system 1000 is wanted to write, writing to physics erases in the physics programming unit PBA (1-1) of unit 304 (1).Memory Controller 104 (or memory management circuitry 202) can map to physics programming unit PBA (1-1) by logical address LBA (5) in logical address-physical address mapping table 800.
As shown in Fig. 9-14, Memory Controller 104 (or memory management circuitry 202) can write as the first data collection unit the data that host computer system 1000 writes in order with the physics unit of erasing, and when this physics is erased unit while being fully written, Memory Controller 104 (or memory management circuitry 202) just can re-use another physics unit of erasing and continue data writing as the first data collection unit.That is to say, the data of wanting to be stored to a plurality of discrete logical addresses can be write to the first data collection unit in order, until this first data collection unit is fully written.
Please refer to Figure 15, if when under the state of Figure 14, host computer system 1000 is wanted data writing to logical address LBA (1), Memory Controller 104 (or memory management circuitry 202) host computer system 1000 can be wanted to write data write to physics and erase in the physics programming unit PBA (1-2) of unit 304 (1), and in logical address mapping table 800, logical address LBA (1) is mapped to physics programming unit PBA (1-2).The data that physics programming unit PBA (0-1) stores can become invalid data.
Please refer to Figure 16, if when under the state of Figure 15, host computer system 1000 wish storage data are to logical address LBA (10), the data that Memory Controller 104 (or memory management circuitry 202) can be wanted host computer system 1000 to write write in physics programming unit PBA (1-3).Memory Controller 104 (or memory management circuitry 202) can map to physics programming unit PBA (1-3) by logical address LBA (10) in logical address-physical address mapping table 800.
Please refer to Figure 17, if when under the state of Figure 16, host computer system 1000 is wanted data writing to logical address LBA (6), Memory Controller 104 (or memory management circuitry 202) host computer system 1000 can be wanted to write data write to physics and erase in the physics programming unit PBA (1-4) of unit 304 (1), and in logical address mapping table 800, logical address LBA (6) is mapped to physics programming unit PBA (1-4).The data that physics programming unit PBA (0-5) stores can become invalid data.
Please refer to Figure 18, if when under the state of Figure 17, host computer system 1000 is wanted data writing to logical address LBA (1), Memory Controller 104 (or memory management circuitry 202) host computer system 1000 can be wanted to write data write to physics and erase in the physics programming unit PBA (1-5) of unit 304 (1), and in logical address mapping table 800, logical address LBA (1) is mapped to physics programming unit PBA (1-5).The data that physics programming unit PBA (1-2) stores can become invalid data.Particularly, as the physics of the first data collection unit unit 304 (1) of erasing, be fully written at present, therefore, Memory Controller 104 (or memory management circuitry 202) unit 304 (1) of physics can being erased is associated to data field 412.
In this exemplary embodiment, in order to identify the physics programming unit of storage invalid data, Memory Controller 104 (or memory management circuitry 202) can be safeguarded physical address information table, and identifying thus the data that each physical address stores is valid data or invalid data.For example, Memory Controller 104 (or memory management circuitry 202) can carry out with physical address store status table the state of recording physical address.
Figure 19 is the schematic diagram of the physical address store status table that illustrates according to this exemplary embodiment, and wherein this physical address store status table is the storage dress state shown in corresponding Figure 18.
Please refer to Figure 19, physical address store status table 1900 comprises physical address index field 1902 and state field 1904, and physical address index field 1902 records the numbering of each physics programming unit and the state that state field 1904 records each corresponding physics programming unit.For example, when state field is marked as ' 0 ', represent that data that corresponding physics programming unit is stored are invalid data and state field while being marked as ' 1 ', represent that corresponding physics programming unit storage data are valid data, but the invention is not restricted to this.
Be worth mentioning, except the physical address store status table 1600 with above-mentioned, identify the state of physical address, in another exemplary embodiment of the present invention, physical address mapping table also can be used to identify the state of physical address.For example, physical address mapping table comprises physical address index field and logical address field, and wherein logical address field is in order to the logical address of the physics programming unit that records mapped physical address index field and record.And by comparison logical address mapping table and physical address mapping table, the data that each physics programming unit is stored are that valid data or invalid data just can be identified.
As mentioned above, when the first data collection unit is fully written, Memory Controller 104 (or memory management circuitry 202) can select another physics to erase unit as the first data collection unit from idle district 414.Yet, physics in idle district 414 unit of erasing is limited, therefore, when the physics in idle district 414 is erased the number of unit while being less than a predetermined threshold value, Memory Controller 104 (or memory management circuitry 202) can executing data arranges running, so that store the physics of the invalid data unit of erasing in data field, can be utilized again.For example, predetermined threshold value is to be set to 5.Yet, it must be appreciated, the invention is not restricted to this, predetermined threshold value also can be set to other suitable values.
In this exemplary embodiment, Memory Controller 104 (or memory management circuitry 202) can select a physics to erase unit as the second data collection unit from idle district 414, and when executing data arranges running, Memory Controller 104 (or memory management circuitry 202) can write to valid data as the physics of the second data collection unit and erase in unit.
Figure 20 ~ 21st, the executing data that one exemplary embodiment illustrates according to the present invention arranges the schematic diagram of running.
Please refer to Figure 20, Memory Controller 104 (or memory management circuitry 202) can from data field 412, select the physics target that unit (for example, physics erase unit 304 (0)) merges as executing data of erasing.
For example, Memory Controller 104 (or memory management circuitry 202) can record the erase effective data rate of unit of each physics.At this, the erase effective data rate of unit of physics is to define the erase physics programming unit of the valid data stored in unit of physics for this reason to account for the erase ratio of all physics programming units of unit of this physics.And Memory Controller 104 (or memory management circuitry 202) can be chosen in the unit of erasing of the physics in data field 412 with least significant data rate and arrange the target of running as executing data.For example, Memory Controller 104 (or memory management circuitry 202) can calculate the erase effective data rate of unit of each physics according to above-mentioned physical address store status table 1900.
Then, the valid data that Memory Controller 104 (or memory management circuitry 202) can be erased physics in unit 304 (0) are moved to the second data collection unit.For example, suppose that the erase physics programming unit PBA (0-2) of unit 304 (0) of physics stores and belongs to the erase physics programming unit PBA (0-3) of unit 304 (0) of the valid data of logical address LBA (8) and physics and store the valid data that belong to logical address LBA (3), and Memory Controller 104 (or memory management circuitry 202) selects physics to erase in the example of unit 304 (2) as the second data collection unit from idle district 414, the erase physics programming unit PBA (2-1) of unit 304 (2) of data-moving to the physics that Memory Controller 104 (or memory management circuitry 202) can be erased physics in the physics programming unit PBA (0-2) of unit 304 (0), logical address LBA (8) is remapped to physics programming unit PBA (2-1), the erase physics programming unit PBA (2-2) of unit 304 (2) of data-moving to the physics that physics is erased in the physics programming unit PBA (0-3) of unit 304 (0), logical address LBA (3) is remapped to physics programming unit PBA (2-2), and the physics unit 304 (0) of erasing is associated to idle district 414, complete thus data preparation running.At this, when valid data are moved to another physics programming unit from original physical programming unit, this original physical programming unit can be marked as the physics programming unit of storage invalid data.
Similarly, if when in memory storage apparatus 100 operation, data preparation running need be performed again, Memory Controller 104 (or memory management circuitry 202) can from data field 412, select again the physics unit of erasing as executing data, arrange the target of running, and the erase valid data of unit of this physics are continued to write at present as the physics of the second data collection unit unit of erasing.
Please refer to Figure 21, suppose that the erase physics programming unit PBA (1-1) of unit 304 (1) of the physics that arranges the target of running as executing data stores the valid data that belong to logical address LBA (5), physics programming unit PBA (1-3) stores the valid data that belong to logical address LBA (10), physics programming unit PBA (1-4) stores the valid data and the physics programming unit PBA (1-5) that belong to logical address LBA (6) and stores in the example of the valid data that belong to logical address LBA (1), the physics programming unit PBA (2-3) of Memory Controller 104 (or memory management circuitry 202) meeting using the data-moving in physics programming unit PBA (1-1) to the unit 304 (2) of erasing as the physics of the second data collection unit, logical address LBA (5) is remapped to physics programming unit PBA (2-3), by the erase physics programming unit PBA (2-4) of unit 304 (2) of data-moving to the physics in physics programming unit PBA (1-3), logical address LBA (10) is remapped to physics programming unit PBA (2-4), by the erase physics programming unit PBA (2-5) of unit 304 (2) of data-moving to the physics in physics programming unit PBA (1-4), and logical address LBA (6) is remapped to physics programming unit PBA (2-5).Due to being fully written of the unit 304 (2) of erasing as the physics of the second data collection unit, Memory Controller 104 (or memory management circuitry 202) unit 304 (2) of physics can being erased is associated to data field 412 and from idle district 414, selects the physics unit (for example, physics erase unit 304 (3)) of erasing to be used as the second data collection unit again.Then, data-moving to the physics in physics programming unit PBA (1-5) can the be erased physics programming unit PBA (3-1) of unit 304 (3) of Memory Controller 104 (or memory management circuitry 202), logical address LBA (1) is remapped to physics programming unit PBA (3-1), and the physics unit 304 (1) of erasing is associated to idle district 414, completes thus data preparation running.
As shown in Figure 20 ~ 21, Memory Controller 104 (or memory management circuitry 202) can write in order executing data as the second data collection unit and arranges the valid data that running is moved with the physics unit of erasing, and when this physics is erased unit while being fully written, Memory Controller 104 (or memory management circuitry 202) just can re-use another physics unit of erasing and continue data writing as the second data collection unit.That is to say, the valid data that belong to a plurality of discrete logical addresses can be moved in order to the second data collection unit, until this second data collection unit is fully written.
Figure 22 is the erase process flow diagram of unit of configures physical that the date storage method of the exemplary embodiment according to the present invention illustrates.
Please refer to Figure 22, in step S2201, Memory Controller 104 (or memory management circuitry 202) can be erased cellular logic by least part of physics and is grouped into data field 412 and idle district 414.
In step S2203, Memory Controller 104 (or memory management circuitry 202) can select a physics to erase unit (hereinafter referred to as the first physics unit of erasing) as the first data collection unit from the physics in idle district 414 is erased unit.
In step S2205, Memory Controller 104 (or memory management circuitry 202) can select a physics to erase unit (hereinafter referred to as the second physics unit of erasing) as the second data collection unit from the physics in idle district is erased unit.
Figure 23 is that the execution that the date storage method of the exemplary embodiment according to the present invention illustrates writes the process flow diagram operating with data preparation running.
In step S2207, Memory Controller 104 (or memory management circuitry 202) can receive data writing from host computer system 1000, and in step S2209, Memory Controller 104 (or memory management circuitry 202) can write to this data writing as the first physics of the first data collection unit and erase in unit.
In step S2211, Memory Controller 104 (or memory management circuitry 202) can judge the first physics unit of erasing whether be fully written.
If erase unit while not being fully written as the physics of the first data collection unit, the flow process of Figure 22 can finish.
If erase unit while being fully written as the physics of the first data collection unit, in step S2213, Memory Controller 104 (or memory management circuitry 202) unit of the first physics can being erased is associated to data field 412 and selects another physics to erase unit as the first data collection unit from the physics in idle district 414 is erased unit.
Afterwards, in step S2215, whether the erase number of unit of the physics that Memory Controller 104 (or memory management circuitry 202) can the idle district 414 of judgement is less than predetermined threshold value.
If the physics in idle district 414 is erased, the number of unit is non-while being less than predetermined threshold value, and the flow process of Figure 22 can finish.
When if the physics in idle district 414 is erased, the number of unit is less than predetermined threshold value, in step S2217, Memory Controller 104 (or memory management circuitry 202) can executing data arranges running to select the physics unit (hereinafter referred to as the 3rd physics unit of erasing) of erasing from data field, the valid data that the 3rd physics is erased in unit are moved to erasing in unit as the second physics of the second data collection unit, and the 3rd physics unit of erasing is associated to idle district.Afterwards, the flow process of Figure 22 can finish.
Particularly, in step S2217, Memory Controller 104 (or memory management circuitry 202) can judge the second physics unit of erasing whether be fully written, if and the second physics erases unit while being fully written, Memory Controller 104 (or memory management circuitry 202) can select another physics to erase unit as the second data collection unit from the physics in idle district 414 is erased unit.
In sum, the date storage method of exemplary embodiment of the present invention, Memory Controller and memory storage apparatus can configure the first data collection unit and write the data that host computer system writes and configure the second data collection unit and write executing data and arrange the valid data that running is moved.Particularly, the valid data of moving due to executing data arrangement running are not updated, therefore, by the memory mechanism of exemplary embodiment of the present invention, valid data can be concentrated on gradually a part of data and be erased in unit, and invalid data can be concentrated to gradually the data of another portion and erase in unit, thus can be when follow-up executing data arranges running, while erasing unit to obtain the data that can store new data, can effectively select physics that effective data rate the is lower unit of erasing to carry out data preparation running, shorten thus executing data and arrange the required time of running.
Although the present invention with embodiment openly as above; so it is not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention, when doing a little change and retouching, are as the criterion depending on appended claims institute confining spectrum therefore protection scope of the present invention is worked as.
Claims (15)
1. a date storage method, for a duplicative non-volatile memory module, this duplicative non-volatile memory module has a plurality of physics unit and each these physics unit of erasing of erasing and has a plurality of physics programming units, and this date storage method comprises:
These at least part of physics are erased to cellular logic and be grouped into a data field and an idle district;
From erasing unit, the physics in this idle district select one first physics to erase unit as one first data collection unit;
From erasing unit, the physics in this idle district select one second physics to erase unit as one second data collection unit;
From a host computer system, receive a data writing;
This data writing is write in this first physics of this first data collection unit is erased the physics programming unit of unit; And
Carry out a data preparation running, wherein this data preparation running comprises and from this data field, selects one the 3rd physics unit of erasing, the valid data that the 3rd physics is erased in unit are moved to the physics programming unit of the unit of erasing as this second physics of this second data collection unit, and the 3rd physics unit of erasing is associated to this idle district
Wherein the physics programming unit of this second data collection unit is written into the data that belong to a plurality of discontinuous logical addresses.
2. date storage method as claimed in claim 1, also comprises:
When this first data collection unit is fully written data, the unit of erasing is associated to this data field and from the physics in this idle district is erased unit, reselects another physics erase unit as this first data collection unit as this first physics of this first data collection unit; And
When this second data collection unit is fully written data, the unit of erasing is associated to this data field and from the physics in this idle district is erased unit, reselects another physics erase unit as this second data collection unit as this second physics of this second data collection unit.
3. date storage method as claimed in claim 1, also comprises:
Whether the erase number of unit of the physics that judges this idle district is less than a predetermined threshold value,
Wherein the step of this data preparation of above-mentioned execution running is to erase when the number of unit is less than this predetermined threshold value and be performed at the physics in this idle district.
4. date storage method as claimed in claim 1, this data preparation running also comprises:
Each these physics that calculates this data field effective data rate of unit of erasing,
Wherein the erase effective data rate of unit of the 3rd physics is less than the erase effective data rate of unit of other physics in this data field.
5. date storage method as claimed in claim 1, wherein the physics programming unit of this first data collection unit is written into the data that belong to a plurality of discontinuous logical addresses.
6. a Memory Controller, be used for controlling a duplicative non-volatile memory module, this duplicative non-volatile memory module has a plurality of physics unit and each these physics unit of erasing of erasing and has a plurality of physics programming units, and this Memory Controller comprises:
One host interface, in order to be coupled to a host computer system;
One memory interface, in order to be coupled to this duplicative non-volatile memory module; And
One memory management circuitry, is coupled to this host interface and this memory interface,
Wherein this memory management circuitry is grouped into a data field and an idle district in order to these at least part of physics are erased to cellular logic,
Wherein this memory management circuitry is also in order to select one first physics to erase unit as one first data collection unit from the physics in this idle district is erased unit,
Wherein this memory management circuitry is also in order to select one second physics to erase unit as one second data collection unit from the physics in this idle district is erased unit,
Wherein this memory management circuitry is also in order to receive a data writing from this host computer system, and this data writing is write in this first physics of this first data collection unit is erased the physics programming unit of unit,
Wherein this memory management circuitry is also in order to carry out a data preparation running to select one the 3rd physics unit of erasing from this data field, the valid data that the 3rd physics is erased in unit are moved to the physics programming unit of the unit of erasing as this second physics of this second data collection unit, and the 3rd physics unit of erasing is associated to this idle district
Wherein the physics programming unit of this second data collection unit is written into the data that belong to a plurality of discontinuous logical addresses.
7. Memory Controller as claimed in claim 6, wherein this memory management circuitry also in order to, when this first data collection unit is fully written data, the unit of erasing as this first physics of this first data collection unit is associated to this data field and from the physics in this idle district is erased unit, reselects another physics and erase unit as this first data collection unit
Wherein this memory management circuitry also in order to, when this second data collection unit is fully written data, the unit of erasing is associated to this data field and from the physics in this idle district is erased unit, reselects another physics erase unit as this second data collection unit as this second physics of this second data collection unit.
8. Memory Controller as claimed in claim 6, wherein this memory management circuitry is also in order to judge whether the erase number of unit of the physics in this idle district is less than a predetermined threshold value,
Wherein this memory management circuitry is to erase and when the number of unit is less than this predetermined threshold value, carry out above-mentioned data preparation running at the physics in this idle district.
9. Memory Controller as claimed in claim 6, wherein in this data preparation running, this memory management circuitry is also in order to calculate an erase effective data rate of unit of each these physics of this data field,
Wherein the erase effective data rate of unit of the 3rd physics is less than the erase effective data rate of unit of other physics in this data field.
10. Memory Controller as claimed in claim 6, wherein the physics programming unit of this first data collection unit is written into the data that belong to a plurality of discontinuous logical addresses.
11. 1 kinds of memory storage apparatus, comprising:
A connector, in order to be coupled to a host computer system;
One duplicative non-volatile memory module, has a plurality of physics unit and each these physics unit of erasing of erasing and has a plurality of physics programming units; And
One Memory Controller, is coupled to this connector and this duplicative non-volatile memory module,
Wherein this Memory Controller is grouped into a data field and an idle district in order to these at least part of physics are erased to cellular logic,
Wherein this Memory Controller is also in order to select one first physics to erase unit as one first data collection unit from the physics in this idle district is erased unit,
Wherein this Memory Controller is also in order to select one second physics to erase unit as one second data collection unit from the physics in this idle district is erased unit,
Wherein this Memory Controller is also in order to receive a data writing from this host computer system, and this data writing is write in this first physics of this first data collection unit is erased the physics programming unit of unit,
Wherein this Memory Controller is also in order to carry out a data preparation running to select one the 3rd physics unit of erasing from this data field, the valid data that the 3rd physics is erased in unit are moved to the physics programming unit of the unit of erasing as this second physics of this second data collection unit, and the 3rd physics unit of erasing is associated to this idle district
Wherein the physics programming unit of this second data collection unit is written into the data that belong to a plurality of discontinuous logical addresses.
12. memory storage apparatus as claimed in claim 11, wherein this Memory Controller also in order to, when this first data collection unit is fully written data, the unit of erasing as this first physics of this first data collection unit is associated to this data field and from the physics in this idle district is erased unit, reselects another physics and erase unit as this first data collection unit
Wherein this Memory Controller also in order to, when this second data collection unit is fully written data, the unit of erasing is associated to this data field and from the physics in this idle district is erased unit, reselects another physics erase unit as this second data collection unit as this second physics of this second data collection unit.
13. memory storage apparatus as claimed in claim 11, wherein this Memory Controller is also in order to judge whether the erase number of unit of the physics in this idle district is less than a predetermined threshold value,
Wherein this Memory Controller is to erase and when the number of unit is less than this predetermined threshold value, carry out above-mentioned data preparation running at the physics in this idle district.
14. memory storage apparatus as claimed in claim 11, wherein in this data preparation running, this Memory Controller is also in order to calculate an erase effective data rate of unit of each these physics of this data field,
Wherein the erase effective data rate of unit of the 3rd physics is less than the erase effective data rate of unit of other physics in this data field.
15. memory storage apparatus as claimed in claim 11, wherein the physics programming unit of this first data collection unit is written into the data that belong to a plurality of discontinuous logical addresses.
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