CN103871481B - Logic controller for non-volatility memorizer - Google Patents
Logic controller for non-volatility memorizer Download PDFInfo
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- CN103871481B CN103871481B CN201210535905.XA CN201210535905A CN103871481B CN 103871481 B CN103871481 B CN 103871481B CN 201210535905 A CN201210535905 A CN 201210535905A CN 103871481 B CN103871481 B CN 103871481B
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Abstract
The invention discloses a kind of logic controller for non-volatility memorizer, including: mode selection module, the logic module that powers on, data read-write module, automatic detection module and testing control module.Mode selection module is used for producing duty and mode of operation.The logic module that powers on completes to be sequentially loaded in User Status lower mold analog quantity one, automatically adjust and single-step debug under test mode.Testing control module completes the manual test of the analog quantity two under test mode including current/voltage, and is outputed test result by test output terminal mouth.Automatic detection module is for automatically comparing the carrying out of the data of storage array and detect.Data read-write module can control high pressure generation module during writing and complete the read-write operation of data.Data exchange is carried out by debugging bus between non-volatility memorizer and external module.The present invention can realize being automatically brought into operation and testing of non-volatility memorizer, the connection of energy simplified system.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of for non-volatility memorizer (NVM)
Logic controller.
Background technology
As it is shown in figure 1, be the structural representation of existing non-volatility memorizer, the structure of existing non-volatility memorizer
Including NVM main part 101.
User logic signal selects module 102 to realize the read-write to described NVM by NVM, and write operation is complicated, needs
User as requested, controls a series of write control signal in a certain order, and operation is complicated and easily makes mistakes.
If needing to carry out the test of full chip, user also needs to increase an extra test module 103, tests mould
Block 103 and NVM main body 101 is two modules that chip is separate, needs individually design and the connection of complexity,
Structure is complex and high cost.The input of test module 103 receives Test input signal, the output of test module 103
End is connected respectively to NVM main part 101 and NVM and selects module 102 to realize the test to NVM main part 101；
The outfan of test module 103 is also respectively connected to analog quantity and adjusts (TRIM) selection module 104, it is achieved to outside
Module such as voltage calibration (Voltage Regulator) module 105, voltage detecting (Voltage Detector) mould
Block 106 and the test of clock oscillation (Oscillator) module 107.
Power on operation process is complicated, needs user given zone from memorizer i.e. NVM main part 101 to read phase
The analog quantity adjusted value (Trimming data) answered, and analog quantity when sequential manual as requested completes to power on
The loading of Trimming data and adjustment, just can make system stability under normal mode of operation.Wherein, analog quantity
Including: the frequency of clock oscillation module 107, the voltage of voltage detection module 106, the electricity of voltage calibration module 105
Pressure.Trimming data in existing non-volatility memorizer needs the value that user is safeguarded, operation complexity；Non-wave
The complex interfaces of the property sent out memorizer, NVM main part 101 is examined with external module such as voltage calibration module 105, voltage
The line of survey module 106 and clock oscillation module 107 etc. is many and easily makes mistakes.
Summary of the invention
The technical problem to be solved is to provide a kind of logic controller for non-volatility memorizer, can be real
Show being automatically brought into operation and testing of non-volatility memorizer, the connection of energy simplified system.
For solving above-mentioned technical problem, the present invention provides a kind of logic controller for non-volatility memorizer, non-waves
The property sent out memorizer includes storage array, test interface module, high pressure generation module, analog quantity test module and logic
Controller, this logic controller includes: mode selection module, the logic module that powers on, data read-write module, automatically examine
Survey module and testing control module.
Described mode selection module is for producing duty and the mode of operation of described non-volatility memorizer, described work
User Status and test mode is included as state；Described mode of operation includes power on operation pattern, read operation pattern, writes
Operator scheme, test pattern and autosensing mode；Described mode selection module is by user logic signal and test interface
The Test input signal co-controlling that module produces.
The described logic module mode of operation according to described non-volatility memorizer that powers on, completes under described User Status
The given zone of the special storage analog quantity one from described non-volatility memorizer is sequentially loaded into described analog quantity one
Described analog quantity one is also automatically adjusted by (Trimming data), and complete under described test mode from
The given zone of described non-volatility memorizer is sequentially loaded into described analog quantity and automatically adjusts described analog quantity one in the lump
Whole and carry out described analog quantity one loading and adjust during single-step debug, make described non-volatility memorizer upper
The work of energy normal table after electricity.
Described testing control module, according to the mode of operation of described non-volatility memorizer, controls described non-volatile holographic storage
The described analog quantity test module of device, the hands of the analog quantity two completed under described test mode including current/voltage
Dynamic test, and outputed test result by test output terminal mouth, described analog quantity two includes two parts, and Part I is only
Needing to adjust in test mode and test, Part II is described analog quantity one, and described analog quantity one needs in test
Need when adjusting and power under pattern to be loaded into.
Described automatic detection module can detect the data message of the described storage array of described non-volatility memorizer, produces
The address of the described non-volatility memorizer that different configurations are lower and control signal, carry out oneself of data of described storage array
Move and compare and detect, and testing result is returned.
Described data read-write module, according to the mode of operation of described non-volatility memorizer, produces described non-volatile holographic storage
The address of device also controls the described high pressure generation module of described non-volatility memorizer, completes described non-volatility memorizer
The read-write operation of data.
Data exchange is carried out by debugging bus between described non-volatility memorizer and external module.
Further improve and be, described in the logic module that powers on include:
Oscillation frequency clock adjusting module, for adjusting the frequency of clock oscillation module, described oscillation frequency clock adjusts
By debugging bus transfer frequency between module and described clock oscillation module.
Relatively current adjusting module, for adjusting the comparison electric current of described non-volatility memorizer.
Calibration voltage adjusting module, for adjusting the calibration voltage of voltage calibration module, described calibration voltage adjusting module
And by debugging bus transfer calibration voltage between described voltage calibration module.
Electric charge pump adjusting module, is used for adjusting charge pump voltage.
Further improving is that described automatic detection module includes:
Relatively configuration module, is used for configuring manner of comparison and comparing data.
Relatively address generating module, for producing address and the control signal of described non-volatility memorizer.
Detection module, for the data of described storage array are automatically compared and detect, and output detections result,
The most described testing result is for controlling the described address comparing address generating module and the generation of control signal.
Further improving is that described data read-write module includes:
Read/write address generation module, for producing the read/write address of described storage array.
Read control module and write control module, is respectively used to produce the control signal of reading and writing operation and control described high pressure
Generation module.
Further improving is that described testing control module, by configuring the depositor in described logic controller, completes
The manual test of the analog quantity two including current/voltage under test mode, and by described non-volatility memorizer
Test output terminal mouth output result.
Further improve and be, described in the logic module analog quantity one that is loaded and that adjust that powers on include: clock oscillation mould
The frequency of block, the comparison electric current of described non-volatility memorizer, the voltage of voltage calibration module, the voltage of electric charge pump.
Further improving is that described external module includes clock oscillation module, voltage calibration module, voltage detecting mould
Block.
Further improving and be, the signal of described debugging bus includes outside Slow Clock, beginning flag signal and two-way
Data signal.
There is advantages that
1, power on operation process is simplified.User need not the Trimming data i.e. analog quantity safeguarded when powering on
One, non-volatility memorizer can be automatically performed the loading of Trimming data when powering on and the adjustment of analog quantity, make be
System is operated in the duty of normal table.User has only to complete to check result output signal afterwards at power on operation
(Trdy), determine that power on operation is the most successful.
2, the write operation process of data is simplified.User has only to send write order, and waits write operation output letter
Number (Busy) release, logic controller just can automatically control high pressure generation module under write operation pattern and complete to write action.
3, when user need not to safeguard and powers on, the value of Trimming data, simplifies connecing of non-volatility memorizer
Mouthful and simplify the connection of system.
4, provide powerful test function, the test of full chip and the automatic detection of data can be completed.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the structural representation of existing non-volatility memorizer；
Fig. 2 is the structural representation of embodiment of the present invention non-volatility memorizer；
Fig. 3 A is the structural representation of the logic module that powers on of embodiment of the present invention non-volatility memorizer；
Fig. 3 B is the structural representation of the automatic detection module of embodiment of the present invention non-volatility memorizer；
Fig. 3 C is the structural representation of the data read-write module of embodiment of the present invention non-volatility memorizer；
Fig. 4 is the connection diagram of embodiment of the present invention non-volatility memorizer and external module；
Fig. 5 is the sequential chart of the debugging bus of the embodiment of the present invention.
Detailed description of the invention
As in figure 2 it is shown, be the structural representation of embodiment of the present invention non-volatility memorizer 1, the embodiment of the present invention is non-
Volatile storage 1 includes that storage array 2, test interface module 6, high pressure generation module 4, analog quantity test module
3 and logic controller 5, also include row decoding, column decoding and data cache module.Described logic controller 5 wraps
Include: mode selection module 7, the logic module that powers on 8, data read-write module 10, automatic detection module 9 and test control
Molding block 11.
Described mode selection module 7 is for producing duty and the mode of operation of described non-volatility memorizer 1, institute
State duty and include User Status and test mode；Described mode of operation include power on operation pattern, read operation pattern,
Write operation pattern, test pattern and autosensing mode；Described mode selection module 7 is by user logic signal and test
The Test input signal co-controlling that interface module 6 produces.
The described logic module 8 mode of operation according to described non-volatility memorizer 1 that powers on, completes at described user's shape
State lower mold analog quantity one is sequentially loaded into by the given zone of described non-volatility memorizer 1, is automatically adjusted, and completes in institute
State test mode lower mold analog quantity one to be sequentially loaded into by the given zone of described non-volatility memorizer 1, automatically adjust and carried out
The loading of analog quantity one and the single-step debug during adjusting, make the described non-volatility memorizer 1 after the power-up can be normal
Stable work.The described logic module 8 that powers on analog quantity one that is loaded and that adjust includes: clock oscillation module 24
Frequency, the comparison electric current of described non-volatility memorizer 1, the voltage of electric charge pump, the electricity of voltage calibration module 22
Pressure.The given zone of described non-volatility memorizer 1 be described storage array 2 be specifically designed to described in storage the logic that powers on
The loaded memory area with the analog quantity one adjusted of module 8.
As shown in Figure 3A, it is the structural representation of the logic module that powers on of embodiment of the present invention non-volatility memorizer,
The described logic module 8 that powers on includes:
Clock oscillation (OSC) frequency regulation block 12, for adjusting the frequency of clock oscillation module 24, described clock
By debugging bus (TMBUS) transmission frequency between frequency of oscillation adjusting module 12 and described clock oscillation module 24.
Relatively current adjusting module 13, for adjusting the comparison electric current of described non-volatility memorizer 1, described comparison is electric
Stream adjusting module 13 produces address and the control signal of described storage array 2, reads from described storage array 2 afterwards
The described corrected value comparing electric current.
Calibration voltage adjusting module 14, for adjusting the calibration voltage of voltage calibration module 22, described calibration voltage is adjusted
By debugging bus transfer calibration voltage between mould preparation block 14 and described voltage calibration module 22.
Electric charge pump adjusting module 15, for adjusting the charge pump voltage of non-volatility memorizer, described electric charge pump adjusts mould
Block 15 produces address and the control signal of described storage array 2, reads described electric charge from described storage array 2 afterwards
The corrected value of pump voltage.
The described logic module 8 that powers on proceeds by work after receiving power on operation enable, and power on operation is defeated after terminating
Go out signal Trdy.
Described testing control module 11, according to the mode of operation of described non-volatility memorizer 1, controls described non-volatile
Property memorizer 1 described analog quantity test module 3, complete the mould including current/voltage under described test mode
The manual test of analog quantity two, and outputed test result by test output (TP) port；Described analog quantity two includes two
Part, Part I only needs to adjust in test mode and test, and Part II is described analog quantity one, described mould
Analog quantity one needs to need when adjusting in test mode and power on to be loaded into.In the embodiment of the present invention, described testing and control mould
Block 11, by configuring the depositor in described logic controller 5, completes under test mode including current/voltage
The manual test of analog quantity two, and export result by the test output terminal mouth of described non-volatility memorizer 1.
Described automatic detection module 9 can detect the data message of the described storage array 2 of described non-volatility memorizer 1,
The address of the described non-volatility memorizer 1 under generation difference configuration and control signal, carry out described storage array 2
Automatically the comparing and detect of data, and testing result is returned.As described in Fig. 3 B, it is that the embodiment of the present invention is non-volatile
The structural representation of the automatic detection module 9 of property memorizer；Described automatic detection module 9 enables at autosensing mode
Start working under the control of signal, including:
Relatively configuration module 16, is used for configuring manner of comparison and comparing data.
Relatively address generating module 17, for producing address and the control signal of described non-volatility memorizer 1.
Detection module 18, for automatically comparing the data of described storage array 2 and detect.Examine after detecting successfully
Surveying module 18 can output detections result；The most described detection module 18 produce when comparison error compare stopping signal arriving
The described generation comparing address generating module 17, halt address and control signal.
Described data read-write module 10, according to the mode of operation of described non-volatility memorizer 1, produces described non-volatile
The address of property memorizer 1 also controls the described high pressure generation module 4 of described non-volatility memorizer 1, completes described non-
The read-write operation of volatile storage 1 data.As shown in Figure 3 C, it is embodiment of the present invention non-volatility memorizer
The structural representation of data read-write module；Described data read-write module 10 enables signal or write operation enable in read operation
Start working under the control of signal, including:
Read/write address generation module 19, for producing the read/write address of described storage array 2.
Read control module 20 and write control module 21, is respectively used to produce the control signal of reading and writing operation and control institute
State high pressure generation module 4.
As shown in Figure 4, it is the connection diagram of embodiment of the present invention non-volatility memorizer and external module.Described non-
Data exchange is carried out by debugging bus between volatile storage 1 and external module.Described external module includes clock
Oscillation module 24, voltage calibration module 22, voltage detection module 23.
As it is shown in figure 5, the sequential chart of the debugging bus of the embodiment of the present invention, when described debugging bus includes that outside is at a slow speed
Clock (SCK), beginning flag signal (SRST) and bi-direction data signal (SDIO).In test mode by read-write
The mode of depositor completes the adjustment of external module analog quantity, and external logic was deposited non-volatile by the response cycle simultaneously
The command response of reservoir.
The duty of described non-volatility memorizer 1 is controlled by external control signal, and its duty can be divided into
Following test mode and User Status two kinds.
Test mode:
In test mode, test input can control the work of described non-volatility memorizer 1 by test interface module 6
Pattern；When being in test mode, non-volatility memorizer 1 can be at above-mentioned all working pattern i.e. power on operation
Pattern, read operation pattern, write operation pattern, test pattern and autosensing mode, and testing procedure can be carried out list
Step is tried.Meanwhile, logic controller 5 provides a status register to show the result of each testing procedure.
Power on operation pattern: the frequency of clock oscillation module 24, the reference of described non-volatility memorizer 1 can be completed
Being automatically loaded and adjusting of the analog quantitys such as electric current i.e. compares electric current, the voltage of voltage calibration module 22, and pass through logic
What the status register of controller 5 indicated each analog quantity adjusts result automatically.
Read operation pattern: the continuous reading of data can be realized, the interval reading data can be set simultaneously, it is simple to debugging institute
State the reading data speed of non-volatility memorizer 1.
Write operation pattern: can control described non-volatility memorizer 1 and carry out erasable and programming control signal is the most permissible
Adjusting the time of operation with high pressure, the result of write operation can be shown by result output signal Busy.
Test pattern: this pattern provides under test mode, manually regulates a kind of method of analog current magnitude of voltage.Logical
Cross the mode of read-write logic controller 5 internal register, complete the calibration of modules analog quantity, and by TP end
Mouth measures.Adjusted calibration value i.e. analog quantity adjusted value (Trimming data) can be write storage array 2
Specific region, in order to the loading of Trimming data under other patterns.
Autosensing mode: can complete under various configurations, quickly reading and to coming from of non-volatility memorizer 1 data
Dynamic testing result, testing result can be read by the status register of logic controller 5.This autosensing mode comprises
The row of storage array 2 compares, arrange and compare and diagonal such as compares at the multiple manner of comparison.
User Status:
Now user logic signal controls the mode of operation of described non-volatility memorizer 1.Under User Status, non-wave
The property sent out memorizer 1 can be operated under power on operation pattern and reading and writing operator scheme.Under power on operation pattern, described
Logic controller 5 can be automatically performed being automatically loaded and adjusting of analog quantity when powering on, and makes chip be in the work of normal table
Making state, user only needs to wait for the corresponding time and observes power on operation result output signal Trdy.At write operation mould
Under formula, logic controller 5 can automatically generate signal and control high pressure generation module 4, and by result output signal Busy
The result of instruction write operation；Under read data pattern, the continuous reading of data can be realized.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improves, this
Also should be regarded as protection scope of the present invention a bit.
Claims (8)
1. the logic controller for non-volatility memorizer, it is characterised in that: non-volatility memorizer includes
Storage array, test interface module, high pressure generation module, analog quantity test module and logic controller, this logic
Controller includes: mode selection module, the logic module that powers on, data read-write module, automatic detection module and test control
Molding block；
Described mode selection module is for producing duty and the mode of operation of described non-volatility memorizer, described work
User Status and test mode is included as state；Described mode of operation includes power on operation pattern, read operation pattern, writes
Operator scheme, test pattern and autosensing mode；Described mode selection module is by user logic signal and test interface
The Test input signal co-controlling that module produces；
The described logic module mode of operation according to described non-volatility memorizer that powers on, completes under described User Status
The given zone of the special storage analog quantity one from described non-volatility memorizer is sequentially loaded into described analog quantity in the lump
Described analog quantity one is automatically adjusted, and completes under described test mode from described non-volatility memorizer
Given zone is sequentially loaded into described analog quantity and is automatically adjusted described analog quantity one in the lump and carries out described analog quantity one
Loading and single-step debug during adjusting, make the described non-volatility memorizer after the power-up can the work of normal table
Make；
Described testing control module, according to the mode of operation of described non-volatility memorizer, controls described non-volatile holographic storage
The described analog quantity test module of device, the hands of the analog quantity two completed under described test mode including current/voltage
Dynamic test, and outputed test result by test output terminal mouth, described analog quantity two includes two parts, and Part I is only
Needing to adjust in test mode and test, Part II is described analog quantity one, and described analog quantity one needs in test
Need when adjusting and power under pattern to be loaded into；
Described automatic detection module can detect the data message of the described storage array of described non-volatility memorizer, produces
The address of the described non-volatility memorizer that different configurations are lower and control signal, carry out oneself of data of described storage array
Move and compare and detect, and testing result is returned；
Described data read-write module, according to the mode of operation of described non-volatility memorizer, produces described non-volatile holographic storage
The address of device also controls the described high pressure generation module of described non-volatility memorizer, completes described non-volatility memorizer
The read-write operation of data；
Data exchange is carried out by debugging bus between described non-volatility memorizer and external module.
2. the logic controller for non-volatility memorizer as claimed in claim 1, it is characterised in that described
The logic module that powers on includes:
Oscillation frequency clock adjusting module, for adjusting the frequency of clock oscillation module, described oscillation frequency clock adjusts
By debugging bus transfer frequency between module and described clock oscillation module；
Relatively current adjusting module, for adjusting the comparison electric current of described non-volatility memorizer；
Calibration voltage adjusting module, for adjusting the calibration voltage of voltage calibration module, described calibration voltage adjusting module
And by debugging bus transfer calibration voltage between described voltage calibration module；
Electric charge pump adjusting module, is used for adjusting charge pump voltage.
3. the logic controller for non-volatility memorizer as claimed in claim 1, it is characterised in that described
Automatic detection module includes:
Relatively configuration module, is used for configuring manner of comparison and comparing data；
Relatively address generating module, for producing address and the control signal of described non-volatility memorizer；
Detection module, for the data of described storage array are automatically compared and detect, and output detections result,
The most described testing result is for controlling the described address comparing address generating module and the generation of control signal.
4. the logic controller for non-volatility memorizer as claimed in claim 1, it is characterised in that described
Data read-write module includes:
Read/write address generation module, for producing the read/write address of described storage array；
Read control module and write control module, is respectively used to produce the control signal of reading and writing operation and control described high pressure
Generation module.
5. the logic controller for non-volatility memorizer as claimed in claim 1, it is characterised in that: described
Testing control module, by configuring the depositor in described logic controller, completes to include that current/voltage exists under test mode
The manual test of interior analog quantity two, and export result by the test output terminal mouth of described non-volatility memorizer.
6. the logic controller for non-volatility memorizer as claimed in claim 1, it is characterised in that: described
The logic module that powers on analog quantity one that is loaded and that adjust includes: the frequency of clock oscillation module, described non-volatile deposits
The comparison electric current of reservoir, the voltage of voltage calibration module, the voltage of electric charge pump.
7. the logic controller for non-volatility memorizer as claimed in claim 1, it is characterised in that: described
External module includes clock oscillation module, voltage calibration module, voltage detection module.
8. the logic controller for non-volatility memorizer as claimed in claim 1, it is characterised in that: described
The signal of debugging bus includes outside Slow Clock, beginning flag signal and bi-direction data signal.
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| CN201210535905.XA CN103871481B (en) | 2012-12-12 | 2012-12-12 | Logic controller for non-volatility memorizer |
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| CN201210535905.XA CN103871481B (en) | 2012-12-12 | 2012-12-12 | Logic controller for non-volatility memorizer |
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| CN103871481B true CN103871481B (en) | 2016-11-02 |
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| CN111028880B (en) * | 2019-12-19 | 2021-10-29 | 上海贝岭股份有限公司 | Reference current generating circuit and memory chip |
| CN111696617B (en) * | 2020-05-28 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Nonvolatile memory reading speed test circuit and test method |
| CN116935939A (en) * | 2023-09-15 | 2023-10-24 | 合肥康芯威存储技术有限公司 | Memory verification method, device and medium based on development board |
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| US6363008B1 (en) * | 2000-02-17 | 2002-03-26 | Multi Level Memory Technology | Multi-bit-cell non-volatile memory with maximized data capacity |
| CN1833293A (en) * | 2003-06-10 | 2006-09-13 | 微米技术有限公司 | Method and apparatus for measuring current as in sensing a memory cell |
| CN101763901A (en) * | 2008-12-23 | 2010-06-30 | 上海芯豪微电子有限公司 | On-wafer self-test and self-repair method |
| CN102354537A (en) * | 2011-07-06 | 2012-02-15 | 华中科技大学 | Method and system for testing chip of phase change memory |
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2012
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6363008B1 (en) * | 2000-02-17 | 2002-03-26 | Multi Level Memory Technology | Multi-bit-cell non-volatile memory with maximized data capacity |
| CN1833293A (en) * | 2003-06-10 | 2006-09-13 | 微米技术有限公司 | Method and apparatus for measuring current as in sensing a memory cell |
| CN101763901A (en) * | 2008-12-23 | 2010-06-30 | 上海芯豪微电子有限公司 | On-wafer self-test and self-repair method |
| CN102354537A (en) * | 2011-07-06 | 2012-02-15 | 华中科技大学 | Method and system for testing chip of phase change memory |
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