CN104320207B - Vector signal analysis device and method - Google Patents
Vector signal analysis device and method Download PDFInfo
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Abstract
The invention provides a vector signal analysis device. The vector signal analysis device is characterized in that an ADC (analog to digital converter) module performs A/D quantification on a received intermediate frequency signal, an I/Q (in-phase/quadrature) convertor performs I/Q conversion on a digital signal output by the ADC module so as to obtain base band I/Q data, an integer extraction module receives an I/Q signal output by the I/Q convertor, and extracts the I/Q signal after down conversion by integral multiples, a decimal fraction extraction module converts data velocity of I/Q data output by the integer extraction module into code element velocity which is an integral multiple of the data velocity, and further can perform decimal fraction multiple data velocity extraction conversion on an I/Q data file, and a vector demodulation analysis module performs subsequent vector demodulation analysis on I/Q data output by the decimal fraction extraction module. The vector signal analysis device can perform the flexible and complete vector demodulation analysis on digital modulation signals, uses the fixed velocity to perform A/D sampling, performs the I/Q conversion and integral multiple sampling rate conversion in a programmable device, and reduces design difficulty of A/D sampling of an existing vector signal analyzer and programmable hardware.
Description
Technical field
The present invention relates to technical field of measurement and test, particularly to a kind of Vector Signal Analysis device, further relate to a kind of vector letter
Number analysis method.
Background technology
Digital modulation signals have the advantages that information capacity is big, anti-interference and good confidentiality, in satellite communication, broadcast electricity
It is widely used depending in the communication systems such as, communication countermeasure.Code element information to digital modulation signals and modulation quality are carried out accurately
Measurement is the important prerequisite of digital communication system application, and VSA can achieve symbol recovery and modulation quality measurement,
And the test of the other parameters such as power, frequency, provide test to ensure for digital communication system.
After completing the frequency-conversion processing of signal, VSA needs programmable hardware device and the cooperation of software in machine
Complete more modulation form and the vector demodulation analysis of different chip rate digital modulation signals.Existing Vector Signal Analysis
Instrument completes I/Q conversion, the conversion of decimal sampling rate, the even process such as vector demodulation, Programming Design in programmable hardware device
Complexity is high；And software in machine cannot be carried out the recovering and analysis of non-integral multiple chip rate I/Q data file, software flexibility
And poor universality.
As shown in figure 1, existing Vector Signal Analysis implementation method typically has two kinds：
One is to carry out A/D conversion using variable high sampling rate, and sampling rate is the integral multiple of chip rate, becomes through I/Q
Change, after integral multiple filtering extraction, carry out vector demodulation analysis.The method requires the integral multiple that sampling clock is chip rate, right
The precision of sampling clock generator and area requirement are very high, realize relatively difficult；
Two is to carry out A/D conversion using fixed sample rate, carries out I/Q conversion, at little several times extraction in programming device
Reason obtains the I/Q data of integral multiple chip rate, carries out vector demodulation analysis in follow-up hardware or software module.
In the first implementation method above-mentioned, the data that VSA software in machine obtains is the knot after vector demodulation
Really, the time-frequency domain information of original sampling data is dropped, and data message utilization rate is not high, leads to interpretation of result angle not complete
Face；Additionally, implemented extremely difficult using variable high sampling rate A/D.
In second implementation method, little several times extract and process in programming device, and programming complexity is high；And the machine of staying is soft
Part lacks decimal sampling rate mapping function, only enables the demodulation analysis of integral multiple sample rate I/Q data it is impossible to recovering and analysis
The I/Q data of the non-integral multiple chip rate that other systems preserve, the software compatibility is poor, big using limitation.
Content of the invention
For solving the disadvantages mentioned above of existing Vector Signal Analysis implementation method, the present invention proposes a kind of Vector Signal Analysis
Device and method.
The technical scheme is that and be achieved in that：
A kind of Vector Signal Analysis device, including：ADC, I/Q changer, integer decimation module, decimal abstraction module
Demodulate analysis module with vector；
ADC carries out A/D quantization to the intermediate-freuqncy signal receiving；
I/Q changer carries out I/Q conversion and obtains baseband I/Q data to the digital signal that ADC exports；
Integer decimation module receives the i/q signal of I/Q changer output, carries out integral multiple to the i/q signal after down coversion
Extract, by the way of integer decimation module adopts multistage cic filter and half-band filter cascade, every grade of cic filter and every grade
All there is selector, cic filter is placed on the front end extracting cascade, and half-band filter is after cic filter before half-band filter
End；
The data rate of the I/Q data that integer decimation module is exported by decimal abstraction module is converted into the code element speed of integral multiple
Rate, can also carry out decimal haplotype data speed and extract conversion to I/Q data file；
The I/Q data that vector demodulation analysis module exports to above-mentioned decimal abstraction module carries out follow-up vector demodulation point
Analysis.
Alternatively, described ADC adopts fixed sample rate, and sample rate value is the integral multiple of 10MHz.
Alternatively, described I/Q changer receives the intermediate-freuqncy signal of described ADC output, is constituted through two multipliers
Frequency mixer after, by input digital signal is multiplied with orthogonal sine signal produced by digital local oscillator, multiplied result be base band
I/Q data.
Alternatively, the decimation factor of described integer decimation module is with 1,2,5,10 fixing gear steppings.
Alternatively, by the way of 5 grades of cascades, half-band filter is by the way of 3 grades of cascades for described cic filter.
Alternatively, decimal abstraction module carries out little several times extraction using sinc interpolation filtering, obtains integral multiple chip rate
I/Q data.
Alternatively, the signal analysis flow process of vector demodulation analysis module includes matched filtering, vector demodulation and modulation matter
Amount analysis.
Present invention also offers a kind of Vector Signal Analysis method, comprise the following steps：
Step (a), carries out A/D quantization to the intermediate-freuqncy signal receiving；
Step (b), the digital signal after A/D is quantified carries out I/Q conversion, will become under digital medium-frequency signal higher for speed
Frequency is baseband I/Q data；
Step (c), carries out integral multiple extraction to the i/q signal after down coversion, integer decimation adopt multistage cic filter and
The mode of half-band filter cascade, all has selector before every grade of cic filter and every grade of half-band filter, cic filter is placed on
Extract the front end of cascade, half-band filter is in the rear end of cic filter；
Step (d), the data rate of the I/Q data after integral multiple is extracted is converted into the chip rate of integral multiple, also may be used
Extract conversion so that I/Q data file is carried out with decimal haplotype data speed；
Step (e), the I/Q data after step (d) is processed carries out vector demodulation analysis.
Alternatively, in step (b), the step of I/Q conversion specifically includes：Digital signal after A/D quantifies is multiplied through two
After the frequency mixer mixing that device is constituted, the digital signal of input is multiplied with orthogonal sine signal produced by digital local oscillator, phase
Result is taken advantage of to be baseband I/Q data.
Alternatively, vector demodulation analysis bag includes matched filtering, vector demodulation and modulation quality analysis.
The invention has the beneficial effects as follows：
(1) digital modulation signals can be carried out with flexible, comprehensive vector demodulation analysis；
(2) adopt fixed rate A/D to sample, programming device carries out I/Q conversion and integral multiple sampling rate conversion, fall
Low existing VSA A/D sampling and the design difficulty of programmable hardware；
(3) carry out the conversion of decimal sampling rate and vector demodulation in VSA software in machine, support non-
The vector recovering and analysis of integral multiple chip rate I/Q file, enhance the comprehensive of vector analyses ability and analysis result.
Brief description
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Have technology description in required use accompanying drawing be briefly described it should be apparent that, drawings in the following description be only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, acceptable
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 realizes schematic diagram for existing Vector Signal Analysis method；
Fig. 2 is the schematic diagram of the Vector Signal Analysis device of the present invention；
Fig. 3 is the theory diagram of the I/Q changer of the present invention；
Fig. 4 is the theory diagram of the integer decimation module of the present invention；
Fig. 5 is the workflow diagram of the decimal abstraction module of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation description is it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of not making creative work
Embodiment, broadly falls into the scope of protection of the invention.
In existing VSA device, lead near handling process front end can for sampling rate conversion and vector demodulation analysis
Programming device logical design is complicated, the analysis of software results in machine is not comprehensively and big using limitation, The present invention gives one
Plant Vector Signal Analysis device and method, superhet VSA is become be mixed tested modulated signal by filtering after
Frequency arrives intermediate frequency, and intermediate-freuqncy signal is digitized after amplifying after filtering, and the intermediate-freuqncy signal after high-speed ADC quantifies becomes through I/Q again
Change and process with filtering extraction, intermediate-freuqncy signal is become the digital I/Q complex signal of zero intermediate frequency, be then based on these I/Q data and carry out
Vector demodulation analysis.
Below in conjunction with the accompanying drawings, the Vector Signal Analysis device and method of the present invention is described in detail.
As shown in Fig. 2 first, ADC carries out A/D quantization using fixed sample rate to the intermediate-freuqncy signal receiving, this
Invention sample rate value is the integral multiple of 10MHz, such as 100MHz, 400MHz, 500MHz etc..Sample rate determines signal
Bandwidth can be analyzed greatly, using fixed sample rate reduce A/D sampling realize difficulty.
Then, the I/Q changer in programmable hardware device carries out I/Q conversion to the digital signal that ADC exports
Obtain baseband I/Q data.
The basic function of I/Q conversion is that digital medium-frequency signal higher for speed is down-converted to digital baseband signal, and Fig. 3 is
I/Q changer of the present invention realize schematic diagram.In Fig. 3, the intermediate-freuqncy signal of high-speed ADC module output sends into I/Q changer；Through two
After the frequency mixer that individual multiplier is constituted, the digital signal of input is multiplied with orthogonal sine signal produced by digital local oscillator,
Multiplied result is I/Q two paths of signals.
Subsequently, i/q signal sends into integer decimation module, completes the integral multiple to the i/q signal after down coversion and extracts.This
In the Vector Signal Analysis device of invention, with 1,2,5,10 fixing gear steppings, the data transfer rate after extraction is defaulted as not decimation factor
Less than 2 times of chip rates it is contemplated that the motility of I/Q data subsequent applications and the compatibility with other systems, after extraction
Data transfer rate can be arranged in the range of 1～20 times of chip rate.Assume that N is every symbol points, (N* chip rate) round up for
1st, 2,5,10 extracted after data transfer rate, then extract ratio be (A/D sample rate)/(data transfer rate after extraction), thus obtaining
The I/Q data of little several times chip rate., when the A/D of 100MHz samples taking the WCDMA signal of 3.84MHz chip rate as a example
In the case of clock, every symbol is set and counts as 2, then 2*3.84MHz=7.68MHz, round up the data transfer rate after being extracted
For 10MHz, extracting than computing formula is 100MHz/10MHz=10.
The integer decimation module of the present invention is realized by the way of multistage cic filter and half-band filter cascade.Due to
Cic filter can be higher with contraction in multiplication device and coefficient memory, operation efficiency, so placing it in the front end extracting cascade,
Realize the extraction of high sampling rate data.Half-band filter frequency characteristic is better than cic filter, used in the rear end of cic filter.This
In invention, cic filter is realized 1～1000 times and is extracted ratio, is realized it is ensured that pressing down outside the band of 67dB by the way of 5 grades of cascades
System, meets stopband attenuation requirement.Half-band filter, by the way of 3 grades of cascades, realizes 1～8 times of extraction ratio.Cic filter
All there is selector with before every grade of half-band filter, choose whether to carry out filtering extraction.Extracting than selection principle is to work as to realize 2,4,8
Times extraction-type selects half-band filter, combine realization extraction by half-band filter and cic filter in the case of other.Taken out with 10 times
Take than as a example, 5 times of filtering extractions will be realized by cic filter, half-band filter realizes 2 times of filtering extractions.
Next, the I/Q number of 1～20 little several times chip rate that above-mentioned integer decimation module is exported by decimal abstraction module
According to the chip rate being converted into integral multiple, I/Q data file can also be carried out with decimal haplotype data speed and extract conversion.The present invention
Little several times extraction is carried out using sinc interpolation filtering, obtains the I/Q data of integral multiple chip rate, integer could be arranged to commonly use
1,2,4,8,16 equivalent.When data transfer rate changes, high fdrequency components to be removed are it is necessary to pass through a low-pass filtering by signal
Device, ideal low-pass filter is exactly sinc function in the form of expression of time domain, as long as therefore realizing input data and sinc function
Convolution i.e. can achieve sampling rate conversion.During realizing, as shown in figure 5, needing to carry out truncate simultaneously to sinc function
Adding window sharpens, for taking into account speed and two kinds of different application situations of precision that little several times extract, respectively using 8 and 40 points
Sinc function, plus Kaiser window carries out intermediate zone sharpening, realizes the selection optimization of speed and precision by controlling switch.
I/Q data not only contains the amplitude information of signal, further comprises the necessary phase information of vector analyses, in signal
There is in analyser application widely, back end signal analysis is almost all based on what I/Q data was carried out, the letter of current main flow
Number analyser all provides I/Q data file to preserve function, and some signal simulation softwares such as MATLAB etc. can also easily be carried out
I/Q file exports, and therefore carries out vector recovering and analysis to I/Q data file and has very important realistic meaning.Due to this
In bright decimal abstraction module, there is little several times extract function, as long as the data in file is read in internal memory according to specific format being
Vector demodulation analysis can be carried out, greatly improve the versatility of vector analyses function.
Finally, the vector demodulation I/Q data to the integral multiple chip rate that above-mentioned decimal abstraction module exports for the analysis module
Carry out follow-up vector demodulation analysis, including a series of signal analyses such as matched filtering, vector demodulation and modulation quality analyses
Flow process.
Digital modulation signals can be carried out flexible, comprehensive vector solution by the Vector Signal Analysis device and method of the present invention
Adjust analysis；Using fixed rate A/D sampling, programming device carries out I/Q conversion and integral multiple sampling rate conversion, reduce existing
There are VSA A/D sampling and the design difficulty of programmable hardware；VSA software in machine is carried out
The conversion of decimal sampling rate and vector demodulation, support the vector recovering and analysis of non-integral multiple chip rate I/Q file, enhance
Vector analyses ability and analysis result comprehensive.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention
Within god and principle, any modification, equivalent substitution and improvement made etc., should be included within the scope of the present invention.
Claims (10)
1. a kind of Vector Signal Analysis device is it is characterised in that include：ADC, I/Q changer, integer decimation module, little
Number abstraction module and vector demodulation analysis module；
ADC carries out A/D quantization to the intermediate-freuqncy signal receiving；
I/Q changer carries out I/Q conversion and obtains baseband I/Q data to the digital signal that ADC exports；
Integer decimation module receives the i/q signal of I/Q changer output, carries out integral multiple extraction to the i/q signal after down coversion,
Integer decimation module by the way of multistage cic filter and half-band filter cascade, filter by every grade of cic filter and every grade half band
All there is selector, cic filter is placed on the front end extracting cascade, and half-band filter is in the rear end of cic filter before ripple device；Extract
It is to select half-band filter when realizing 2,4,8 times and extracting than selection principle, by half-band filter and CIC filtering in the case of other
Device combination is realized extracting；
The data rate of the I/Q data that integer decimation module is exported by decimal abstraction module is converted into the chip rate of integral multiple,
I/Q data file can also be carried out with decimal haplotype data speed and extract conversion；
The I/Q data that vector demodulation analysis module exports to above-mentioned decimal abstraction module carries out follow-up vector demodulation analysis.
2. as claimed in claim 1 a kind of Vector Signal Analysis device it is characterised in that described ADC using fixation adopt
Sample rate, sample rate value is the integral multiple of 10MHz.
3. as claimed in claim 1 a kind of Vector Signal Analysis device it is characterised in that described I/Q changer receive described
The intermediate-freuqncy signal of ADC output, through after the frequency mixer that two multipliers are constituted, by the digital signal of input and digital local oscillator
Produced orthogonal sine signal is multiplied, and multiplied result is baseband I/Q data.
4. as claimed in claim 1 a kind of Vector Signal Analysis device it is characterised in that the extraction of described integer decimation module
The factor is with 1,2,5,10 fixing gear steppings.
5. as claimed in claim 4 a kind of Vector Signal Analysis device it is characterised in that described cic filter adopt 5 grades of levels
The mode of connection, half-band filter is by the way of 3 grades of cascades.
6. as claimed in claim 1 a kind of Vector Signal Analysis device it is characterised in that decimal abstraction module adopt sinc in
Slotting filtering carries out little several times extraction, obtains the I/Q data of integral multiple chip rate.
7. as claimed in claim 1 a kind of Vector Signal Analysis device it is characterised in that vector demodulate analysis module signal
Analysis process includes matched filtering, vector demodulation and modulation quality analysis.
8. a kind of Vector Signal Analysis method is it is characterised in that comprise the following steps：
Step (a), carries out A/D quantization to the intermediate-freuqncy signal receiving；
Step (b), the digital signal after A/D is quantified carries out I/Q conversion, and digital medium-frequency signal higher for speed is down-converted to
Baseband I/Q data；
Step (c), carries out integral multiple extraction to the i/q signal after down coversion, and integer decimation adopts multistage cic filter and half to carry
The mode of wave filter cascade, all has selector before every grade of cic filter and every grade of half-band filter, cic filter is placed on extraction
The front end of cascade, half-band filter is in the rear end of cic filter；Extracting than selection principle is the choosing when realizing 2,4,8 times and extracting
Select half-band filter, in the case of other, realization is combined by half-band filter and cic filter and extract；
Step (d), the data rate of the I/Q data after integral multiple is extracted is converted into the chip rate of integral multiple, can also be right
I/Q data file carries out decimal haplotype data speed and extracts conversion；
Step (e), the I/Q data after step (d) is processed carries out vector demodulation analysis.
9. as claimed in claim 8 a kind of Vector Signal Analysis method it is characterised in that in step (b), the step of I/Q conversion
Suddenly specifically include：Digital signal after A/D quantization, after the frequency mixer mixing that two multipliers are constituted, the numeral of input is believed
Number it is multiplied with orthogonal sine signal produced by digital local oscillator, multiplied result is baseband I/Q data.
10. a kind of Vector Signal Analysis method includes coupling it is characterised in that vector demodulates analysis bag as claimed in claim 9
Filtering, vector demodulation and modulation quality analysis.
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| CN108762154B (en) * | 2018-06-05 | 2019-11-05 | 中国电子科技集团公司第四十一研究所 | The parallel down coversion FPGA data processing system of Vector Signal Analysis high speed and method |
| CN110768682B (en) * | 2019-10-30 | 2022-01-04 | 中国电子科技集团公司第四十一研究所 | PXIe bus vector signal real-time transceiving module device and method |
| CN111049772B (en) * | 2019-12-20 | 2023-09-29 | 上海创远仪器技术股份有限公司 | System and method for realizing 5G signal synchronous processing applied to vector signal analyzer platform |
| CN117749134A (en) * | 2024-02-19 | 2024-03-22 | 成都玖锦科技有限公司 | Data playback method for baseband data and intermediate frequency data |
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