CN104425448A - Anti-fuse structure - Google Patents
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- CN104425448A CN104425448A CN201310410836.4A CN201310410836A CN104425448A CN 104425448 A CN104425448 A CN 104425448A CN 201310410836 A CN201310410836 A CN 201310410836A CN 104425448 A CN104425448 A CN 104425448A
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Abstract
The invention relates to an anti-fuse structure which comprises an NMOS transistor and a programmable transistor, wherein the trench length at the edge in the NMOS transistor is greater than that at the center of the NMOS transistor; a source region in the NMOS transistor is connected with the programmable transistor; a drain region in the programmable transistor is connected with a programmable power supply. The anti-fuse structure comprises an MOS transistor; the trench length at the edge part in the MOS transistor is greater than that at the center part of the MOS transistor; correspondingly, key sizes of two ends in a gate electrode structure are greater than the key size of the middle part; when the anti-fuse structure is programmed, after programming voltage is applied to the drain region and the programmable transistor, breakdown of the source region and the drain region is initiated, so that a passageway is formed, and an anti-fuse effect is achieved.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of anti-fuse structures.
Background technology
Along with the development of semiconductor technology, antifuse (Anti-fuse) technology has attracted the remarkable concern of a lot of inventor, integrated circuit (integrated circuits, IC) designer and manufacturer.Antifuse is the structure that can change to conduction state, or in other words, antifuse is that never conduction state changes into the electronic device of conduction state.Equally, binary condition can be in response to any one in the high resistance of electric stress (as program voltage or program current) and low resistance.Antifuse device can be disposed in storage array, forms generally known One Time Programmable (OTP) memory thus.
The programmable chip technology of antifuse (Anti-fuse) provides the conductive path between stable and transistor, relative to the molten link method of the fuse (blowing fuses) of routine, antifuse technology is the novel electricity device of a class, antifuse starts to have very high resistance most, be in off-state, but when applying voltage on described anti-fuse structures, form permanent path when voltage exceedes to a certain degree described anti-fuse structures.
Anti-fuse structures is widely used in integrated circuit (the integrated circuits of permanent programming (permanently program), IC) in, such as certain programming drain device (Certainprogrammable logic devices), special object and integrated circuit (the ApplicationSpecific Integrated Circuit designed, ASIC), the design of the logical circuit utilizing anti-fuse structures to configure and IC design establishment one customization from a standard, anti-fuse structures may be used for program read-only memory (programmable read-only memory, PROM) in.
In prior art, the structure of antifuse (Anti-fuse) as seen in figure la and lb, wherein, described substrate 101 is formed the sandwich structure of metal level 102-dielectric layer 103-metal level 104, wherein said dielectric layer is amorphous silicon (amorphous silicon), described antifuse is utilized to carry out the sequencing of grid array, wherein as shown in Figure 1a, when not applying voltage on described anti-fuse structures, described middle dielectric layer is in "off" state, now described dielectric layer is non-conductive, when applying voltage on described fuse-wires structure, described dielectric layer amorphous silicon (amorphous silicon) becomes polysilicon (polysilicon), be in conduction state, described antifuse is in "open" state, as shown in Figure 1 b, the sequencing of antifuse is carried out with this.Another anti-fuse structures, metal alloy is selected in intermediate layer, such as tungsten alloy, titanium alloy and siliceous alloy.
Anti-fuse structures is used widely in integrated circuits, but the long-time stability of anti-fuse structures become a major issue of anti-fuse structures, because along with the prolongation of time, described anti-fuse structures has the trend of performance degradation.
Therefore, although antifuse technology is developed widely in semiconductor technology and is applied, but along with the development of semiconductor technology and constantly reducing of device size, how to ensure that described anti-fuse structures has the problem that good stability becomes needs solution in for a long time, all there is described problem in various anti-fuse structures of the prior art, be not well solved at present, need to be improved further the structure of antifuse, to eliminate the problems referred to above.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of anti-fuse structures, comprising:
Nmos pass transistor, in described nmos pass transistor, the channel length of edge is greater than the channel length of center;
Programming transistor, the source region in described nmos pass transistor is connected with described programming transistor, and the drain region in described nmos pass transistor is connected with programming power supply.
As preferably, grid and the tagma of described nmos pass transistor are floating.
As preferably, the grid of described nmos pass transistor and source region are connected to described programming transistor, and the tagma of described nmos pass transistor is floating.
As preferably, the grid of described nmos pass transistor, source region and tagma are connected to described programming transistor.
As preferably, described nmos pass transistor comprises:
Semiconductor substrate;
Grid structure, is positioned in described Semiconductor substrate, and the length of the raceway groove below described grid structure two ends is greater than the length of middle raceway groove;
Source region and drain region are positioned at the both sides of described grid structure, and described source region is connected with programming transistor, and described drain region is connected with programming power supply.
As preferably, the critical size at the two ends of described grid structure is greater than middle critical size.
As preferably, described anti-fuse structures also comprises the LDD doped region be only positioned at inside described drain region.
As preferably, described anti-fuse structures also comprises the LDD doped region be positioned at inside described source region and the LDD doped region be positioned at inside described drain region.
As preferably, described Semiconductor substrate is P type semiconductor substrate.
As preferably, be formed with P trap in described P type semiconductor substrate, described anti-fuse structures is arranged on described P trap.
As preferably, described source region and described drain region are N-type doping.
As preferably, described anti-fuse structures also comprises P type doped region, and described P type doped region is arranged in described P trap.
As preferably, described P type doped region is connected with described programming transistor.
Anti-fuse structures of the present invention comprises a MOS transistor, in described MOS transistor, the channel length of marginal portion is greater than the length of the raceway groove of core, accordingly, in described grid structure, the critical size at two ends is greater than the critical size of middle part, after applying program voltage during described anti-fuse structures programming on described drain region and programming transistor, cause puncturing of source region and drain region, form path, play the effect of antifuse.
The raceway groove that the critical size of nmos pass transistor edge described in described anti-fuse structures is larger can ensure that the raceway groove of described edge channels and middle part can be simultaneously breakdown, realize programming simultaneously, contribute to described anti-fuse structures and obtain consistent (uniform) blown state, achieve the fusing speed that can not realize in PPM rank in prior art.Described anti-fuse structures is set can solves by described the problem that the anti-fuse structures caused due to amorphous silicon (amorphous silicon) and metal alloy in prior art is difficult to maintain a long-term stability, anti-fuse structures after improvement can keep long stability, has good performance and yield.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-1b be in prior art anti-fuse structures be in pass and open state time structural representation;
Fig. 2 a-2c is structural representation and the circuit diagram of anti-fuse structures in the embodiment of the invention;
Fig. 3 is the structural representation of nmos pass transistor described in the embodiment of the invention;
Fig. 4 be in the embodiment of the invention channel width to the schematic diagram of anti-fuse structures stability influence.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed description is proposed, so that anti-fuse structures of the present invention to be described.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
The present invention, in order to solve the various problems existed in prior art, provides a kind of anti-fuse structures, comprising:
Semiconductor substrate;
Grid structure, is positioned in described Semiconductor substrate, and the length of the raceway groove at described grid structure two ends is greater than the length of intermediate channel;
Source region and drain region are positioned at the both sides of described grid structure, and described source region is connected with programming transistor, and described drain region is connected with programming power supply.
Anti-fuse structures of the present invention comprises a MOS transistor, be preferably nmos pass transistor, in described NMOS, raceway groove is arranged at conventional nmos pass transistor difference, in described nmos pass transistor, the channel length of marginal portion is greater than the length of the raceway groove of core, accordingly, in described grid structure, the critical size at two ends is greater than the critical size of middle part.
Wherein, described source region is connected with the drain electrode of described programming transistor, the source ground of described programming transistor, and the grid of described programming transistor connects programming power supply.
After applying program voltage during the programming of described anti-fuse structures on described drain region and programming transistor, cause puncturing of source region and drain region, form path, now, described grid structure becomes floating boom, is in the state of path ON after described nmos pass transistor is breakdown always, plays the effect of antifuse.
The raceway groove that the critical size of nmos pass transistor edge described in described anti-fuse structures is larger can ensure that the raceway groove of described edge channels and middle part can be simultaneously breakdown, realize programming simultaneously, contribute to described anti-fuse structures and obtain consistent (uniform) blown state, achieve the fusing speed that can not realize in PPM rank in prior art.Described anti-fuse structures is set can solves by described the problem that the anti-fuse structures caused due to amorphous silicon (amorphous silicon) and metal alloy in prior art is difficult to maintain a long-term stability, anti-fuse structures after improvement can keep long stability, has good performance and yield.
Wherein, described MOS transistor can be symmetrical, and the inner side that the such as inner side in described source region and drain region is formed with LDD doped region or described source region and drain region simultaneously does not form LDD doped region; In addition, described MOS transistor can also be asymmetric, such as, only form LDD doped region in the inner side of doped region, described source region, in described drain region, do not form LDD doped region.
Below in conjunction with accompanying drawing, anti-fuse structures of the present invention is described in further detail.
Embodiment 1
First with reference to Fig. 2 a, Fig. 2 a is the described anti-fuse structures of the present invention one execution mode particularly, the wherein schematic diagram attempted for described anti-fuse structures on the left side, the circuit diagram attempted for described anti-fuse structures on the right side.
As shown in Figure 2 a, described anti-fuse structures comprises a nmos pass transistor, described nmos pass transistor comprises Semiconductor substrate 201, grid structure 205, be positioned in described Semiconductor substrate, source region 204 and drain region 203 are positioned at the both sides of described grid structure, and described source region is connected with programming transistor, and described drain region is connected with programming power supply Vd.Further, described source region 204 is connected with the drain electrode of described programming transistor, the source ground of described programming transistor, and the grid of described programming transistor connects programming power supply Vd.
Wherein, described Semiconductor substrate 201 can be selected from silicon, silicon-on-insulator (SOI), insulator stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator.It Semiconductor substrate 201 is P type substrate.
As preferably, P trap 202 is formed in described Semiconductor substrate 201, described grid structure 205, source region 204 and drain region 203 are all arranged on described P trap 202, the formation method of described P trap 202 is doped with P type admixture in described Semiconductor substrate 201, such as boron, such as by ion implantation technology, boron can be injected and described Semiconductor substrate 201, then utilize Technology for Heating Processing to drive in admixture, to form P type admixture.
Described grid structure 205 is positioned on described P trap 202, described grid structure 205 can be conventional polysilicon gate can also be metal gate structure, the gate dielectric be positioned in described Semiconductor substrate 201 is comprised in described grid structure 205, the setting of other routines such as offset side wall and clearance wall can also be comprised, do not repeat them here, those skilled in the art can design according to actual needs, are not limited to a certain structure.
Described grid structure 205 is with the setting of conventional gate structure difference in described grid structure shape, the vertical view of grid structure 205 described in this embodiment as shown in Figure 3, described grid structure 205 entirety is in " dumbbell shaped ", shape thin in the middle of the two ends that described grid structure 205 is are thick, the critical size of the edges at two ends of described grid structure 205 is Lw, the critical size of described grid structure 205 mid portion is Ln, the critical size of the edges at two ends part of described grid structure 205 and the lap in described source region 204 is We, and wherein Lw is greater than Ln.
By the setting of described gate shapes, the length that can obtain edge's raceway groove accordingly in described nmos pass transistor is larger, and the length of mid portion raceway groove is less, the raceway groove that the critical size of nmos pass transistor edge described in described anti-fuse structures is larger can ensure that the raceway groove of described edge channels and middle part can be simultaneously breakdown, realize programming simultaneously, contribute to described anti-fuse structures and obtain consistent (uniform) blown state, achieve the fusing speed that can not realize in PPM rank in prior art, long stability can be kept, there is good performance and yield.In addition, can also by the length of further preferred described Lw, Ln and We, to obtain best programing effect and stability.
As Fig. 4 be in this embodiment channel width to the schematic diagram of anti-fuse structures stability influence, the performance degradation of the described anti-fuse structures of reduction can found out along with channel width by this figure is constantly increased, and be because owing to forming boundary defect (interface traps) at marginal position place and shallow trench isolation intersection in the marginal position place wider channel width of setting, cause the transposition (modulation) of electric field, after therefore edge's channel length being widened, can guarantee that it has consistent breakdown performance with center raceway groove.
Source region 204 and drain region 203 is also formed in the both sides of described grid structure, as preferably, described source region 204 and drain region 203 are formed by the mode of ion implantation after formation grid skew sidewall and clearance wall, described N-type dopant comprises P, As, Sb, the ion energy of described injection is 1kev-10kev, and the ion dose of injection is 5 × 10
14-5 × 10
16atom/cm
2.Be preferably less than 400 DEG C in the present invention, and comparatively independently can control Impurity Distribution (ion energy) and impurity concentration (ion current density and injection length) by described method, the method more easily obtains the doping of high concentration, and be anisotropy doping, can independently controlling depth and concentration.
The transistor of anti-fuse structures described in this embodiment is nmos pass transistor, but it should be noted that to illustrate that transistor is defined as NMOS by the structure of this transistor better, but described transistor can also be PMOS transistor or other transistors, be not limited to a certain, as long as said structure can be had, realize the effect of transistor.
As further preferred, described anti-fuse structures can also comprise LDD doped region 206 further, described LDD doped region 206 can only be formed in the inner side in source region 204, now described nmos pass transistor is non-symmetric transistor, described LDD doped region 206 can also be arranged at the inner side in described source region 204 and drain region 203 simultaneously, now, described nmos pass transistor is symmetrical transistor.
In order to simplify the preparation technology of described antifuse, described LDD doped region 206 can not also be formed, relative to formation LDD doped region 206, when not forming LDD doped region 206 in the inner side in described source region 204 and drain region 203, it has higher electric field in drain region, and the puncture voltage in source region-drain region is also lower simultaneously.
Described LDD doped region 206 is N-type light dope, and described LDD doped region 206 can be formed by ion implantation technology or diffusion technology.The ionic type that described LDD injects is according to the electrical decision of the semiconductor device that will be formed, and the device namely formed is nmos device, then the foreign ion mixed in LDD injection technology is one in phosphorus, arsenic, antimony, bismuth or combination.
The Programming Principle of the anti-fuse structures in this embodiment is: described drain region 204 is connected with programming power supply, described source region 204 is connected with the drain electrode of described programming transistor, the source ground of described programming transistor, the grid of described programming transistor connects programming power supply, after applying program voltage during the programming of described anti-fuse structures on the grid of described drain region 204 and programming transistor, cause puncturing of source region and drain region, form path, now, described grid structure and described Semiconductor substrate floating, be in the state of path ON after described nmos pass transistor is breakdown always, play the effect of antifuse.Wherein said floating be exactly not electric power loop ground connection, any phase, neutral point etc. of no matter both positive and negative polarity, mid point or interchange, in this embodiment, described grid structure and all unearthed formation current circuit of described Semiconductor substrate.When there is no specified otherwise, described floating all with reference to this explanation in this application.
Embodiment 2
First with reference to Fig. 2 b, Fig. 2 b is the described anti-fuse structures of the present invention one execution mode particularly, the wherein schematic diagram attempted for described anti-fuse structures on the left side, the circuit diagram attempted for described anti-fuse structures on the right side.
As shown in Figure 2 b, described anti-fuse structures comprises a nmos pass transistor, described MOS transistor comprises Semiconductor substrate 201, grid structure 205, be positioned in described Semiconductor substrate, source region 204 and drain region 203 are positioned at the both sides of described grid structure, and described source region and described grid structure 205 are connected with programming transistor, and described drain region is connected with programming power supply Vd.
Wherein, described Semiconductor substrate 201 is P type substrate, and as preferably, in described Semiconductor substrate 201, form P trap 202, described grid structure 205, source region 204 and drain region 203 are all arranged on described P trap 202.
The substrate that described Semiconductor substrate 201 can select this area conventional, the formation method of described P trap can select conventional doping method, the ionic species of described doping and concentration etc. all can design according to device, are not limited to a certain or a certain scope, do not repeat them here.
Described grid structure 205 is positioned on described P trap 202, described grid structure 205 can be conventional polysilicon gate can also be metal gate structure, the gate dielectric be positioned in described Semiconductor substrate 201 is comprised in described grid structure 205, the setting of other routines such as offset side wall and clearance wall can also be comprised, do not repeat them here, those skilled in the art can design according to actual needs, are not limited to a certain structure.
Described grid structure 205 is with the setting of conventional gate structure difference in described grid structure shape, the vertical view of grid structure 205 described in this embodiment as shown in Figure 3, described grid structure 205 entirety is in " dumbbell shaped ", shape thin in the middle of the two ends that described grid structure 205 is are thick, the critical size of the edges at two ends of described grid structure 205 is Lw, the critical size of described grid structure 205 mid portion is Ln, the critical size of the edges at two ends part of described grid structure 205 and the lap in described source region 204 is We, and wherein Lw is greater than Ln.
By the setting of described gate shapes, the length that can obtain edge's raceway groove accordingly in described nmos pass transistor is larger, and the length of mid portion raceway groove is less, the raceway groove that the critical size of nmos pass transistor edge described in described anti-fuse structures is larger can ensure that the raceway groove of described edge channels and middle part can be simultaneously breakdown, realize programming simultaneously, contribute to described anti-fuse structures and obtain consistent (uniform) blown state, achieve the fusing speed that can not realize in PPM rank in prior art, long stability can be kept, there is good performance and yield.In addition, can also by the length of further preferred described Lw, Ln and We, to obtain best programing effect and stability.
Source region 204 and drain region 203 is also formed in the both sides of described grid structure, as preferably, described source region 204 and drain region 203 are formed by the mode of ion implantation after formation grid skew sidewall and clearance wall, described N-type dopant comprises P, As, Sb, the ion energy of described injection is 1kev-10kev, and the ion dose of injection is 5 × 10
14-5 × 10
16atom/cm
2.Be preferably less than 400 DEG C in the present invention, and comparatively independently can control Impurity Distribution (ion energy) and impurity concentration (ion current density and injection length) by described method, the method more easily obtains the doping of high concentration, and be anisotropy doping, can independently controlling depth and concentration.
The transistor of anti-fuse structures described in this embodiment is nmos pass transistor, but it should be noted that to illustrate that transistor is defined as NMOS by the structure of this transistor better, but described transistor can also be PMOS transistor or other transistors, be not limited to a certain, as long as said structure can be had, realize the effect of transistor.
As further preferred, described anti-fuse structures can also comprise LDD doped region 206 further, described LDD doped region 206 can only be formed in the inner side in source region 204, now described nmos pass transistor is non-symmetric transistor, described LDD doped region 206 can also be arranged at the inner side in described source region 204 and drain region 203 simultaneously, now, described nmos pass transistor is symmetrical transistor.
In order to simplify the preparation technology of described antifuse, described LDD doped region 206 can not also be formed, relative to formation LDD doped region 206, when not forming LDD doped region 206 in the inner side in described source region 204 and drain region 203, it has higher electric field in drain region, and the puncture voltage in source region-drain region is also lower simultaneously.
Described LDD doped region 206 is N-type light dope, and described LDD doped region 206 can be formed by ion implantation technology or diffusion technology.The ionic type that described LDD injects is according to the electrical decision of the semiconductor device that will be formed, and the device namely formed is nmos device, then the foreign ion mixed in LDD injection technology is one in phosphorus, arsenic, antimony, bismuth or combination.
The Programming Principle of the anti-fuse structures in this embodiment is: described drain region 204 is connected with programming power supply, described source region 204 is connected with the drain electrode of described programming transistor, the source ground of described programming transistor, the grid of described programming transistor connects programming power supply, after applying program voltage during the programming of described anti-fuse structures on the grid of described drain region 204 and programming transistor, cause puncturing of source region and drain region, form path, now, described Semiconductor substrate 205 is floating, be in the state of path ON after described nmos pass transistor is breakdown always, play the effect of antifuse.
Embodiment 3
In this embodiment, described anti-fuse structures also comprises the P type doped region 207 be positioned at outside described source region 204 further, and as shown in Figure 2 c, described P type doped region 207 is arranged with described P trap 202, and described P type doped region 207 is connected with described programming transistor.
Other formations of described anti-fuse structures are all identical with embodiment 2, with reference to embodiment 2, can not repeat them here.
The Programming Principle of the anti-fuse structures in this embodiment is: described drain region 204 is connected with programming power supply, described source region 204 is connected with the drain electrode of described programming transistor, the source ground of described programming transistor, the grid of described programming transistor connects programming power supply, after applying program voltage during the programming of described anti-fuse structures on the grid of described drain region 204 and programming transistor, cause puncturing of source region and drain region, form path, now, described grid structure 205, Semiconductor substrate 201, drain region 205 and source region 204 are all communicated with, be in the state of path ON after described nmos pass transistor is breakdown always, play the effect of antifuse.
Anti-fuse structures of the present invention comprises a MOS transistor, in described MOS transistor, the channel length of marginal portion is greater than the length of the raceway groove of core, accordingly, in described grid structure, the critical size at two ends is greater than the critical size of middle part, after applying program voltage during described anti-fuse structures programming on described drain region and programming transistor, cause puncturing of source region and drain region, form path, play the effect of antifuse.
The raceway groove that the critical size of nmos pass transistor edge described in described anti-fuse structures is larger can ensure that the raceway groove of described edge channels and middle part can be simultaneously breakdown, realize programming simultaneously, contribute to described anti-fuse structures and obtain consistent (uniform) blown state, achieve the fusing speed that can not realize in PPM rank in prior art.Described anti-fuse structures is set can solves by described the problem that the anti-fuse structures caused due to amorphous silicon (amorphous silicon) and metal alloy in prior art is difficult to maintain a long-term stability, anti-fuse structures after improvement can keep long stability, has good performance and yield.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (13)
1. an anti-fuse structures, comprising:
Nmos pass transistor, in described nmos pass transistor, the channel length of edge is greater than the channel length of center;
Programming transistor, the source region in described nmos pass transistor is connected with described programming transistor, and the drain region in described nmos pass transistor is connected with programming power supply.
2. anti-fuse structures according to claim 1, is characterized in that, grid and the tagma of described nmos pass transistor are floating.
3. anti-fuse structures according to claim 1, is characterized in that, the grid of described nmos pass transistor and source region are connected to described programming transistor, and the tagma of described nmos pass transistor is floating.
4. anti-fuse structures according to claim 1, is characterized in that, the grid of described nmos pass transistor, source region and tagma are connected to described programming transistor.
5. anti-fuse structures according to claim 1, is characterized in that, described nmos pass transistor comprises:
Semiconductor substrate;
Grid structure, is positioned in described Semiconductor substrate, and the length of the raceway groove below described grid structure two ends is greater than the length of middle raceway groove;
Source region and drain region are positioned at the both sides of described grid structure, and described source region is connected with programming transistor, and described drain region is connected with programming power supply.
6. anti-fuse structures according to claim 5, is characterized in that, the critical size at the two ends of described grid structure is greater than middle critical size.
7. anti-fuse structures according to claim 5, is characterized in that, described anti-fuse structures also comprises the LDD doped region be only positioned at inside described drain region.
8. anti-fuse structures according to claim 5, is characterized in that, described anti-fuse structures also comprises the LDD doped region be positioned at inside described source region and the LDD doped region be positioned at inside described drain region.
9. anti-fuse structures according to claim 5, is characterized in that, described Semiconductor substrate is P type semiconductor substrate.
10. anti-fuse structures according to claim 9, is characterized in that, is formed with P trap in described P type semiconductor substrate, and described anti-fuse structures is arranged on described P trap.
11. anti-fuse structures according to claim 9, is characterized in that, described source region and described drain region are N-type doping.
12. anti-fuse structures according to claim 10, is characterized in that, described anti-fuse structures also comprises P type doped region, and described P type doped region is arranged in described P trap.
13. anti-fuse structures according to claim 12, is characterized in that, described P type doped region is connected with described programming transistor.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786359A (en) * | 2017-11-13 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN109961821A (en) * | 2017-12-22 | 2019-07-02 | 长鑫存储技术有限公司 | Disposable programmable non-volatile fuse storage unit |
| CN113314170A (en) * | 2020-02-27 | 2021-08-27 | 台湾积体电路制造股份有限公司 | One-time programmable memory cell and electronic device |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6143612A (en) * | 1998-10-14 | 2000-11-07 | Advanced Micro Devices, Inc. | High voltage transistor with high gated diode breakdown, low body effect and low leakage |
| US6229733B1 (en) * | 1999-03-24 | 2001-05-08 | Texas Instruments Incorporated | Non-volatile memory cell for linear mos integrated circuits utilizing fused mosfet gate oxide |
| KR20020090421A (en) * | 2001-05-25 | 2002-12-05 | 주식회사 하이닉스반도체 | Redundancy circuits |
| US20030231534A1 (en) * | 2002-06-14 | 2003-12-18 | Nec Electronics Corporation | Data latch circuit having anti-fuse elements |
| US20040004268A1 (en) * | 2002-07-08 | 2004-01-08 | International Business Machines Corporation | E-Fuse and anti-E-Fuse device structures and methods |
| CN1610007A (en) * | 2003-10-07 | 2005-04-27 | 尔必达存储器股份有限公司 | Antifuse programming circuit in which one stage of transistor is interposed in a series with antifuse between power supplies during programming |
| US20080185627A1 (en) * | 2007-02-02 | 2008-08-07 | Horch Andrew E | RFID tag having non-volatile memory device having floating-gate fets with different source-gate and drain-gate border lengths |
| US20090059645A1 (en) * | 2007-08-28 | 2009-03-05 | Broadcom Corporation | One time programmable memory |
| US20100124139A1 (en) * | 2008-11-19 | 2010-05-20 | Elpida Memory, Inc. | Semiconductor device including an anti-fuse element |
| US20100127731A1 (en) * | 2008-11-27 | 2010-05-27 | Samsung Electronics Co., Ltd. | Antifuse circuit of inverter type and method of programming the same |
| KR20110111954A (en) * | 2010-04-06 | 2011-10-12 | 창원대학교 산학협력단 | Antifuse one time programmable cell of dual port |
| CN102272854A (en) * | 2009-12-16 | 2011-12-07 | 英特尔公司 | Antifuse programmable memory array |
| CN102376360A (en) * | 2010-08-20 | 2012-03-14 | 庄建祥 | Phase change memory, electronic system, reversible resistive memory, and providing method |
-
2013
- 2013-09-10 CN CN201310410836.4A patent/CN104425448B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6143612A (en) * | 1998-10-14 | 2000-11-07 | Advanced Micro Devices, Inc. | High voltage transistor with high gated diode breakdown, low body effect and low leakage |
| US6229733B1 (en) * | 1999-03-24 | 2001-05-08 | Texas Instruments Incorporated | Non-volatile memory cell for linear mos integrated circuits utilizing fused mosfet gate oxide |
| KR20020090421A (en) * | 2001-05-25 | 2002-12-05 | 주식회사 하이닉스반도체 | Redundancy circuits |
| US20030231534A1 (en) * | 2002-06-14 | 2003-12-18 | Nec Electronics Corporation | Data latch circuit having anti-fuse elements |
| US20040004268A1 (en) * | 2002-07-08 | 2004-01-08 | International Business Machines Corporation | E-Fuse and anti-E-Fuse device structures and methods |
| CN1610007A (en) * | 2003-10-07 | 2005-04-27 | 尔必达存储器股份有限公司 | Antifuse programming circuit in which one stage of transistor is interposed in a series with antifuse between power supplies during programming |
| US20080185627A1 (en) * | 2007-02-02 | 2008-08-07 | Horch Andrew E | RFID tag having non-volatile memory device having floating-gate fets with different source-gate and drain-gate border lengths |
| US20090059645A1 (en) * | 2007-08-28 | 2009-03-05 | Broadcom Corporation | One time programmable memory |
| US20100124139A1 (en) * | 2008-11-19 | 2010-05-20 | Elpida Memory, Inc. | Semiconductor device including an anti-fuse element |
| US20100127731A1 (en) * | 2008-11-27 | 2010-05-27 | Samsung Electronics Co., Ltd. | Antifuse circuit of inverter type and method of programming the same |
| CN102272854A (en) * | 2009-12-16 | 2011-12-07 | 英特尔公司 | Antifuse programmable memory array |
| KR20110111954A (en) * | 2010-04-06 | 2011-10-12 | 창원대학교 산학협력단 | Antifuse one time programmable cell of dual port |
| CN102376360A (en) * | 2010-08-20 | 2012-03-14 | 庄建祥 | Phase change memory, electronic system, reversible resistive memory, and providing method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786359A (en) * | 2017-11-13 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN109786359B (en) * | 2017-11-13 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN109961821A (en) * | 2017-12-22 | 2019-07-02 | 长鑫存储技术有限公司 | Disposable programmable non-volatile fuse storage unit |
| CN113314170A (en) * | 2020-02-27 | 2021-08-27 | 台湾积体电路制造股份有限公司 | One-time programmable memory cell and electronic device |
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