CN104425498A - Storage apparatus and manufacture method thereof - Google Patents
Storage apparatus and manufacture method thereof Download PDFInfo
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- CN104425498A CN104425498A CN201310382680.3A CN201310382680A CN104425498A CN 104425498 A CN104425498 A CN 104425498A CN 201310382680 A CN201310382680 A CN 201310382680A CN 104425498 A CN104425498 A CN 104425498A
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- peripheral circuit
- memory array
- dimensional memory
- storage device
- metal layer
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Abstract
The invention discloses a storage apparatus and a manufacture method thereof. The storage apparatus comprises a substrate, a 3D memory array, a periphery circuit and a conductive connection structure. The 3D memory array and the periphery circuit are arranged on the substrate in a laminated mode. The periphery circuit comprises a patterning metal layer and a contact structure. The contact structure is electrically connected with the patterning metal layer. The connective connection structure is electrically connected with the patterning metal layer. The 3D memory array is connected with the periphery circuit through the conductive connection structure.
Description
Technical field
The invention relates to a kind of storage device and manufacture method thereof, and relate to a kind of storage device and the manufacture method thereof with vertical stack structure especially.
Background technology
The structure of semiconductor element constantly changes in recent years, and the memory storage capacity of element also constantly increases.Storage device is used in many products, such as, in the storage unit of MP3 player, digital camera, computer archives etc.Along with the increase of application, the demand for storage device also tends to less size, larger memory capacity.In response to this demand, be need manufacture high component density and there is undersized storage device.
Therefore, designers are devoted to develop a kind of three-dimensional memory devices invariably, not only have many lamination planes and reach higher storage volume, possessing good characteristic, have more small size simultaneously.
Summary of the invention
The invention relates to a kind of storage device and manufacture method thereof.In storage device, by three-dimensional memory array and peripheral circuit vertical stack, the area that element occupies at chip surface significantly can be reduced, and then effectively reach the effect of chip size micro.
According to one embodiment of the invention, be propose a kind of storage device.Storage device comprises a substrate, a three-dimensional memory array (3Dmemory array), a peripheral circuit (periphery circuit) and a conduction connecting structure (conductive connection structure).Three-dimensional memory array and peripheral circuit lamination are arranged on substrate.Peripheral circuit comprises a patterned metal layer and contact structures (contactstructure), and contact structures are electrically connected at patterned metal layer.Conduction connecting structure is electrically connected at patterned metal layer, and three-dimensional memory array is electrically connected to peripheral circuit via conduction connecting structure.
According to another embodiment of the present invention, be the manufacture method proposing a kind of storage device.The manufacture method of storage device comprises the following steps.One substrate is provided; One three-dimensional memory array is set and a peripheral circuit is stacked on substrate; And form a conduction connecting structure.Peripheral circuit comprises a patterned metal layer and contact structures, and contact structures are electrically connected at patterned metal layer.Conduction connecting structure is electrically connected at patterned metal layer, and three-dimensional memory array is electrically connected to peripheral circuit via conduction connecting structure.
In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinating institute's accompanying drawings, being described in detail below:
Accompanying drawing explanation
Fig. 1 illustrates the stereogram of storage device according to an embodiment of the invention.
Fig. 2 illustrates the end view of storage device according to an embodiment of the invention.
Fig. 3 illustrates the stereogram of storage device according to another embodiment of the present invention.
Fig. 4 illustrates the end view of storage device according to another embodiment of the present invention.
Fig. 5 illustrates the simplification stereogram of conduction connecting structure according to an embodiment of the invention.
Fig. 6 A to Fig. 6 C illustrates the manufacture method schematic diagram of the storage device according to one embodiment of the invention.
Fig. 7 A to Fig. 7 C illustrates the manufacture method schematic diagram of the storage device according to another embodiment of the present invention.
[symbol description]
100,200: storage device
110: substrate
120: three-dimensional memory array
130: peripheral circuit
131,131a, 131b: patterned metal layer
133,133a, 133b: contact structures
135: transistor
140,140 ', 340,540,540 ': conduction connecting structure
150: insulating barrier
360: silicon epitaxial layers
580: chip
ML, ML1, ML2, ML3: metal level
Embodiment
In an embodiment of the present invention, be propose a kind of storage device and manufacture method thereof.In storage device, by three-dimensional memory array and peripheral circuit vertical stack, the area that element occupies at chip surface significantly can be reduced, and then effectively reach the effect of chip size micro.Below propose various embodiment to be described in detail.But embodiment, can't the scope of limit the present invention for protecting only in order to illustrate as example.In addition, the graphic element being omission part and wanting in embodiment, with clear display technical characterstic of the present invention.
Fig. 1 illustrates the stereogram of storage device 100 according to an embodiment of the invention, and Fig. 2 illustrates the end view of storage device 100 according to an embodiment of the invention.Please refer to Fig. 1 ~ Fig. 2, storage device 100 comprises substrate 110, three-dimensional memory array (3Dmemory array) 120, peripheral circuit (peripherycircuit) 130 and conduction connecting structure (conductive connection structure) 140.Three-dimensional memory array 120 and peripheral circuit 130 lamination are arranged on substrate 110.Peripheral circuit 130 comprises patterned metal layer 131 and contact structures (contact structure) 133, and contact structures 133 are electrically connected at patterned metal layer 131.Conduction connecting structure 140 is electrically connected at patterned metal layer 131, and three-dimensional memory array 120 is electrically connected to peripheral circuit 130 via conduction connecting structure 140.In the present embodiment, three-dimensional memory array 120 is stacked on peripheral circuit 130, and storage device 100 has the structure that array is positioned at (array-on-periphery, AOP) on peripheral circuit.
In one embodiment, be different from peripheral circuit 130 originally for being connected to contact point (contact) and the metal bracing wire (metal routing) of each transistor 135, patterned metal layer 131 is such as the extra metal bracing wire of one deck, contact structures 133 are such as extra contact points, be exclusively used in and be connected to conduction connecting structure 140, to reach the object being electrically connected three-dimensional memory array 120 and peripheral circuit 130.
In storage device 100, three-dimensional memory array 120 is stacked on peripheral circuit 130, and both are electrically connected via vertical conduction connecting structure 140.Compared to structure storage array and peripheral circuit were arranged on the same plane of chip in the past, according to embodiments of the invention, by the structure of three-dimensional memory array 120 with peripheral circuit 130 vertical stack on one chip, the area that element occupies at chip surface significantly can be reduced, and then effectively reach the effect of chip size micro.For example, when three-dimensional memory array 120 and the peripheral circuit 130 shared area of plane out of the ordinary about equal time, by both vertical stack on one chip, the area that element (mainly three-dimensional memory array 120 and peripheral circuit 130) occupies at chip surface significantly can be reduced up to about 50%.
In one embodiment, as shown in Figure 1, conduction connecting structure 140 such as has vertical column structure, and the length-width ratio (aspect ratio) of conduction connecting structure 140 is such as greater than 2, is preferably such as greater than 10.
As shown in Figure 2, peripheral circuit 130 more comprises multiple transistor 135, and transistor 135 is electrically connected at patterned metal layer 131 via contact structures 133.In embodiment, transistor 135 is such as metal oxide semiconductor device (metal oxide semiconductor, MOS).
In embodiment, as shown in Fig. 1 ~ Fig. 2, be comprise one deck patterned metal layer 131 for peripheral circuit 130.During right practical application, also visual application feature increases the quantity of patterned metal layer 131, in order to be electrically connected contact structures 133 and conduction connecting structure 140, and the also visual application feature increase of the quantity of contact structures 133, be not limited with aforesaid single layer patterning metal level 131 and contact structures 133.
In embodiment, patterned metal layer 131 and contact structures 133 adopt low sheet resistance values (sheetresistance) and resistant to elevated temperatures material.For example, the material of patterned metal layer 131 and contact structures 133 can comprise independently respectively aluminium, copper, tungsten or metal silicide at least one of them.Material can affect the temperature range of subsequent technique.For example, when the material of patterned metal layer 131 and contact structures 133 is tungsten, last part technology (back end of line, BEOL) temperature can be born to about 800 DEG C, when the material of patterned metal layer 131 and contact structures 133 be aluminium or copper time, the temperature of last part technology need lower than about 400 DEG C, but aluminium or copper have higher conductivity.
As shown in Fig. 1 ~ Fig. 2, three-dimensional memory array 120 comprises at least one metal level ML1, and conduction connecting structure 140 is electrically connected at metal level ML1.In embodiment, as shown in Figure 1, three-dimensional memory array 120 can comprise three-layer metal layer ML1, ML2 and ML3, conduction connecting structure 140 is electrically connected at metal level ML1, conduction connecting structure 140 ' is electrically connected at metal level ML3, and three-dimensional memory array 120 also can sequentially be electrically connected at patterned metal layer 131, contact structures 133 to peripheral circuit 130 via conduction connecting structure 140 '.
In one embodiment, three-dimensional memory array 120 is such as three-dimensional perpendicular grid NAND gate memory (3Dvevtical gate NAND flash memory), metal level ML1 is such as wordline, and metal level ML2 is such as that string selects line, and metal level ML3 is such as bit line.During right practical application, the kind of three-dimensional memory array 120, metal layer numbers are also looked application feature and are done suitably to select, and are not limited with the kind listed by aforesaid embodiment and number.
As shown in Fig. 1 ~ Fig. 2, in the present embodiment, three-dimensional memory array 120 is stacked on peripheral circuit 130, and patterned metal layer 131 is arranged between three-dimensional memory array 120 and peripheral circuit 130.In embodiment, storage device 100 more comprises insulating barrier 150, and insulating barrier 150 to be arranged between three-dimensional memory array 120 and peripheral circuit 130 and coated patterned metal layer 131.The surface that insulating barrier 150 is adjacent to three-dimensional memory array 120 is flat surfaces.In embodiment, insulating barrier 150 is such as interlayer dielectric layer (interlayer dielectric).
Please refer to Fig. 3 ~ Fig. 4, Fig. 3 illustrates the stereogram of storage device 200 according to another embodiment of the present invention, and Fig. 4 illustrates the end view of storage device 200 according to another embodiment of the present invention.From storage device 100 difference of previous embodiment, the storage device 200 of the present embodiment is that the stacked system of three-dimensional memory array and peripheral circuit is different.In the present embodiment, peripheral circuit 130 is stacked on three-dimensional memory array 120, and storage device 200 has the structure that peripheral circuit is positioned at (periphery onarray, POA) on array.
Similarly, in storage device 200, peripheral circuit 130 is stacked on three-dimensional memory array 120, and both are electrically connected via vertical conduction connecting structure 340.According to embodiments of the invention, the structure of vertical stack on one chip by three-dimensional memory array and peripheral circuit, can significantly reduce about 50% by the area that element occupies at chip surface, and then effectively reach the effect of chip size micro.
In embodiment, as shown in Figure 4, peripheral circuit 130 such as comprises multi-layered patterned metal level 131,131a, 131b and multilayer contact structure 133,133a, 133b, the transistor 135 of peripheral circuit 130 is electrically connected to conduction connecting structure 340 via patterned metal layer 131,131a, 131b and contact structures 133,133a, 133b, is electrically connected to three-dimensional memory array 120 further.
As shown in Fig. 3 ~ Fig. 4, in the present embodiment, peripheral circuit 130 is stacked on three-dimensional memory array 120.In one embodiment, as shown in Figure 4, storage device 200 more comprises epitaxial silicon (epi-Si) layer 360, and silicon epitaxial layers 360 is arranged between three-dimensional memory array 120 and peripheral circuit 130.The surface that silicon epitaxial layers 360 is adjacent to peripheral circuit 130 is flat surfaces.In another embodiment, storage device 200 also more can comprise silicon-on-insulator (SOI) layer (not being illustrated in figure), and silicon-on-insulator layer is arranged between three-dimensional memory array 120 and peripheral circuit 130.The surface that silicon-on-insulator layer is adjacent to peripheral circuit 130 is flat surfaces.
Fig. 5 illustrates the simplification stereogram of conduction connecting structure according to an embodiment of the invention.Conduction connecting structure can be electrically connected three-dimensional memory array 120 and peripheral circuit 130 via the outside of three-dimensional memory array 120 or by the inside of three-dimensional memory array 120.
In one embodiment, as shown in Figure 5, perforate conduction connecting structure 540 can be made between the chip 580 in three-dimensional memory array 120.Although the design of array must be coordinated to plan the space of perforate from the internal production conduction connecting structure 540 of three-dimensional memory array 120, technique may more complicated, but via array internal production conduction connecting structure 540, make cabling shorter, and then make the RC delay of wordline meeting shorter.As shown in Figure 5, one end of conduction connecting structure 540 can be connected directly to the original metal bracing wire for being connected to each transistor 135 of peripheral circuit 130, and the other end is connected to the metal level ML of three-dimensional memory array 120.
In another embodiment, as shown in Figure 5, conduction connecting structure 540 ' can be made in the outside of three-dimensional memory array 120.Even so one, cabling can be long, and the RC of wordline postpones can be long, but technique relatively can be simply many, and process yields also can promote.As shown in Figure 5, one end of conduction connecting structure 540 ' is connected to patterned metal layer 131 and contact structures 133, and the other end is connected to the metal level ML of three-dimensional memory array 120.For example, as shown in Figure 1, in storage device 100, conduction connecting structure 140 and 140 ' is made in the outside of three-dimensional memory array 120.
Be below the manufacture method of a kind of storage device proposing embodiment, so those steps are only the use illustrated, and are not used to limit the present invention.Have usually know the knowledgeable when can according to reality implement aspect need those steps are modified or are changed.It is noted that some elements in partial view illustrate in a perspective fashion, part secondary element omits, with clearer expression the present invention.
Fig. 6 A to Fig. 6 C illustrates the manufacture method schematic diagram of the storage device 100 according to one embodiment of the invention.Please refer to Fig. 6 A to Fig. 6 C.
As shown in Fig. 6 A to Fig. 6 B, provide substrate 110, and form peripheral circuit 130 on substrate 110.In embodiment, the step forming peripheral circuit 130 such as comprises formation patterned metal layer 131, contact structures 133 and transistor 135.Contact structures 133 are electrically connected at patterned metal layer 131, and transistor 135 is electrically connected at patterned metal layer 131 via contact structures 133.
Then, as shown in Figure 6B, insulating barrier 150 is set on peripheral circuit 130 and coated patterned metal layer 131.In embodiment, such as, be first form metal oxide layer 150 on patterned metal layer 131, the then surface of planarization insulating layer 150.The step of the planarization on the surface of this insulating barrier is crucial, and the surface of planarization is conducive to the carrying out of follow-up laminating step.
Then, as shown in Figure 6 C, monolithic three-dimensional storage array 120 on peripheral circuit 130, form conduction connecting structure 140 and carry out the making (not illustrating) of last part technology.In embodiment, three-dimensional memory array 120 is formed on the surface of the planarization of insulating barrier 150.In other words, patterned metal layer 131 and insulating barrier 150 are all between three-dimensional memory array 120 and peripheral circuit 130.So far, the storage device 100 shown in Fig. 6 C (Fig. 2) is formed at.
In embodiment, be such as after manufacturing segment process time, namely after the surface of planarization insulating layer 150, the metal connecting layer (not illustrating) making multiple raceway groove or patterning in the lump in oxide layer (being such as insulating barrier 150) is connected to the patterned metal layer 131 of peripheral circuit 130, then insert electric conducting material in channels again, just form conduction connecting structure 140.Conduction connecting structure 140 is electrically connected at patterned metal layer 131, and three-dimensional memory array 120 comprises at least one metal level ML1, and conduction connecting structure 140 is electrically connected at metal level ML1.Three-dimensional memory array 120 is electrically connected to peripheral circuit 130 via vertical conduction connecting structure 140.
Fig. 7 A to Fig. 7 C illustrates the manufacture method schematic diagram of the storage device 200 according to another embodiment of the present invention.Please refer to Fig. 7 A to Fig. 7 C.
As shown in Figure 7 A, provide substrate 110, and form three-dimensional memory array 120 on substrate 110.Three-dimensional memory array 120 comprises at least one metal level ML1, and metal level ML1 is for being electrically connected at conduction connecting structure made in subsequent technique.
Then, as shown in Figure 7 B, silicon epitaxial layers 360 is set on three-dimensional memory array 120.In another embodiment, a silicon-on-insulator layer (not illustrating) also can be set on three-dimensional memory array 120.The setting of this silicon epitaxial layers 360 or silicon-on-insulator layer is crucial, thus, follow-up peripheral circuit 130 can directly be formed on silicon epitaxial layers 360 or silicon-on-insulator layer, therefore existing technique lamination peripheral circuit 130 can be adopted, and the technique of lamination peripheral circuit 130 can not produce incompatible problem with the technique of existing three-dimensional memory array 120, thus can improve the technological feasibility of whole storage device 200.
Then, as seen in figure 7 c, lamination peripheral circuit 130 on three-dimensional memory array 120, form conduction connecting structure 140 and carry out the making (not illustrating) of last part technology.In embodiment, be such as after manufacturing segment process time, the metal connecting layer making multiple raceway groove or patterning in the lump in oxide layer is connected to the metal level of three-dimensional memory array 120 (being such as metal level ML1), then insert electric conducting material in channels again, just form conduction connecting structure 140.In embodiment, the step of lamination peripheral circuit 130 such as comprises formation patterned metal layer 131, contact structures 133 and transistor 135.Contact structures 133 are electrically connected at patterned metal layer 131, and transistor 135 is electrically connected at patterned metal layer 131 via contact structures 133.Conduction connecting structure 140 is electrically connected at patterned metal layer 131 and metal level ML1.Three-dimensional memory array 120 is electrically connected to peripheral circuit 130 via vertical conduction connecting structure 140.In embodiment, peripheral circuit 130 is formed on silicon epitaxial layers 360 or silicon-on-insulator layer.In other words, silicon epitaxial layers 360 or silicon-on-insulator layer are between three-dimensional memory array 120 and peripheral circuit 130.So far, the storage device 200 shown in Fig. 7 C (Fig. 4) is formed at.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.
Claims (10)
1. a storage device, comprising:
One substrate;
One three-dimensional memory array (3Dmemory array) and a peripheral circuit (periphery circuit) lamination are arranged on this substrate, and this peripheral circuit comprises:
One patterned metal layer; And
One contact structures (contact structure), are electrically connected at this patterned metal layer; And
One conduction connecting structure (conductive connection structure), be electrically connected at this patterned metal layer, wherein this three-dimensional memory array is electrically connected to this peripheral circuit via this conduction connecting structure.
2. storage device according to claim 1, wherein this three-dimensional memory array is stacked on this peripheral circuit.
3. storage device according to claim 1, wherein this peripheral circuit is stacked on this three-dimensional memory array.
4. storage device according to claim 3, more comprises:
One epitaxial silicon (epi-Si) layer or a silicon-on-insulator (SOI) layer, be arranged between this three-dimensional memory array and this peripheral circuit.
5. storage device according to claim 1, wherein the length-width ratio (aspect ratio) of this conduction connecting structure is greater than 2.
6. a manufacture method for storage device, comprising:
One substrate is provided;
Arrange a three-dimensional memory array and a peripheral circuit is stacked on this substrate, wherein this peripheral circuit comprises:
One patterned metal layer; And
One contact structures, are electrically connected at this patterned metal layer; And
Form a conduction connecting structure, be electrically connected at this patterned metal layer, wherein this three-dimensional memory array is electrically connected to this peripheral circuit via this conduction connecting structure.
7. the manufacture method of storage device according to claim 6, wherein this peripheral circuit more comprises multiple transistor, and those transistors are electrically connected at this patterned metal layer via these contact structures.
8. the manufacture method of storage device according to claim 6, wherein arranges the step that this three-dimensional memory array and this peripheral circuit be stacked on this substrate and comprises:
Form this peripheral circuit on this substrate; And
This three-dimensional memory array of lamination is on this peripheral circuit.
9. the manufacture method of storage device according to claim 8, more comprises:
One insulating barrier is set between this three-dimensional memory array and this peripheral circuit and this patterned metal layer coated.
10. the manufacture method of storage device according to claim 6, wherein arranges the step that this three-dimensional memory array and this peripheral circuit be stacked on this substrate and comprises:
Form this three-dimensional memory array on this substrate; And
This peripheral circuit of lamination is on this three-dimensional memory array.
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| CN201310382680.3A CN104425498A (en) | 2013-08-28 | 2013-08-28 | Storage apparatus and manufacture method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310382680.3A CN104425498A (en) | 2013-08-28 | 2013-08-28 | Storage apparatus and manufacture method thereof |
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| CN104425498A true CN104425498A (en) | 2015-03-18 |
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| CN201310382680.3A Pending CN104425498A (en) | 2013-08-28 | 2013-08-28 | Storage apparatus and manufacture method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273450A (en) * | 2018-09-04 | 2019-01-25 | 长江存储科技有限责任公司 | The manufacturing method of three-dimensional storage |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5835396A (en) * | 1996-10-17 | 1998-11-10 | Zhang; Guobiao | Three-dimensional read-only memory |
| CN101312199A (en) * | 2007-05-21 | 2008-11-26 | 国际商业机器公司 | Multiple port register file cell and manufacturing method thereof |
| US20100314711A1 (en) * | 2008-08-19 | 2010-12-16 | International Business Machines Corporation | 3d integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer |
| WO2013078069A1 (en) * | 2011-11-21 | 2013-05-30 | SanDisk Technologies, Inc. | 3d non-volatile memory with metal silicide interconnect |
| US20130148402A1 (en) * | 2011-12-13 | 2013-06-13 | Meng-Fan Chang | Control scheme for 3d memory ic |
-
2013
- 2013-08-28 CN CN201310382680.3A patent/CN104425498A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5835396A (en) * | 1996-10-17 | 1998-11-10 | Zhang; Guobiao | Three-dimensional read-only memory |
| CN101312199A (en) * | 2007-05-21 | 2008-11-26 | 国际商业机器公司 | Multiple port register file cell and manufacturing method thereof |
| US20100314711A1 (en) * | 2008-08-19 | 2010-12-16 | International Business Machines Corporation | 3d integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer |
| WO2013078069A1 (en) * | 2011-11-21 | 2013-05-30 | SanDisk Technologies, Inc. | 3d non-volatile memory with metal silicide interconnect |
| US20130148402A1 (en) * | 2011-12-13 | 2013-06-13 | Meng-Fan Chang | Control scheme for 3d memory ic |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273450A (en) * | 2018-09-04 | 2019-01-25 | 长江存储科技有限责任公司 | The manufacturing method of three-dimensional storage |
| CN109273450B (en) * | 2018-09-04 | 2020-06-23 | 长江存储科技有限责任公司 | Method for manufacturing three-dimensional memory |
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Application publication date: 20150318 |