CN104575619A - Restoration method of DRAM (Dynamic Random Access Memory) chip - Google Patents

Abstract

The invention relates to a restoration method of a DRAM (Dynamic Random Access Memory) chip. The restoration method comprises the following steps of: adopting a method for expanding virtual address bits, loading non-2n (n is equal to an integer) addresses into the expanded virtual address bits, and using the virtual address bits to carry out identification on the boundaries of the chip designing addresses. The restoration method has the advantages that the need of chip designing persons is really reflected, so that a series of problems related to positioning of the address boundaries in chip testing are solved; and since the two expanded virtual addresses can not generate any influence on the X address of the original m-bit chip, the normal addressing of the chip is not influenced and further correct access for the address of the test chip is guaranteed.

Description

A kind of restorative procedure of dram chip

Technical field

The present invention relates to a kind of restorative procedure of dram chip.

Background technology

When the design of dram chip is no longer with traditional 2 ⁿwhen (n equals integer) individual number of addresses is plan boundary, testing tool cannot position the plan boundary of chip, and existing solution is the true address border of abandoning chip, still adopts 2 ⁿindividual number of addresses is the way on border.This way can not reflect the demand of chip designer really, and then locate relevant series of problems to address boundary in initiation chip testing, such as: dram chip recovery scenario can not be implemented, the write of topology can not ensure the accuracy etc. of chip testing result.

As shown in Figure 1,1.1 in Fig. 1 gives chip designer the recovery scenario provided, and suppose that this DRAM has X address, m (m equals integer) position, namely the X address number of this chip is 2 ^mindividual, and 2 ^mindividual address is evenly distributed in 3 independent restoring areas (area 0, region 1 and region 2), and therefore the X number of addresses of each independent restoring area is 2 ^marticle/3, one, redundancy also with identical rule by trisection, and each decile independently can repair the fail address in this region.Suppose that the test result of this chip is as shown in 1.2 parts in Fig. 1, each own failpoint (characterizing with x) in each region.According to the restorative procedure that chip designer provides, this chip can be repaired, and will be embodied in the dose rate of wafer.But, due to 2 ^m/ 3 be not equal to 2 integral multiple, therefore traditional method of testing cannot look for out suitable chip address by chip trisection in the X direction in the X address, m position of chip, as shown in 1.3 parts, it gives traditional recovery scenario of chip testing, the program abandons the division of the X-direction to chip, and the design concept of independent restoring area has not been existed.Therefore when the test result of chip is as shown in 1.2 parts of Fig. 1, this chip cannot be repaired, can not by calculation in the dose rate of wafer.This way does not have the real demand of reaction designing personnel, result in the increase of production cost.

Summary of the invention

In order to solve existing employing 2 ⁿindividual number of addresses is the demand that the way on border truly cannot reflect chip designer, and the write of topology can not ensure the technical matters of the robustness of chip testing result to the invention provides a kind of method finding dram chip address boundary.

Technical solution of the present invention is:

A restorative procedure for dram chip, its special character is: comprise the following steps,

1] on the X address, chip m position that will repair, two virtual address spaces are expanded;

2] the X address will repaired is divided into odd number restoring area, and redundant storage unit is divided into odd number storage unit with same rule by correspondence; Storage unit and restoring area one_to_one corresponding;

3] two virtual addresses expanded are encoded, find out the reparation border of each restoring area;

4] the reparation border of each storage unit to corresponding restoring area is utilized to modify.

Above-mentioned steps 2] X address is divided into three restoring areas.

The advantage that the present invention has:

1, the present invention adopts the way expanding virtual address space, by non-2 ⁿ(n equals integer) individual number of addresses loads in the virtual address space expanded, and carries out the mark of chip design address boundary with virtual address space; The method reflects the demand of chip designer really, makes to locate relevant series of problems to address boundary in chip testing and is solved.

2, the present invention due to expand two virtual address spaces can not produce any impact to chip X address, original m position, therefore, the normal addressing of chip is unaffected, and then ensure that the correct access of test chip address.

Accompanying drawing explanation

Fig. 1 is traditional chip restorative procedure schematic diagram;

Fig. 2 is chip restorative procedure schematic diagram provided by the present invention.

Embodiment

For the reparation of dram chip, illustrate address boundary be positioned at DRAM repair in application, be trisection citing.

As shown in Figure 2, give the recovery scenario that chip designer provides in a, suppose that this DRAM has X address, m (m equals integer) position, namely the X address number of this chip is 2 ^mindividual, and 2 ^mindividual address is evenly distributed in 3 independent restoring areas (area 0, region 1 and region 2), and therefore the X number of addresses of each independent restoring area is 2 ^m/ 3, article one, redundant storage unit is also divided into storage unit with identical rule by third-class, and the storage unit of each decile independently can repair this fail address to a restoring area (utilizing storage redundancy unit to repair disabling unit at respective reparation border inner).Shown in c part, for the situation of chip trisection in the X direction, on the basis, X address, m position of chip, expand two virtual address Xm+2 and Xm+1 and it has been encoded, having ensured the uniqueness of the coded combination of these two virtual addresses at these three independent restoring areas simultaneously.These two virtual addresses will be introduced in the test of chip, for positioning the trisection border in chip X-direction, when chip is repaired, the address boundary of chip can be found out accurately, the test bad point of the b part in correct reparation Fig. 2, avoids the problem caused by traditional recovery scenario.Because two that newly produce virtual X addresses can not produce any impact to chip X address, original m position, therefore, the normal addressing of chip is unaffected, and then ensure that the correct access of test chip address.

Claims (2)

1. a restorative procedure for dram chip, is characterized in that: comprise the following steps,

1] on the X address, chip m position that will repair, two virtual address spaces are expanded;

2] the X address will repaired is divided into odd number restoring area, and redundant storage unit is divided into odd number storage unit with same rule by correspondence; Storage unit and restoring area one_to_one corresponding;

3] two virtual addresses expanded are encoded, find out the reparation border of each restoring area;

4] the reparation border of each storage unit to corresponding restoring area is utilized to modify.

2. the restorative procedure of dram chip according to claim 1, is characterized in that: described step 2] X address is divided into three restoring areas.