CN104659102A - SOI (silicon on insulator) voltage-resistant structure provided with partial composite buried layer - Google Patents
SOI (silicon on insulator) voltage-resistant structure provided with partial composite buried layer Download PDFInfo
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- CN104659102A CN104659102A CN201510076359.1A CN201510076359A CN104659102A CN 104659102 A CN104659102 A CN 104659102A CN 201510076359 A CN201510076359 A CN 201510076359A CN 104659102 A CN104659102 A CN 104659102A
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Abstract
The invention discloses an SOI (silicon on insulator) voltage-resistant structure provided with a partial composite buried layer. The structure comprises a P/N substrate 1, a partial composite oxygen buried layer 4 arranged on the P/N substrate and an active top silicon layer 2 arranged on the partial composite oxygen buried layer, wherein the partial composite oxygen buried layer 4 comprises an oxygen buried layer 3 and a composite buried layer which are arranged in parallel, and the composite buried layer comprises a bottom oxygen buried layer 7 arranged on the P/N substrate, a middle polycrystalline silicon layer 6 arranged on the bottom oxygen buried layer and a first oxygen buried layer 5 arranged on the middle polycrystalline silicon layer. On the basis of a conventional SOI voltage-resistant structure, part of the oxygen buried layer is replaced by a composite buried layer structure of first oxygen buried layer-middle polycrystalline silicon layer-bottom oxygen buried layer. New electric field peaks appear in interface positions of the composite buried layer and the oxygen buried layer in an off state, so that the breakdown voltage is higher, the concentration of impurities in the active top silicon layer conforming to the RESURF (reduced surface field) condition is higher, and the communication resistance is lower in an on state. Besides, the heat conductivity of polycrystalline silicon is higher than that of silicon oxide, so that the heat-conducting property of the structure is better.
Description
Technical field
The present invention relates to a kind of semiconductor power device pressure-resistance structure, particularly a kind of SOI pressure-resistance structure with part compound buried regions.
Background technology
Isolate supports (Semiconductor On Insulator and SOI) is the semiconductor substrate materials of the new structure grown up in the eighties in last century, and the design feature of its uniqueness overcomes the deficiency of many conventional body silicon materials.Similar with body Si power device, the contradiction between the puncture voltage of preparation power device on soi substrates and conducting resistance is also one of focal issue of paying close attention to of scholars.Simultaneously due to the existence of oxygen buried layer, SOI device self-heating effect is comparatively serious, also causes extensive concern.
Drawing RESURF in autologous silicon (Reduced SURface Field reduces surface field) technology is one of wherein the most conventional technology.Fig. 1 is conventional single RESURF (Single-RESRUF) SOI n raceway groove LDMOS device structure, and wherein 1 is P/N substrate, and 2 is n-active top silicon layer, 3 is oxygen buried layer, 8 is underlayer electrode, and 9 is drain electrode, and 10 is source electrode, 11 is field oxygen, 12 Wei Lou N+ districts, 13 Wei Yuan N+ districts, 14 Wei Yuan P+ districts, 15 is P-body district, and 16 is gate electrode.This structure is when drift region all exhausts, and depletion region, drift region electric field and substrate depletion region electric field are cancelled out each other, and reduce surface field, makes breakdown point transfer in body by PN junction surface, reaches the effect improving puncture voltage and reduce conduction resistance.According to RESURF technology, the drift region concentration of optimization is relevant with the thickness of active top silicon layer 2 and oxygen buried layer 3, and the timing of active top silicon layer 2 thickness one, the drift region concentration of optimization reduces along with the increase of oxygen buried layer 3 thickness.The visible list of references of related content: Y.S.Huang, B.J.Baliga, Extension of resurf Principle to dielectrically isolated power devices, Proceeding of IEEEISPSD ' 91,1991, pp.27-30.On this basis, two RESURF (Double-RESURF) structure is also used in the middle of the power device of SOI substrate.Compared with single RESURF, two RESURF adds a P-top layer on surface, drift region, and this P-top layer assisted depletion N-drift region, makes N-drift doping concentration improve further when meeting RESURF condition, thus obtains less conducting resistance.The visible list of references of related content: R.P.Zingg, I.Weijland, H.V.Zwol, et al, 850V DMOS-switch in silicon-on insulator with specific Ron 13 Ω-mm2, IEEE International SOIConference, 2000, pp.62-63.In addition, Triple-RESURF technology is also introduced in SOI power device, and this technology P layer is imbedded active top layer silicon inside, makes its assisted depletion N-drift region effect more obvious, obtain less resistance.The visible list of references of related content: X.R.Hu, B.Zhang, X.R.Luo, and Z.J.Li, " Analytical models for theelectric field distributions and breakdown voltage of triple Resurf SOI LDMOS, " Solid-StateElectron., vol.69, pp.89-93, Mar.2012.
Improve the withstand voltage aspect of SOI device, strengthen buried regions electric field and cause extensive concern in recent years, such technology by adopting ultra-thin top layer silicon, adopting low-K dielectric buried regions and strengthening buried regions electric field in the mode of buried regions surface introducing interface charge, thus improves the withstand voltage of whole device.The visible list of references of related content: Bo Zhang, Zhaoji Li, Shengdong Hu, and Xiaorong Luo.Field enhancement for dielectric layer of high-vltage devices on silicon on insulator.IEEE Trans.Electron Devices 2009,56 (10): 2327-2334.As shown in Figure 2, wherein 1 is P/N substrate to ultra-thin silicon layer device structure, and 2 is the active top layer silicon of n-, and 3 is oxygen buried layer, and 8 is underlayer electrode, 9 is drain electrode, and 10 is source electrode, and 11 is field oxygen, 12 Wei Lou N+ districts, 13 Wei Yuan N+ districts, 14 Wei Yuan P+ districts, 15 is P-body district, and 16 is gate electrode.This structure adopts variety lateral doping technical optimization electric field in ultra-thin active top layer silicon 2, utilizes the high critical electric field of ultra-thin silicon layer to strengthen the electric field in oxygen buried layer 3, obtains high withstand voltage.The visible list of references of related content: S.Merchant, E.Arnold, H.Baumgart, et al.Realization of high breakdown voltage (>700V) in thin SOI device.In:Proc ISPSD, 1991, pp31-35.Low-K dielectric buried regions device as shown in Figure 3.Wherein 1 is P/N substrate, and 2 is the active top layer silicon of n-, and 3 is oxygen buried layer, and 8 is underlayer electrode, and 9 is drain electrode, and 10 is source electrode, and 11 is field oxygen, 12 Wei Lou N+ districts, 13 Wei Yuan N+ districts, 14 Wei Yuan P+ districts, and 15 is P-body district, and 16 is gate electrode, and 17 is low-K dielectric.Oxygen buried layer low-K dielectric 17 below drain terminal replaces by this structure, thus improves buried regions electric field and device withstand voltage, but low-K dielectric SOI and the compatible aspect of stand CMOS run into challenge.Related content sees reference document: A new structure and its analytical model for the electric field andbreakdown voltage of SOI high voltage device with variable-k dielectric buried layer, Solid-StateElectronics, 2007,51:493-99.Charge type SOI high tension apparatus aspect, US Patent No. 6495864 proposes media slot buried structure, as shown in Figure 4, wherein 1 is P/N substrate, and 2 is the active top layer silicon of n-, and 3 is oxygen buried layer, 8 is underlayer electrode, and 9 is drain electrode, and 10 is source electrode, 11 is field oxygen, 12 Wei Lou N+ districts, 13 Wei Yuan N+ districts, 14 Wei Yuan P+ districts, 15 is P-body district, and 16 is gate electrode, and 18 is oxidation trough.The interception of this devices use oxidation trough 18 pairs of transverse electric fields, at oxygen buried layer 3 surface accumulation inversion charge, utilizes electric charge to strengthen oxygen buried layer 3 internal electric field, thus obtains high puncture voltage.Related content sees reference document: United States Patent (USP): Dieter Silber, Wolfgang Wondrak, Robert Plikat, Patent, 6495864, Dec.17,2002.
In addition, partial SOI (partial-SOI, PSOI) technology is also suggested, as shown in Figure 5, wherein 1 is P/N substrate, and 2 is the active top layer silicon of n-, 3 is oxygen buried layer, and 8 is underlayer electrode, and 9 is drain electrode, 10 is source electrode, and 11 is field oxygen, 12 Wei Lou N+ districts, 13 Wei Yuan N+ districts, 14 Wei Yuan P+ districts, 15 is P-body district, 16 is gate electrode, and 19 is silicon window.It is withstand voltage that this structure makes substrate participate in, thus obtain high withstand voltage, simultaneously because the existence of silicon window 19 alleviates natural effect.Related content sees reference document: R, Tadikonda etc., Realizing high breakdown voltage (>600V) in partial SOItechnology, Solid State Electron., 2004, pp1655-1660.
At present, how to obtain high puncture voltage, low conducting resistance, preferably thermal effect remain the study hotspot in SOI power devices field.
Summary of the invention
In view of this, the present invention proposes a kind of SOI pressure-resistance structure with part compound buried regions, this kind of structure solves the low problem of SOI power device withstand voltage, to go forward side by side the conducting resistance of the low SOI power device of a step-down, alleviate contradictory problems between device electric breakdown strength and conducting resistance, and better thermal characteristics can be obtained.
The object of the invention is by such technical scheme realize, a kind of SOI pressure-resistance structure with part compound buried regions, the active top silicon layer 2 comprising P/N substrate 1, be arranged on the part compound oxygen buried layer 4 on P/N substrate and be arranged on part compound oxygen buried layer, described part compound oxygen buried layer 4 comprises the oxygen buried layer 3 and compound buried regions that are set up in parallel, the first floor oxygen buried layer 5 that described compound buried regions comprises the bottom oxygen buried layer 7 be arranged on P/N substrate, arranges the intermediate polysilicon layer 6 on bottom oxygen buried layer and be arranged on intermediate polysilicon layer.
Owing to have employed technique scheme, the present invention has following advantage:
A part for oxygen buried layer, on the SOI pressure-resistance structure basis of routine, is replaced with the compound buried structure of " first floor oxide layer-intermediate polysilicon layer-bottom oxide layer " by the present invention.First, when device OFF state is withstand voltage, compound buried regions and oxygen buried layer interface location there will be new electric field peak, thus modulate the Electric Field Distribution in whole active top layer silicon, make it more optimize, thus obtain high puncture voltage.Secondly, because the first floor oxide layer in compound buried regions is thinner than oxygen buried layer, by RESURF principle, optimum corresponding to it active top layer silicon doping content is higher, thus can mix higher impurity concentration in the active top layer silicon in pressure-resistance structure proposed by the invention, thus reduce the ON state conducting resistance of this structure.Finally, because the heat conductivility of polysilicon is far due to silica, due to the existence of polycrystalline silicon material in buried regions in pressure-resistance structure thus proposed by the invention, make its heat conductivility more excellent.
Accompanying drawing explanation
In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail, wherein:
Fig. 1 is SOI mono-RESURF device architecture schematic diagram;
Fig. 2 is the SOI device structural representation of ultra-thin active top layer silicon technology;
Fig. 3 is the structure of SOI power device schematic diagram adopting low-K dielectric technology;
Fig. 4 is the structure of SOI power device schematic diagram adopting oxidation trough technology;
Fig. 5 is partial SOI device architecture schematic diagram;
Fig. 6 is a kind of SOI pressure-resistance structure with part compound buried regions that the present invention proposes;
Fig. 7 is a kind of n raceway groove LDMOS device structural representation with the SOI pressure-resistance structure of part compound buried regions proposed based on the present invention;
Fig. 8 is a kind of n raceway groove LDMOS device with the SOI pressure-resistance structure of part compound buried regions proposed based on the present invention equipotential lines distribution map when puncturing;
Fig. 9 is the mono-RESURF device of conventional SOI equipotential lines distribution map when puncturing;
Figure 10 is device surface distribution map of the electric field when puncturing based on the LDMOS of pressure-resistance structure proposed by the invention and conventional LDMOS;
Figure 11 is based on the I-V relation that drains when the LDMOS of pressure-resistance structure proposed by the invention and conventional LDMOS ON state;
Figure 12 is LDMOS based on pressure-resistance structure proposed by the invention and the surface temperature distribution of conventional LDMOS when power consumption is 1mW/ μm;
Wherein 1 is P/N substrate, and 2 is active top silicon layer, and 3 is oxygen buried layer, and 4 is compound buried regions, 5 is first floor oxygen buried layer, and 6 is intermediate polysilicon layer, and 7 is bottom oxygen buried layer, 8 is underlayer electrode, and 9 is drain electrode, and 10 is source electrode, 11 is field oxygen, 12 Wei Lou N+ districts, 13 Wei Yuan N+ districts, 14 Wei Yuan P+ districts, 15 is P-body district, and 16 is gate electrode, 17 is low-K dielectric, and 18 is oxidation trough, and 19 is silicon window.
Embodiment
Below with reference to accompanying drawing, the preferred embodiments of the present invention are described in detail; Should be appreciated that preferred embodiment only in order to the present invention is described, instead of in order to limit the scope of the invention.
Fig. 6 is a kind of SOI pressure-resistance structure with part compound buried regions that the present invention proposes, comprise the P/N substrate, active top layer silicon 2, the part compound oxygen buried layer that arrange from bottom to top, part compound oxygen buried layer comprises the oxygen buried layer 3 and compound buried regions 4 that are set up in parallel, and wherein compound buried regions 4 comprises from the first floor oxide layer 5 of upper and upper setting, intermediate polysilicon layer 6 and bottom oxide layer 7.The doping module that described active top layer silicon 2 can distribute different, for power MOS (Metal Oxide Semiconductor) device, power diode device and power IGBT device.Described active top layer silicon 2 is one or more in Si, SiC, GaN semi-conducting material.Described oxygen buried layer 3 is SiO
2and/or Si
3n
4medium.Described intermediate polysilicon layer 6 adulterates for N-type and/or P type doping and/or zero is adulterated.
Operation principle of the present invention, with a kind of n raceway groove LDMOS device structure with the SOI pressure-resistance structure of part compound buried regions proposed based on the present invention, is described in detail to the working mechanism of proposed new pressure-resistance structure.Fig. 7 is a kind of n raceway groove LDMOS device structural representation with the SOI pressure-resistance structure of part compound buried regions proposed based on the present invention.Wherein 1 is P/N substrate, and 2 is active top silicon layer, and 3 is oxygen buried layer, 4 is compound buried regions (it is made up of 5 first floor oxygen buried layers, 6 intermediate polysilicon layers and 7 bottom oxygen buried layers), 8 is underlayer electrode, and 9 is drain electrode, and 10 is source electrode, 11 is field oxygen, 12 Wei Lou N+ districts, 13 Wei Yuan N+ districts, 14 Wei Yuan P+ districts, 15 is P-body district, and 16 is gate electrode.First, when device OFF state is withstand voltage, compound buried regions and oxygen buried layer interface location there will be new electric field peak, thus modulate the Electric Field Distribution in whole active top layer silicon, make it more optimize, thus obtain high puncture voltage.
Fig. 8 corresponds to the equipotential lines distribution of the mono-RESURF device of conventional SOI shown in Fig. 1 when puncturing, and Fig. 9 corresponds to the equipotential lines distribution of the n raceway groove LDMOS device with the SOI pressure-resistance structure of part compound buried regions shown in Fig. 7 when puncturing.The top layer active silicon layer thickness of two kinds of devices and length, oxygen buried layer thickness are all identical, there is concentrating of equipotential lines at compound buried regions and oxygen buried layer interface location in the visible SOI device based on pressure-resistance structure proposed by the invention, and then the electromotive force optimized in whole active top layer silicon and Electric Field Distribution.
Figure 10 is device surface distribution map of the electric field when puncturing based on the LDMOS of pressure-resistance structure proposed by the invention and conventional LDMOS, visible, there is obvious electric field peak in the lateral attitude of pressure-resistance structure proposed by the invention corresponding to compound buried regions level oxygen buried layer interface, thus the puncture voltage based on the LDMOS of pressure-resistance structure proposed by the invention is increased to 467V by the 350V of conventional LDMOS, and amplification reaches 33.4%.Secondly, because the first floor oxide layer in compound buried regions is thinner, by RESURF principle, the active top layer silicon of the optimum corresponding to it doping content is higher, thus can mix higher impurity concentration in the active top layer silicon in pressure-resistance structure proposed by the invention, thus reduce the ON state conducting resistance of this structure.
The active top layer silicon concentration of LDMOS when obtaining the most high-breakdown-voltage of 467V as shown in Figure 8 based on pressure-resistance structure of the present invention is 4.1 × 10
15cm
-3, and the conventional SOI LDMOS as shown in Figure 9 active top layer silicon concentration when obtaining the most high-breakdown-voltage of 350V is only 2.4 × 10
15cm
-3, this means that the LDMOS based on pressure-resistance structure of the present invention keeps low conducting resistance while acquisition high-breakdown-voltage.
Figure 11 is based on the I-V relation that drains when the LDMOS of pressure-resistance structure proposed by the invention and conventional LDMOS ON state, the visible LDMOS based on pressure-resistance structure proposed by the invention has lower conducting resistance and better current driving ability, and its conducting resistance is by the 10ohmmm of conventional SOI LDMOS
2be reduced to 6.3ohmmm
2, reduction amplitude reaches 37%.Finally, because the heat conductivility of polysilicon is far due to silica, due to the existence of polycrystalline silicon material in buried regions in pressure-resistance structure thus proposed by the invention, make its heat conductivility more excellent.
Figure 12 is LDMOS based on pressure-resistance structure proposed by the invention and the surface temperature distribution of conventional LDMOS when power consumption is 1mW/ μm, obviously can find out, LDMOS temperature characterisitic based on pressure-resistance structure proposed by the invention is better than conventional LDMOS, and its maximum temperature has the 350.8K of conventional structure to reduce to 337.9K.Comprehensive, compared with conventional SOI LDMOS, the LDMOS device based on part compound buried regions pressure-resistance structure proposed by the invention has higher puncture voltage, lower conducting resistance, and more excellent temperature performance.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (4)
1. one kind has the SOI pressure-resistance structure of part compound buried regions, active top silicon layer (2) comprising P/N substrate (1), be arranged on the part compound oxygen buried layer (4) on P/N substrate and be arranged on part compound oxygen buried layer, it is characterized in that: described part compound oxygen buried layer (4) comprises the oxygen buried layer (3) and compound buried regions that are set up in parallel, the first floor oxygen buried layer (5) that described compound buried regions comprises the bottom oxygen buried layer (7) be arranged on P/N substrate, arranges the intermediate polysilicon layer (6) on bottom oxygen buried layer and be arranged on intermediate polysilicon layer.
2. a kind of SOI pressure-resistance structure with part compound buried regions according to claim 1, described active top layer silicon (2) is one or more in Si, SiC, GaN semi-conducting material.
3. a kind of SOI pressure-resistance structure with part compound buried regions according to claim 1, is characterized in that: described oxygen buried layer (3) is SiO
2and/or Si
3n
4medium.
4. a kind of SOI pressure-resistance structure with part compound buried regions according to claim 1, is characterized in that: described intermediate polysilicon layer (6) adulterates for N-type and/or P type doping and/or zero is adulterated.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105932062A (en) * | 2016-05-19 | 2016-09-07 | 杭州电子科技大学 | SOI LDMOS device with buried field plates |
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| US4300150A (en) * | 1980-06-16 | 1981-11-10 | North American Philips Corporation | Lateral double-diffused MOS transistor device |
| US5640040A (en) * | 1987-02-26 | 1997-06-17 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
| KR20020071574A (en) * | 2001-03-07 | 2002-09-13 | 한민구 | Soi power transistor and manufacturing method thereof |
| CN101083278A (en) * | 2006-10-25 | 2007-12-05 | 电子科技大学 | Pressure resistant layer structure having dual-medium buried layer and SOI power device using the same |
| CN101477999A (en) * | 2009-01-19 | 2009-07-08 | 电子科技大学 | SOI voltage resistant structure having interface charge island for power device |
-
2015
- 2015-02-12 CN CN201510076359.1A patent/CN104659102A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4300150A (en) * | 1980-06-16 | 1981-11-10 | North American Philips Corporation | Lateral double-diffused MOS transistor device |
| US5640040A (en) * | 1987-02-26 | 1997-06-17 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
| KR20020071574A (en) * | 2001-03-07 | 2002-09-13 | 한민구 | Soi power transistor and manufacturing method thereof |
| CN101083278A (en) * | 2006-10-25 | 2007-12-05 | 电子科技大学 | Pressure resistant layer structure having dual-medium buried layer and SOI power device using the same |
| CN101477999A (en) * | 2009-01-19 | 2009-07-08 | 电子科技大学 | SOI voltage resistant structure having interface charge island for power device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105932062A (en) * | 2016-05-19 | 2016-09-07 | 杭州电子科技大学 | SOI LDMOS device with buried field plates |
| CN105932062B (en) * | 2016-05-19 | 2019-04-02 | 杭州电子科技大学 | It is a kind of with the SOI LDMOS device for burying oxygen field plate |
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