CN104752380A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN104752380A
CN104752380A CN201310750904.1A CN201310750904A CN104752380A CN 104752380 A CN104752380 A CN 104752380A CN 201310750904 A CN201310750904 A CN 201310750904A CN 104752380 A CN104752380 A CN 104752380A
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CN
China
Prior art keywords
bare chip
semiconductor
post
substrate
semiconductor bare
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310750904.1A
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English (en)
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CN104752380B (zh
Inventor
邱进添
S.阿帕德亚裕拉
邰恩勇
黄大成
Y.张
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk SemiConductor Shanghai Co Ltd
SanDisk Information Technology Shanghai Co Ltd
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SanDisk SemiConductor Shanghai Co Ltd
SanDisk Information Technology Shanghai Co Ltd
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Application filed by SanDisk SemiConductor Shanghai Co Ltd, SanDisk Information Technology Shanghai Co Ltd filed Critical SanDisk SemiConductor Shanghai Co Ltd
Priority to CN201310750904.1A priority Critical patent/CN104752380B/zh
Priority to US14/561,689 priority patent/US20150187745A1/en
Priority to TW103144381A priority patent/TWI654721B/zh
Publication of CN104752380A publication Critical patent/CN104752380A/zh
Application granted granted Critical
Publication of CN104752380B publication Critical patent/CN104752380B/zh
Expired - Fee Related legal-status Critical Current
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Abstract

本技术公开了一种半导体装置。该半导体装置包括半导体裸芯，例如控制器裸芯，安装在基板的表面上。诸如焊料的柱也可形成在基板上，位于半导体裸芯周围。柱在基板上方形成的高度大于包括任何引线键合的基板安装半导体裸芯在基板上方的高度。诸如闪存裸芯的一个或多个第二半导体裸芯的组可固定到基板，在焊料柱的顶部上，而不接触基板安装半导体裸芯。

Description

半导体装置
技术领域
本技术涉及半导体装置。
背景技术
便携式消费电子产品需求上的快速增长驱动了高容量存储装置的需求。诸如闪存存储卡的非易失性半导体存储装置正变得广泛地用于满足日益增长的数字信息存储和交换的需求。它们的轻便性、多功能性和耐久设计以及它们的高可靠性和大容量已经使这样的存储装置理想地用于广泛种类的电子装置，例如包括数字相机、数字音乐播放器、视频游戏控制台、PDA和移动电话。
尽管很多变化的封装构造是已知的，但是闪存存储卡通常可制造为系统级封装（system-in-a-package，SiP）或多芯片模块（MCM），其中多个裸芯（die）安装且互连在小的足印（footprint）基板上。基板通常可包括刚性、电介质基底，具有在一侧或两侧上蚀刻的导电层。电连接形成在裸芯和导电层之间，并且导电层提供电引线结构用于裸芯到主机装置的连接。一旦裸芯和基板之间的电连接制成，该组件然后典型地装入提供保护封装的模制化合物（molding compound）中。
图1和2中示出了传统半导体封装体的截面侧视图和俯视图（图2中没有模制化合物）。典型的封装体包括贴附到基板26的多个半导体裸芯，例如闪存裸芯22和控制器裸芯24。多个裸芯键合衬垫28可在裸芯制造工艺期间形成在半导体裸芯22、24上。类似地，多个接触衬垫30可形成在基板26上。裸芯22可贴附到基板26，然后裸芯24可安装在裸芯22上。然后，所有的裸芯可通过在各裸芯键合衬垫28和接触衬垫30对之间的贴附引引线键合件32电连接到基板。一旦所有的电连接制成，则裸芯和引线键合件可包封在模制化合物34中以密封封装体且保护裸芯和引线键合件。
为了最有效地利用封装足印，已知在彼此顶上堆叠半导体裸芯、彼此完全重叠或者如图1和2所示具有偏移。在偏移构造中，一个裸芯堆叠在另一个裸芯的顶上，使得下裸芯的键合衬垫被暴露。偏移构造提供了便利接近堆叠中每个半导体裸芯上的键合衬垫的优点。尽管图1的堆叠中示出了两个存储器裸芯，但是已知在堆叠中提供更多个存储器裸芯，例如，四个或八个存储器裸芯。
为了在保持或减小封装体总体尺寸的同时提高半导体封装体的存储能力，存储器裸芯的尺寸与封装体的总体尺寸相比已经变得很大。为此，通常使存储器裸芯的足印与基板的足印几乎同样大。
控制器裸芯24通常小于存储器裸芯22。因此，控制器裸芯24通常设置在存储器裸芯堆叠的顶部。该构造具有一定的缺点。例如，难以形成从控制器裸芯上的裸芯键合衬垫下至基板的大量的引线键合件。已经知晓在控制器裸芯下方提供插入体（interposer）或重分配层，使得从控制器裸芯至插入体，然后从插入体下至基板，形成引线键合件。然而，这增加了半导体装置制造的成本和复杂性。而且，从控制器裸芯到基板的相对长的引线键合件减慢了半导体装置的操作。
内容
本技术的示例涉及半导体装置，其包括：基板；安装到基板的表面且电连接到基板的第一半导体裸芯；半导体裸芯连同电连接件，在基板的表面上方延伸第一高度；多个柱，贴附在第一半导体裸芯周围，多个柱在基板的表面上方延伸第二高度，第二高度大于第一高度；一个或多个第二半导体裸芯的组附着在多个柱上，柱将一个或多个第二半导体裸芯的组支撑在第一半导体裸芯以及第一半导体裸芯的到基板的电连接件上方。
在另一个示例中，本技术涉及半导体装置，其包括：基板，包括接触衬垫；第一半导体裸芯，安装到基板的表面且电连接到基板；多个焊料柱，焊接到第一半导体裸芯周围的接触衬垫；附着在多个柱上的一个或多个第二半导体裸芯的组，柱支撑一个或多个第二半导体裸芯的组，以将一个或多个第二半导体裸芯的组与第一半导体裸芯和第一半导体裸芯的到基板的电连接件间隔开。
在进一步的示例中，本技术涉及半导体装置，其包括：基板；第一半导体裸芯，安装到基板的表面且电连接到基板；多个柱，具有在第一半导体裸芯周围附着到基板的第一表面和与基板间隔开的第二表面；一个或多个第二半导体裸芯的组，一个或多个第二半导体裸芯的组中的半导体裸芯包括在该半导体裸芯的表面上的裸芯附着膜的层，一个或多个第二半导体裸芯的组通过多个柱的第二表面附着到基板，多个柱埋置在一个或多个半导体裸芯组的该半导体裸芯的表面上的裸芯附着膜中，柱支撑一个或多个第二半导体裸芯的组，一个或多个第二半导体裸芯的组与包括第一半导体裸芯的到基板的电连接件的第一半导体裸芯之间具有间隔。
附图说明
图1是传统半导体装置的现有技术侧视图，包括以偏移关系堆叠的成对半导体裸芯。
图2是传统半导体装置的现有技术侧视图，包括以重叠关系堆叠且由焊料柱分开的成对半导体裸芯。
图3是根据本技术实施例的形成半导体裸芯的流程图。
图4是根据本技术实施例的半导体装置的制造中的阶段的立体图（perspective view）。
图5是根据本技术实施例的半导体装置的制造中的进一步阶段的立体图。
图6是根据本技术可替换实施例的半导体装置的制造中的阶段的立体图。
图7是根据本技术实施例的半导体装置的制造中的另一阶段的立体图。
图8是根据本技术实施例的半导体装置的制造中进一步阶段的立体图。
图9和10是根据本技术实施例的半导体装置的制造中的进一步阶段的立体图和侧视图。
图11和12是根据本技术实施例的半导体装置的制造中的进一步阶段的立体图和侧视图。
图13是根据本技术的可替换实施例的焊料柱的部分侧视图。
图14-16是根据本技术可替换实施例的基板上的焊料柱的立体图。
图17是在根据本技术可替换实施例的在半导体裸芯上形成焊料柱的流程图。
图18是根据图17的流程包括焊料柱的半导体晶片的立体图。
图19是来自图17的晶片的单一半导体裸芯。
图20和21是根据图17-19的可替换实施例制造的半导体装置的制造阶段的侧视图。
具体实施方式
现在，将参考图3至21描述本技术，在实施例中，本技术涉及包括安装在基板的表面上的诸如为控制器的第一半导体裸芯的半导体装置。柱（其材料例如是焊料）也可形成在基板上，位于半导体裸芯周围。柱在基板上方形成的高度大于包括任何引线键合件的基板安装半导体裸芯在基板上方的高度。一个或多个第二半导体裸芯的组（诸如闪存裸芯）可附着到基板，在焊料柱的顶上而不接触基板安装半导体裸芯。
在可替换实施例中，柱不形成在基板上以随后接收一个或多个第二半导体裸芯的组，而是改为形成在半导体晶片上，第二组的最底部裸芯从该晶片形成。在对半导体晶片切块时，拾取和放置机器人可安装最底部裸芯使得柱设置为抵靠基板，因此在基板安装半导体裸芯之上隔开最底部裸芯。
应理解，本技术可以以很多不同的形式实施，而不应解释为限于在此阐述的实施例。相反，提供这些实施例使本公开透彻且完整，并且将向本领域的技术人员全面传达本技术。实际上，本技术旨在覆盖这些实施例的替换、变型和等同方案，其包括在如所附权利要求限定的本技术的范围和精神内。此外，在本技术的下面的详细描述中，阐述了大量的特定细节，以便提供对本技术的透彻理解。然而，本领域的普通技术人员应理解，本技术可在没有这些特定细节的情况下实施。
如这里所用的术语“顶”和“底”、“上”和“下”以及“垂直”和“水平”仅为示例和说明的目的，而不意味着限制本技术的描述，因为所述项目在位置和方向上可调换。再者，如这里所用，术语“基本上”和/或“约”是指特定的尺寸或参数可在给定应用的可接受制造公差内变化。在一个实施例中，可接受制造公差为±.25%。
现在将参考图3和17的流程图以及图4-16和18-21的视图说明本技术的实施例。尽管附图示出了各半导体装置100或其一部分，但是应理解，装置100可与基板面板上的多个其它装置100一起批量加工以实现规模经济。基板面板上的半导体装置100的行数和列数可变化。
基板面板可从基板102开始（再一次地，例如，一个这样的基板示出在图4-16中）。基板102可为各种不同的裸芯载体介质，包括印刷电路板（PCB）、引线框或带自动键合（TAB）带。
参见图4，基板可包括多个通路孔104、电迹线106和接触衬垫108。基板102可包括比所示更多或更少的通路孔104、迹线106和/或接触衬垫108（图中仅给出了其中一部分）。接触衬垫108示出为图中的阴影矩形和圆形（而通路孔示出为没有阴影的圆形）。在另外的实施例中，通路孔104、迹线106和接触衬垫108可具有与图中所示不同的位置。图4还示出了虚拟电路图案110，用于防止基板102的表面上的热失配。
参见图3的流程图，无源元件112可在步骤200中固定到基板102。一个或多个无源元件可包括例如一个或多个电容器、电阻器和/或电感器，然而可以考虑其它的部件。所示的无源元件112（图中仅标示出其中一个）仅为示例，并且在另外的实施例中数量、类型和位置可变化。
在步骤204中，焊料柱120（标示出了其中一部分）可形成在基板102的表面上，如图5所示。焊料柱120的数量和位置仅示出为示例，并且如下面所说明可在本技术的另外的实施例中变化。然而，在一个示例中，当实施为随后固化的焊料球或焊料膏时，焊料柱可施加到多个接触衬垫108。在一个示例中，焊料柱可由锡形成，然而可以考虑诸如金、铝或铜的其它材料。在实施例中，焊料柱可由电介质材料形成，或者具有电介质添加物以使焊料柱不导电。
在焊料球用于焊料柱120的情况下，焊料球可以是已知的结构且在焊料球放置工艺中施加。在一个示例中，焊料球可在基板102的表面上方延伸30μm至200μm之间，并且在另外的实施例中，在基板的表面上方延伸120μm。然而，应理解，这些数字仅为示例，在另外的实施例中，焊料球在表面上方的高度可更小或更大。通过加热焊料球到焊料球熔点以上的温度（在一个示例中221℃）持续30至60秒的时间，峰值温度在245℃和255℃之间，焊料球可固化到接触衬垫108上。这些时间和温度仅为示例，并且在另外的实施例中可变化。
在焊料膏用于焊料柱120的情况下，焊料膏可以以已知的丝网印刷工艺施加到接触衬垫108。如所知的，这样的焊料丝网工艺可包括施加膏到接触衬垫108，膏包括悬浮在液态溶剂材料中的微焊料球（例如其直径约为10μm至50μm）。焊料膏可在之后的加热工艺（例如IR-回流工艺）中固化成固化焊料柱，以将焊料膏加热到熔点（在一个示例中为221℃）之上持续30至60秒的时间，峰值温度在245℃和255℃之间。这些时间和温度仅为示例，并且在另外的实施例中可变化。一旦固化，焊料膏柱可各自在基板102的表面上方延伸30μm至200μm之间，并且在另外的实施例中，在基板的表面上方延伸120μm。应理解，这些数字仅为示例，在另外的实施例中焊料膏柱在表面上方的高度可比此更小或更大。
进一步可以考虑的是其它结构性刚性材料可用于取代焊料膏或者焊料球具有柱120。这样的结构性刚性材料可以是在施加到基板100时为结构性刚性的，或者可在加热或固化工艺后变为结构性刚性，并且如下所说明的可以以相同的方式用作由焊料球或焊料膏形成的焊料柱。
如在图5的立体图中所见，在一个实施例中，焊料柱120可在基板102的表面之上定位为相对均匀地分布在接触衬垫108上。在图5所示的示例中，有15个焊料柱120。应理解，在另外的实施例中可有几百个焊料柱120，少到三个或四个焊料柱，或者其之间的任何数量，如下面参考图14-16的更加详细描述的。在可替换实施例中，焊料柱可在基板102上设置成各种其它图案。
焊料柱120可施加到有源的接触衬垫108，是指这样的接触衬垫108用于某种电功能，例如用作功率、接地和/或信号管道（conduits）。焊料柱120可替换地或附加地施加到无源的接触衬垫108，无源的接触衬垫108不传送信号、功率或接地。
在步骤208中，半导体裸芯114可安装在基板102的表面上，如图6所示。表面安装半导体裸芯114可设置在基板102上，位于没有焊料柱120的区域115内，例如，在基板102的中心。半导体裸芯114可为控制器ASIC。然而，裸芯114可为其它类型的半导体裸芯，例如DRAM或NAND。
图7示出了安装在基板102上的半导体裸芯114。半导体裸芯114包括裸芯键合衬垫116，图7中示例性地标示出其中一个。所示裸芯键合衬垫116的数量仅为清楚起见，并且应理解在另外的实施例中可有更多的接触衬垫108和裸芯键合衬垫116。而且，尽管半导体裸芯114在图7中示出在四侧上具有裸芯键合衬垫116，但是应理解在另外的实施例中半导体裸芯114可在半导体裸芯114的一侧、两侧或三侧上具有裸芯键合衬垫116。
在实施例中，半导体裸芯114可具有46μm的厚度，并且半导体裸芯114利用10μm厚的裸芯附着膜附着到基板，然而这些厚度可能变化。焊料柱120每一个在基板102上方离开基板表面的高度可形成为比半导体裸芯114和裸芯附着膜连同半导体裸芯114的任何从其离开的引线键合件的厚度更高。如上所述，在一个示例中，焊料柱120的高度可为120μm。
在步骤210中，半导体裸芯114上的裸芯键合衬垫116可通过引线键合件118电连接到基板102上的接触衬垫108，图7中标示出了其中一个。引线键合件可通过形成引线键合件118的引线键合劈刀（未示出）实现。应理解，半导体裸芯114可采用引线键合之外的技术电连接到基板102。例如，半导体裸芯114可为焊接在基板102的接触衬垫上的倒装芯片。作为另一示例，导电引线可通过已知的印刷工艺印刷在裸芯键合衬垫和接触衬垫之间以电连接半导体裸芯114到基板102。
应理解，在另外的实施例中，形成焊料柱（步骤204）、安装半导体裸芯114（步骤208）和引线键合半导体114（步骤210）的步骤的顺序可以以不同的顺序执行。例如，可安装且引线键合半导体裸芯114，其后在基板上形成焊料柱120。作为进一步的示例，可安装半导体裸芯114，形成焊料柱，其后可引线键合半导体裸芯114。
在步骤214中，一个或多个半导体裸芯140可如图8-10所示堆叠在焊料柱120的顶上。半导体裸芯140可以台阶构造堆叠。尽管示出了两个这样的半导体裸芯140，但是在另外的实施例中裸芯堆叠中可有单一的半导体裸芯140或多于两个的半导体裸芯。半导体裸芯140可包括集成电路142，例如用作存储器裸芯，更优选NAND闪存裸芯，然而可以考虑其它类型的半导体裸芯。
由图10-13可见，最底部半导体裸芯140因被焊料柱120的上表面（上表面是焊料柱与基板102接触的表面的相反表面）支撑而可附着到基板。如上面所讨论，焊料柱120在基板102上方延伸的距离大于半导体裸芯114和引线键合件，使得半导体裸芯140安装在柱120上而不接触半导体裸芯114或引线键合件。另外，焊料柱120在基板102上的分布对半导体裸芯140提供总体上平面的支撑。
在实施例中，焊料柱（焊料球或焊料膏）制造为使每个焊料柱120在基板102的表面上方延伸相同的高度。这对安装在焊料柱上的半导体裸芯140提供总体平面支撑。
然而，应理解，柱120不需要每一个在基板的表面上方延伸相同的高度，例如在焊料柱的制造公差内变化。焊料柱120埋置在在最底部裸芯140的底表面上的裸芯附着膜的层内，如下面所说明。焊料柱120埋置在裸芯附着膜内允许焊料柱高度不同。具体地，不同高度的焊料柱可在裸芯附着膜的层中埋置到不同的程度，从而对其上安装的半导体裸芯140提供整体的平面支撑。
在实施例中，裸芯附着膜（DAF）144的层可施加到半导体裸芯140的底表面。DAF144用于在裸芯堆叠中彼此连接半导体裸芯140。另外，在将最底部裸芯140安放在基板上时，焊料柱120的上表面埋置在最底部半导体裸芯140上的DAF144内。图10是通过图9的线10-10的侧视图。图10示出埋置在最底部半导体裸芯140的DAF层144内的焊料柱120的上表面。这用于将最底部裸芯140以及安装在其上的裸芯附着在基板102的合适位置上，并且在包封工艺中用于抵抗施加在裸芯140上的剪切力，下面将更加详细地说明。
在实施例中，DAF144可从日本的Nitto Denko公司购买，并且可具有20至25μm之间的厚度，尽管在另外的实施例中它可更薄或更厚。较厚的DAF层可增加半导体装置100的高度，但是也可允许焊料柱120和DAF144之间更好的粘合以及在包封期间更好地消散剪切力。
柱120埋置在DAF层144内的表面可为平坦的或圆头的。还可想到焊料柱120的这些表面的形状可为锯齿状的、有刃的和/或另外不规则的，以改善焊料柱120和DAF144之间的键合。图11示出了根据这样的实施例的埋置在最底部半导体裸芯140的DAF144内的焊料柱120的部分放大图。
在步骤216中，半导体裸芯140可以以已知的引线键合工艺通过引线键合件146引线键合到基板102上的接触衬垫108，例如采用图10所示的引线键合劈刀（未示出）。
在裸芯堆叠形成且引线键合到基板102上的接触衬垫108后，半导体装置100可在如图12和13所示的步骤220中包封在模制化合物150内。如图12所示，一旦半导体装置100安放在上模板和下模板（未示出）之间，液态的模制化合物150可注入在半导体装置100周围以及进入其中。具体地，模制化合物150可在基板102和最底部半导体裸芯140之间注入由焊料柱120限定的间隔中。
一旦模制化合物150硬化，模制化合物包封且保护基板102上的半导体裸芯114。模制化合物150还固定了半导体裸芯140在半导体装置100中的位置，半导体裸芯140固定到由于焊料柱120埋置在最底部半导体裸芯140的DAF144内而所处的适当位置的点。
模制化合物150可为已知的环氧，例如从Sumitomo公司和Nitto Denko公司可购买，二者在日本有总部。在步骤220后，包封的封装体可在步骤224中从基板面板单片化以形成图13所示的最终的半导体装置100。其后，装置100可在步骤226中经受电测试和寿命测试。在某些实施例中，最终的半导体装置100可在在步骤228中包封在盖（未示出）内。
如上所述，焊料柱120可提供为不同的数量和在基板102上的不同位置。图14示出了包括安放在基板102上的四个焊料柱120的实施例，其放置为总体上与最底部半导体裸芯140的四个角接触。图15示出了包括焊料柱120的另外的实施例。三个柱焊料柱120足以限定一平面，该平面用于支撑半导体裸芯114和基板102的表面之上的半导体裸芯140。
在上述实施例中，焊料柱120焊接到接触衬垫108上。鉴于柱120不执行电功能，在另外的实施例中柱可在接触衬垫108之外的位置固定到基板102。这样的示例示出在图16中。焊料掩模层（未示出）可形成在基板102的表面上以覆盖基板的接触衬垫108之外的区域。该实施例中的柱120可附着到焊料掩模上的不同位置。如前所述，在另外的实施例中，柱120可由焊料之外的材料形成。
在如上所述的实施例中，焊料柱120形成在基板102上，并且其后半导体裸芯140安装在焊料柱120上。在另一可替换实施例中，焊料柱120可在从其切割半导体裸芯140的工艺中形成在半导体裸芯140的表面上。现在，参考图17的流程图以及图18-21的图示描述这样的示例。
参见图18，最底部半导体裸芯140可由半导体晶片300形成。半导体晶片300可在在步骤250中形成的晶片材料的锭开始。在一个示例中，锭可为根据切克劳斯基（CZ）或浮区（FZ）工艺生长的单晶硅。在另外的实施例中锭可为多晶硅。
在步骤252中，半导体晶片300可从锭切割且在两个主表面上抛光以提供光滑的表面。晶片300可具有其中形成集成电路144的第一主表面以及相反的、第二主表面305（图18）。在步骤254中，研磨轮可施加到第二主表面305以背研磨晶片300例如780μm至280μm，然而这些厚度仅为示例，并且在不同的实施例中可变化。因为此步骤在实施例中可跳过，故此步骤以虚线示出。DAF（例如前面所述的DAF144）的层可在步骤256中施加到晶片300的表面305。
在步骤260中，柱120形成在主表面305上。在形成柱120之前，要形成的柱的位置可在步骤258中对准到晶片。例如，已经知晓要从晶片300切割半导体裸芯的完成位置。柱120的位置可设置为在从晶片切块的半导体裸芯的每个的相同位置上对准。此对准可由多种不同的方法实现。在一个示例中，参考位置可限定在晶片300上，并且半导体裸芯和柱120的所有位置可相对于这些参考点限定。
例如，晶片300典型地包括平边310（图18），用于识别和定向用于加工的晶片的晶体结构。平边310在称为劈开点312、314的点终止，其中晶片300的圆形部分与平边310相接。半导体裸芯140切块的位置可相对于劈开点312、314中的一者或二者限定。其后，用于半导体裸芯140的每一个的柱120的位置可通过以沿着x和y轴相对于劈开点312和/或314已知的距离定位而对准半导体裸芯的位置。因此，每个柱120可精确地定位在每个半导体裸芯内，例如，定位为当裸芯从晶片300切块时在每个裸芯140内留下敞开的中心区域148（图19）。
在步骤260中，柱120形成在晶片300上的所希望位置。柱可附着在主表面305上的DAF层中。在实施例中，柱可埋置在DAF层中。在另外的实施例中，柱305可通过DAF层安装到主表面305，例如通过已知的凸块键合技术。柱120可由锡或金形成，尽管其它的材料是可能的。柱120可具有如上所述的尺寸。
在形成柱120之后，晶片300可在在步骤262中切块成各个半导体裸芯140。晶片300可采用已知切块技术中的锯片切割。
在切块步骤中，晶片300可保持在晶片卡盘（未示出）上，包括柱120的主表面305保持抵靠晶片卡盘。晶片卡盘可设计为允许晶片300牢固地保持（尽管存在柱），例如，在晶片的外边缘周围在晶片和卡盘之间形成真空密封。其后，在步骤266中，具有真空尖端的拾取和放置机器人160（图20）可接触包括集成电路146的主表面且从真空卡盘取出半导体裸芯140。
拾取和放置机器人160可将半导体裸芯140放置在基板102上，如图20所示。半导体裸芯114可以已经如上所述安装且引线键合到基板102。裸芯140上的柱120可定位为抵靠基板102的表面，例如对准为抵靠接触衬垫108，并且例如在超声焊接或其它加热工艺中附着到接触衬垫108。
然后，一个或多个附加的半导体裸芯140可安装到图21所示的最底部半导体裸芯140以形成裸芯堆叠。这些附加的半导体裸芯140可来自于与图19所示晶片300不同的晶片，并且可不包括柱120。裸芯堆叠中的半导体裸芯140之后可引线键合到基板，并且半导体装置100可如上所述用模制化合物150包封。包封的封装体之后可单片化以形成最终的半导体装置100，如图21所示以及如前所述。
半导体装置100可用作LGA（焊盘栅格阵列）封装体，以用作主机装置内的可移除存储器。在这样的实施例中，接触指（未示出）可形成在基板102的下表面上，在半导体装置100插入主机装置中时用于与主机装置中的插脚匹配。可替换地，半导体装置100可用作BGA（球栅阵列）封装体以永久固定到主机装置内的印刷电路板。在这样的实施例中，焊料球（未示出）可形成在基板102的下表面上的接触衬垫上，用于焊接到主机装置的印刷电路板上。
焊料柱120允许诸如控制器的半导体裸芯114安装到基板102的表面上，同时提供大的、平坦的支撑平面用于安装附加的半导体裸芯，例如存储器裸芯。焊料柱120也是好的热导体以从半导体裸芯114和/或140传导热。
本技术前面的具体描述为了示例和说明的目的给出。它不旨在使穷举的或将本技术限制到所公开的精确形式。根据上面的教导，许多修改和变型都是可能的。所描述的实施例选择为最好地说明本技术的原理及其实际应用，因此使本领域的技术人员能以适合于（现在和将来的）具体预期应用的不同的实施方式和不同的变型利用本技术。本技术的范围旨在由所附权利要求限定。

Claims (31)

1.一种半导体装置，包括：
基板；
附着到该基板的多个柱；
一个或多个半导体裸芯的组；
裸芯附着膜，位于该一个或多个半导体裸芯的组中的该半导体裸芯之一的表面上，该多个柱埋置在该裸芯附着膜内以将该一个或多个半导体裸芯的组支撑在该基板上方。
2.如权利要求1所述的半导体装置，该一个或多个半导体裸芯的组包括一个或多个第二半导体裸芯的组，该装置还包括安装到该基板的表面且电连接到该基板的第一半导体裸芯，该第一半导体裸芯连同电连接件适配在该一个或多个第二半导体裸芯的组下方。
3.如权利要求1所述的半导体装置，其中该多个柱的埋置在该裸芯附着膜的层内的表面具有平坦的、圆头的、锯齿状的、有刃的或不规则的表面形状。
4.如权利要求1所述的半导体装置，还包括模制化合物，该模制化合物相对于该基板固定该一个或多个第二半导体裸芯的组。
5.如权利要求1所述的半导体装置，其中该多个柱由焊料制成。
6.如权利要求1所述的半导体装置，其中该多个柱由焊料球制成。
7.如权利要求1所述的半导体装置，其中该多个柱由焊料膏制成。
8.如权利要求1所述的半导体装置，其中该多个柱分布在该基板的该表面上。
9.如权利要求1所述的半导体装置，其中该多个柱是四个柱。
10.如权利要求1所述的半导体装置，其中该多个柱是三个柱。
11.如权利要求1所述的半导体装置，还包括在该基板上的接触衬垫，该多个柱安装到该接触衬垫。
12.如权利要求11所述的半导体装置，其中该多个柱安装到有源的该接触衬垫。
13.如权利要求11所述的半导体装置，其中该多个柱安装到无源的该接触衬垫。
14.如权利要求2所述的半导体装置，其中该第一半导体裸芯是控制器。
15.如权利要求14所述的半导体装置，其中该一个或多个第二半导体裸芯的组是闪存裸芯。
16.一种半导体装置，包括：
基板，包括接触衬垫；
第一半导体裸芯，安装到该基板的表面且电连接到该基板；
多个焊料柱，焊接到该第一半导体裸芯周围的接触衬垫；
附着在该多个柱上的一个或多个第二半导体裸芯的组，该柱支撑该一个或多个第二半导体裸芯的组，以将该一个或多个第二半导体裸芯的组与该第一半导体裸芯以及该第一半导体裸芯的到该基板的电连接件间隔开。
17.如权利要求16所述的半导体装置，其中该多个柱由焊料球制成。
18.如权利要求16所述的半导体装置，其中该多个柱由焊料膏制成。
19.如权利要求16所述的半导体装置，其中该多个柱是四个柱。
20.如权利要求16所述的半导体装置，其中该多个柱是三个柱。
21.如权利要求16所述的半导体装置，其中该多个柱安装到有源的该接触衬垫。
22.如权利要求16所述的半导体装置，其中该多个柱安装到无源的该接触衬垫。
23.如权利要求16所述的半导体装置，其中该第一半导体裸芯是控制器。
24.如权利要求23所述的半导体装置，其中该一个或多个第二半导体裸芯的组是闪存裸芯。
25.一种半导体装置，包括：
基板；
第一半导体裸芯，安装到该基板的表面且电连接到该基板；
多个柱，具有在该第一半导体裸芯周围附着到该基板的第一表面和与该基板间隔开的第二表面；
一个或多个第二半导体裸芯的组，该一个或多个第二半导体裸芯的组中的半导体裸芯包括在该半导体裸芯的表面上的裸芯附着膜的层，该一个或多个第二半导体裸芯的组通过该多个柱的该第二表面附着到该基板，该多个柱埋置在该一个或多个半导体裸芯组的该半导体裸芯的该表面上的该裸芯附着膜中，该柱支撑该一个或多个第二半导体裸芯的组，该一个或多个第二半导体裸芯的组与包括该第一半导体裸芯的到该基板的电连接件的该第一半导体裸芯之间具有间隔。
26.如权利要求25所述的半导体装置，其中该多个柱的该第二表面具有平坦的、圆头的、锯齿状的、有刃的或不规则表面形状。
27.如权利要求25所述的半导体装置，还包括模制化合物，该模制化合物相对于该基板固定该一个或多个第二半导体裸芯的组。
28.如权利要求25所述的半导体装置，其中该多个柱由焊料制造。
29.如权利要求25所述的半导体装置，还包括在该基板上的接触衬垫，该多个柱安装到该接触衬垫。
30.如权利要求25所述的半导体装置，其中该第一半导体裸芯是控制器。
31.如权利要求30所述的半导体装置，其中该一个或多个第二半导体裸芯的组是闪存裸芯。
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