CN105453067A - N-phase signal transition alignment - Google Patents

N-phase signal transition alignment Download PDF

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Publication number
CN105453067A
CN105453067A CN201480044658.0A CN201480044658A CN105453067A CN 105453067 A CN105453067 A CN 105453067A CN 201480044658 A CN201480044658 A CN 201480044658A CN 105453067 A CN105453067 A CN 105453067A
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CN
China
Prior art keywords
connectors
connector
lasting
limited proportionality
code element
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Granted
Application number
CN201480044658.0A
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Chinese (zh)
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CN105453067B (en
Inventor
C·李
G·A·威利
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4278—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using an embedded synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4919—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using balanced multilevel codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state.

Description

N phase signals changes aims at
The cross reference of related application
This application claims the U.S. Provisional Patent Application No.61/863 submitted on August 8th, 2013,695 and on August 6th, 2014 submit to U.S. Non-provisional Patent application No.14/453, the right of priority of 346 and rights and interests, the full content of this two pieces application is included in this by quoting.
Background
Field
The disclosure relates generally to high-speed data communication interface, particularly relates to the Signal Regulation in multi-thread, heterogeneous data link.
Background technology
The manufacturer of mobile device (such as cell phone) can obtain (comprising different manufacturer) each assembly of mobile device from various source.Such as, the application processor in cell phone can obtain from the first manufacturer, and cellular display can obtain from the second manufacturer.Measured or proprietary physical interface can be used to come interconnection applications processor and display or other equipment.Such as, display can provide the interface deferred to by display system interface (DSI) standard of mobile Industry Processor Interface alliance (MIPI) defined.
In multi-thread interface, the ability of the maximal rate of communication link and clock and data recovery (CDR) circuit recovered clock information can change and limited by changing relevant maximum time with the signal transmitted on the communication link.In multi-thread interface, the transformation on different conductor can represent the difference variation of signal fringe time, and this may cause the output of the receiver in receiver equipment to change at the different time relative to data or symbol boundaries.Fringe time difference larger in multiline signal needs to realize delay element usually in ce circuit, and the minimum delay that wherein this delay element has at least reaches the difference of minimum receiver transition events and maximum receiver transition events.Maximum time of this delay element can because limiting cycle of transfer clock and the handling capacity limited on communication link significantly.
General introduction
Embodiment disclosed herein provides system, the method and apparatus of the transfer rate that the physical interface between the equipment in implement device improves.This device can comprise having and can be co-located in electronic installation and by the mobile terminal of multiple integrated circuit (IC) equipment that is coupled of one or more data link communication ground.
In one side of the present disclosure, a kind of data transmission method comprise the difference between determining the every a pair consecutive code unit in the multiple code elements transmitted on three or more connectors, based on this difference estimate this between the limited proportionality at the symbol boundaries place between coherent code element last and lasting between this limited proportionality is estimated as and exceedes threshold time period time revise the operation of one or more drivers of these three or more connectors to reduce lasting between this limited proportionality.Difference between every a pair consecutive code unit can be relevant with the signaling status of these three or more connectors.Each code element can be a kind of signaling status in each connector definition at least three kinds of signaling statuss in these three or more connectors.
On the other hand, the operation revising this one or more driver can make two or more outputs of the state transfer testing circuit in receiver aim in time.This state transfer testing circuit can be configured to the signaling status comparing each pair of connectors different in these three or more connectors.Make to comprising, transformation to be occurred within the time period being less than threshold time period in time.
On the other hand, the operation revising this one or more driver comprises the one or more delay of configuration and initiates to initiate state transfer on the first connector before corresponding state changes on the second connector to make driver.
On the other hand, the operation revising this one or more driver comprises the one or more delay of configuration and initiates to initiate state transfer on the first connector after corresponding state changes on the second connector to make driver.
On the other hand, the operation revising this one or more driver comprises the one or more delay of configuration and postpones to make driver relative to initiating corresponding state change on the second connector or initiate state transfer on the first connector in advance.
On the other hand, the operation revising this one or more driver is included in lasting between limited proportionality and is estimated as and postpones or initiate at least one connector in advance state transfer and lasting between this limited proportionality when exceeding threshold time period and be estimated as when being less than this threshold time period and suppress to postpone on these three or more connectors or advanced condition transformation.
On the other hand, the operation revising this one or more driver is included in the period be at least partially estimated as when exceeding threshold time period between this limited proportionality of lasting between limited proportionality and actively drives a connector and lasting between this limited proportionality to be estimated as when being less than this threshold time period to be suppressed when this transmits the second code element in coherent code element to drive this connector.
On the other hand, estimate lasting between limited proportionality comprise determine each connector in these three or more connectors change relative to the signaling status fringe time of symbol boundaries and the output of each differential receivers estimated in multiple differential receivers at this symbol boundaries and receiver place between delay.Each differential receivers in the plurality of differential receivers can be coupled to each pair of connectors different in these three or more connectors.
On the other hand, these three or more connectors can comprise at least three wires, and at least one wire is in non-driving condition between the transmission period of each code element.
In one side of the present disclosure, a kind of equipment comprise the difference between determining the every a pair consecutive code unit in the multiple code elements transmitted on three or more connectors device, be used for estimating based on this difference this to the device lasted between the limited proportionality at the symbol boundaries place between coherent code element and be used for the one or more drivers revising these three or more connectors when lasting between this limited proportionality is estimated as and exceedes threshold time period operation to reduce the device lasted between this limited proportionality.Difference between every a pair consecutive code unit can be relevant with the signaling status of these three or more connectors.Each code element can be a kind of signaling status in each connector definition at least three kinds of signaling statuss in these three or more connectors.
In one side of the present disclosure, a kind of device comprises multiple connector and the treatment circuit of two equipment in coupling terminal communicatedly.Difference between this treatment circuit can be configured to determine by the every a pair consecutive code unit in the multiple code elements transmitted on three or more connectors, based on this difference estimate this between the limited proportionality at the symbol boundaries place between coherent code element last and lasting between this limited proportionality is estimated as and exceedes threshold time period time revise the operation of one or more drivers of these three or more connectors to reduce lasting between this limited proportionality.This difference can be relevant with the signaling status of these three or more connectors.Each code element can be a kind of signaling status in each connector definition at least three kinds of signaling statuss in these three or more connectors.
In one side of the present disclosure, processor readable storage medium has one or more instruction.This one or more instruction can be performed by least one treatment circuit.This one or more instruction can make this at least one treatment circuit to determine the every a pair consecutive code unit in the multiple code elements transmitted on three or more connectors between difference, based on this difference estimate this between the limited proportionality at the symbol boundaries place between coherent code element last and lasting between this limited proportionality is estimated as and exceedes threshold time period time revise the operation of one or more drivers of these three or more connectors to reduce lasting between this limited proportionality.Difference between every a pair consecutive code unit can be relevant with the signaling status of these three or more connectors.Each code element can be a kind of signaling status in each connector definition at least three kinds of signaling statuss in these three or more connectors.
Accompanying drawing is sketched
Fig. 1 depicts the device adopting data link between each IC equipment, and this data link optionally operates according to one of multiple available standards.
Fig. 2 has explained orally the system architecture of the device for adopting data link between IC equipment.
Fig. 3 has explained orally N phase polarity data scrambler.
Fig. 4 has explained orally the signaling in N phase polarity addressable port.
Fig. 5 has explained orally N phase polarity decoder.
Fig. 6 has explained orally the transition detection in M line N phase polarity decoder.
Fig. 7 is the simplification example of signal elevating time on the impact of the transition detection in M line N phase polarity decoder.
Fig. 8 is the constitutional diagram of the sneak condition transformation explained orally in M line N phase polarity decoder.
Fig. 9 is the diagram explaining orally transformation in M line N phase polarity decoder and eye district.
Figure 10 explains orally according to the transformation of some aspect disclosed herein in advance and the reduced graph of some aspect postponed.
Figure 11 be explain orally according to some aspect disclosed herein for the signal that transmits on multi-thread interface in advance/diagram of an example of delay circuit.
Figure 12 explanation according to some aspect disclosed herein provide in advance/example of the operation of delay circuit.
Figure 13 explains orally the block diagram adopting and can carry out the example of the device of adaptive treatment circuit according to some aspect disclosed herein.
Figure 14 is the process flow diagram changing the method for aiming at for M line N phase signals.
Figure 15 explains orally the diagram adopting M line N phase signals to change the hard-wired example of the device aimed at.
Describe in detail
Referring now to accompanying drawing, various aspects are described.In the following description, numerous detail has been set forth for explanatory purposes to provide the thorough understanding to one or more aspect.But, be apparent that do not have these details also can put into practice this kind (class) aspect.
As used in this application, term " assembly ", " module ", " system " and similar terms are intended to comprise computer related entity, such as but be not limited to hardware, firmware, the combination of hardware and software, software or executory software.Such as, assembly can be but be not limited to be, the process run on a processor, processor, object, can executive item, the thread of execution, program and/or computing machine.As explanation, the application run on the computing device and this computing equipment can be all assemblies.One or more assembly can reside in the thread of process and/or execution, and assembly can localization on one computer and/or be distributed between two or more platform computing machines.In addition, the various computer-readable mediums that these assemblies can store various data structure from it perform.These assemblies can communicate by local and/or remote process, such as communicate according to the signal with one or more packet, such packet all in this way from by another component interaction in this signal and local system, distributed system and/or across the data of the network of such as the Internet and so on and the mutual assembly of other system.
In addition, term "or" is intended to represent inclusive "or" and nonexcludability "or".That is, can be clear that except as otherwise noted or from context, otherwise phrase " X adopts A or B " is intended to represent any arrangement of naturally can holding concurrently.That is, phrase " X adopts A or B " obtains meeting of following any example: X adopts A; X adopts B; Or X adopts A and B.In addition, the article " " used in the application and appended claims and " certain " generally should be construed as representing " one or more ", unless stated otherwise or can know from the context and find out and refer to singulative.
Some aspect of the present invention is applicable to the communication link be deployed between electronic devices, and these electronic equipments can comprise the sub-component of device (such as phone, mobile computing device, electrical equipment, vehicle electronics, avionics system etc.).Fig. 1 depicts the simplification example of the device of the communication link adopted between IC equipment.Device 100 can comprise the communication transceiver 106 being operationally coupled to treatment circuit 102.In one example, device 100 can comprise Wireless Telecom Equipment, and this Wireless Telecom Equipment is by RF transceiver 106 and radio access network (RAN), core access network, the Internet and/or another network service.Treatment circuit 102 can comprise application-specific integrated circuit (ASIC) 108 and/or other IC equipment one or more.ASIC108 can comprise one or more treatment facility, logical circuit etc.Treatment circuit 102 can comprise and/or be coupled to processor readable storage (such as storer 112), and this processor readable storage can safeguard the instruction that can be performed by the processor for the treatment of circuit 102 and the data can handled by treatment circuit 102.Some function for the treatment of circuit 102 can be controlled by one or more in operating system and application programming interface (API) 110 layers, and this API110 layer support also allows the software module of executive resident in storage medium (such as memory devices 112).Any memory devices that memory devices 112 can comprise ROM (read-only memory) (ROM) or random access memory (RAM), electrically erasable ROM (EEPROM), flash card or can use in disposal system and computing platform.Treatment circuit 102 can comprise or access local database 114, and this local data base 114 can safeguard operating parameter for configuring and operate this device 100 and out of Memory.One or more in local data base 114 active bank module, flash memory, magnetic medium, EEPROM, optical medium, tape, floppy disk or hard disk etc. realizes.Treatment circuit 102 also operationally can be coupled to external unit, such as antenna 122, display 124, operator's control (such as keypad 126, button, rocking bar or slider switch 128) and/or other assemblies.
Fig. 2 is the schematic block diagram of some aspect explaining orally device 200, all wireless mobile apparatus in this way of this device 200, mobile phone, mobile computing system, wireless telephone, notebook, tablet computing device, media player, game station, electrical equipment, wearable computing equipment etc.Device 200 can comprise the multiple IC equipment 202 and 230 being exchanged data and control information by communication link 220.Communication link 220 can be used to connect IC equipment 202 and 230, and no matter IC equipment 202,230 is closely adjacent to each other or is arranged in the physically different part of device 200.In one example, communication link 220 can be arranged on carry IC equipment 202 and 230 chip carrier, substrate or circuit board on.In another example, an IC equipment 202 can be arranged in the keyboard portion of folding telephone, and the 2nd IC equipment 230 can be arranged in the display part of folding telephone.In another example, a part for communication link 220 can comprise cable or optics connection.
Communication link 220 can comprise multiple channel 222,224 and 226.One or more channel 226 can be two-way, and can operate in semiduplex mode and/or in full-duplex mode.One or more channel 222 and/or 224 can be unidirectional.Communication link 220 can be asymmetrical, provides higher bandwidth in one direction thus.In one example, first communication channel 222 can be called as forward link 222, and second communication channel 224 can be called as reverse link 224.One IC equipment 202 can be designated as host computer system or transmitter, and the 2nd IC equipment 230 can be designated as client machine system or receiver, even if IC equipment 202 and 230 is all configured to transmit on communication link 222 and receive.In one example, forward link 222 can operate with higher data when data are conveyed to the 2nd IC equipment 230 from an IC equipment 202, and reverse link 224 can operate with lower data rate when data are conveyed to an IC equipment 202 from the 2nd IC equipment 230.
IC equipment 202 and 230 can comprise processor 206,236 separately, and this processor 206,236 can be located in treatment circuit, counting circuit or other circuit.In one example, one IC equipment 202 can be adapted to the Core Feature of actuating unit 200, comprise the radio communication safeguarded by transceiver 204 and antenna 214, and the 2nd IC equipment 230 can be configured to the user interface supporting management or operation display controller 232, and camera controller 234 can be used to control the operation of camera or video input apparatus.One or more further feature supported in IC equipment 202 and 230 can comprise keyboard, speech recognition component, GPS, biometric recognition system, motion sensor and other input or output equipment.Display controller 232 can comprise the circuit and software driver of supporting display (such as liquid crystal display (LCD) panel, touch-screen display, indicator etc.).Storage medium 208 and 238 can comprise transient state and/or non-transient memory device, and it is adapted to the instruction and data safeguarded and used by other assembly of respective processor 206 and 236 and/or IC equipment 202 and 230.Its corresponding storage medium 208 and 238 of each processor 206,236 and the communication between other module and circuit can be facilitated by one or more bus 212 and 242 respectively.
Reverse link 224 can operate by the mode identical with forward link 222, and forward link 222 and reverse link 224 can transmit with suitable speed or with different speed, and its medium velocity can be represented as data transfer rate (or message transmission rate) and/or transmitter clock speed.Depend on application, forward direction and reverse data rate can be substantially the same or differ several order of magnitude.In some applications, single two-way link 226 can support the communication between an IC equipment 202 and the 2nd IC equipment 230.When such as forward direction is shared identical physical connection with reverse link 222 with 224 and works in a half duplex manner, forward link 222 and/or reverse link 224 can be configured to two-way mode work.In one example, communication link 220 can be operated between an IC equipment 202 and the 2nd IC equipment 230, pass on data, control, order and out of Memory according to industry or other standard.
Industry standard can be different because of application.In one example, MIPI standard definition physical layer interface, this physical layer interface comprises application processor IC equipment 202 and supports the sync cap specification (D-PHY) between the IC equipment 230 of camera in mobile device or display.The operating characteristic of the product of the MIPI specification of mobile device is deferred in this D-PHY specification management and control.D-PHY interface can to support to be used between the assembly 202 and 230 in mobile device flexible, the low cost of interconnection, the data transmission of serial line interface at a high speed.These interfaces can comprise provides relative low bit rate and slow edge to avoid complementary metal oxide semiconductor (CMOS) (CMOS) parallel bus of electromagnetic interference (EMI) (EMI) problem.
The communication link 220 of Fig. 2 can be implemented as the wired bus comprising many signal conductor (being denoted as M bar wire).This M bar wire can be configured to carry the N phase coded data of (such as in display interface device) in high speed digital interface.The N phase polarity coding that this M bar wire can be facilitated in channel 222,224 and/or 226 on one or more.Physical layer driver 210 and 240 can be configured to or be adapted to the N phase polarity encoded data symbol generated for transmission on communication link 220, and/or the N phase polarity encoded data symbol that decoding receives from communication link 220.High speed data transfer is provided to the use of N phase polarity coding, and the half or less of the power of other interface can be consumed, such as, because less driver is active in N phase polarity coded data link 220.
N phase polarity encoding device 210 and/or 240 usually can to the multiple bit of each transformation coding on communication link 220.In one example, the combination of 3 phase codings and polarity coding can be used to support the lcd driver IC of wide Video Graphics Array (WVGA) 80 frames per second and do not need frame buffer, and it sends pixel data for display refreshing with the speed of 810Mbps.
Fig. 3 explains orally to can be used for the M line of some aspect of the communication link 220 realizing describing in Fig. 2, the schematic diagram of N phase polarity scrambler 300.In described example, M line, N phase polarity encoder transmission machine are configured to use M=3 wire and N=3 phase signaling to transmit information.Only for simplification, the object of the description of some aspect of the present invention be have selected to the example of 3 lines, 3 phases codings.Can be applied to for the principle disclosed in 3 lines, 3 phase scramblers and technology in other configuration of M line, N phase polarity encoder.
The signaling status defined for each wire in this M bar wire in M line, N phase polarity encoding scheme can comprise non-driving condition, positive driving condition and negative driving condition.In 3 lines, 3 phase polarity encoding schemes, by provide between two signal conductor in signal conductor 310a, 310b and/or 310c differential voltage and/or by drive a current through two signal conductor in signal conductor 310a, 310b and/or 310c of being connected in series with make electric current in this two signal conductor 310a, 310b and/or 310c in different directions flowing obtain positive driving condition and negative driving condition.In one example, the output by the driver by signal conductor 310a, 310b or 310c is placed in high impedance mode to realize non-driving condition.In another example, the voltage level by the intermediate point between the positive and negative voltage level that passively or actively makes " driving " signal conductor 310a, 310b or 310c present substantially to be in and driven signal conductor 310a, 310b and/or 310c provide obtains non-driving condition on signal conductor 310a, 310b or 310c.Under normal circumstances, signal conductor 310a, 310b or 310c of not having remarkable electric current to flow through not drive.{+1,0 ,-1} indicates the signaling status defined for 3 lines, 3 phase polarity encoding schemes can to use three signaling statuss that can represent voltage or current status.In one example, these three states+1,0 ,-1} can represent three voltage level+V, 0 ,-V.In another example, {+1,0 ,-1} can represent three voltage level+V ,+V/2,0 to these three states.In another example, these three states+1,0 ,-1} can represent electric current I, 0 ,-I.
3 lines, 3 phase polarity scramblers can adopt a set drive 308 to carry out the signaling status of control connector 310a, 310b and 310c.Driver 308 can be implemented as unit current levels pattern or voltage mode driver.Each driver 308 can receive one group of signal 316a, 316b or 316c of the signaling status determining corresponding connector 310a, 310b or 310c.In described example, each driver 308 is received as a pair signal 316a, 316b or 316c that corresponding connector 310a, 310b or 310c define four kinds of states.In another example, each driver 308 can be received as one group of three signal that corresponding connector 310a, 310b or 310c define 8 kinds of states.
For each transmission symbol section in M line, N phase polarity encoding scheme, at least one signal conductor 310a, 310b or 310c is in non-driving condition (0 signaling status), and just drive the number of (+1 signaling status) signal conductor 310a, 310b or 310c to equal the negative number driving (-1 signaling status) signal conductor 310a, 310b or 310c, to make the electric current sum flowing to receiver for zero.The signaling status of at least one signal conductor 310a, 310b or 310c transmits code element formerly and each code element transformation place that next transmits between code element changes.When the signaling status of at least one signal conductor 310a, 310b and/or 310c changes between every a pair continuation code unit, receiver reliably can generate receive clock based on these transformations.
In operation, mapper 302 can receive input data 310 and be mapped to a group code unit 312.In 3 described lines, 3 phase examples, this group code unit comprises seven 3 bit symbols, and 16 bit words inputting data 310 can be coded in every group code unit.Each bit of 3 bit symbols is for the state of symbol section definition signal wire one of 310a, 310b and a 310c.Parallel-serial converter 304 can be used sequence of symhols 312 serialization, this parallel-serial converter 304 provide code element 314 through timing sequence, the signaling status of each symbol definition these 3 wires 310a, 310b and 310c.Usual use carries out timing for the transfer clock defining symbol section to sequence of symhols 314, transmits single code element thus in each symbol section.3 phase of line scrambler 306 1 times code element ground receive 7 sequence of symhols 314 produced by mapper, and calculate the state of every signal conductor 310a, 310b and 310c for each symbol section.3 line scramblers 306 select the state of signal conductor 310a, 310b and 310c based on present input code unit 314 and the original state of signal conductor 310a, 310b and 310c.
Use M line, N phase encodes and permit several bit and be coded in multiple code element.Can to encode in each code element a non-integer data bit.In the example of 3 lines, 3 phase systems, 2 wires that can be driven via storage capacitors simultaneously have 3 kinds of available combination, and driven wire has 2 kinds may combine to upper polarity, thus produce 6 possible states.Signaling status each transformation place between symbols of signal conductor 310a, 310b and 310c changes, and correspondingly has 5 kinds of states to use when each transformation in these 6 kinds of states.In other words, the state of at least one wire generates reliable receive clock in each transformation place change with permit reception machine, and has five kinds may signaling statuss be available when given current signaling state in each transformation place.When there being 5 kinds of states, each code element codified log 2(5) ≌ 2.32 bits.Correspondingly, mapper can accept 16 bit words and convert thereof into 7 code elements, because every code element carries 7 code element codifieds, 16.24 bits of 2.32 bits.In other words, the combination of seven code elements of five kinds of states of encoding has 5 7(namely 78125) plant arrangement.Correspondingly, these 7 code elements can be used to 2 of coding 16 binary bits 16(namely 65536) plant arrangement.
Fig. 4 is the diagram of the example of the sequential chart 400 comprising the signal using three-phase modulations data coding scheme (it is explained orally by circular state diagram 450) to encode.Information can be coded in signaling status sequence, and wherein such as wire or connector are in the three-phase state S defined by constitutional diagram 450 1, S 2and S 3one of.Each state can separate 120 ° of phase shifts with other states.In one example, coded data can be carried out by the sense of rotation of the phase state on wire or connector.Phase state in signal can in the direction of the clock 452,452 ' or by counterclockwise 454,454 ' rotating.Such as in the clockwise direction on 452,452 ', phase state can comprise from S 1to S 2, from S 2to S 3with from S 3to S 1transformation in one or more sequence in advance.In the counterclockwise direction on 454,454 ', phase state can comprise from S 1to S 3, from S 3to S 2with from S 2to S 1transformation in one or more sequence in advance.Article three, wire 310a, 310b and 310c carry the different phase-shifted version of identical signal, and wherein these versions are relative to each other by phase shift 120 °.Each signaling status can be represented as the direction that different voltage level on wire or connector and/or electric current flow through wire or connector.During each state in signaling status sequence in 3 wire system, every bar wire 310a, 310b are in the signaling status different from other wires with 310c.When in 3 phase coded systems, use 3 is with upper conductor 310a, 310b and 310c, two or more wires 310a, 310b and/or 310c can be in identical signaling status in each signaling interval, but each state appears at least one wire 310a, 310b and/or 310c in each signaling interval.
Can carry out coded message at each phase transformation 410 place by sense of rotation, and 3 phase signals can change direction for each signaling status.By considering which wire 310a, 310b and/or 310c was in ' 0 ' state (such as before and after phase transformation, non-driving condition) determine sense of rotation, because wire 310a, 310b and/or 310c of not driving change rotating each signaling status place in three-phase signal, and no matter sense of rotation is how.
This encoding scheme also can in by the polarity 408 of two conductors in conductor 310a, 310b and 310c of actively driving coded message.Any time in 3 lines realize, lucky two conductors in conductor 310a, 310b, 310c are with the contrary electric current in direction and/or drive by differential voltage.In simple realization, two bit values 412 can be used to carry out coded data 412, and one of them bit is coded in the direction of phase transformation 410, and the second bit is coded in the polarity 408 of current state.
Sequential chart 400 has explained orally the data encoding using phase-rotation direction and polarity.Curve 402,404 is relevant with the signal that three wires 310a, 310b and 310c carry respectively for multiple phase state with 406.At first, phase transformation 410 is clockwise and highest significant position is set to scale-of-two ' 1 ', until the time that is rotated in 414 place of phase transformation 410 to be switched to counterclockwise (as represented by the scale-of-two ' 0 ' of highest significant position).Least significant bit (LSB) reflects the polarity 408 of this signal in each state.
In some instances, this encoding scheme can at two by coded message in the change of the polarity 408 of conductor 310a, 310b and/or 310c that actively drives.In one example, the bit with " 1 " value can be encoded as polarity 408 to be changed between two symbol section, and the bit with " 0 " value can be encoded as polarity 408 constant between these two symbol section.Demoder can be configured to the boundary decoded data coming between symbols by detecting the change of sense of rotation and the change of polarity.If data are coded in the change in polarity between two symbol section in the example of Fig. 4, then the sequence of described encoded radio 412 can by sequence { 11,10,10,11,10,01,01,01,01,01,01,01} replacement.
According to some aspect disclosed herein, the data of a bit can be coded in rotation in 3 lines, 3 phase coded systems or phase place change, and added bit can be coded in the polarity of two driven wires or be driven in the change in polarity compared with the polarity for preceding wire state of wire.Encode additional information each transformation of 3 lines, 3 phase coded systems is carried out by allowing to be converted to any one possible state from current state.When given 3 rotatable phases and each phase place have two kinds of polarity, in 3 lines, 3 phase coded systems, 6 kinds of states are had to use.Correspondingly, 5 kinds of states are had to use from the transformation of any current state.Correspondingly, every code element (transformation) codified log 2(5) ≌ 2.32 bits, this allows mapper 302 accept 16 bit words and be encoded into 7 code elements.
The transmission of N phase data can be used in provide in communication media (such as bus) three with upper conductor.The additional signal wire that use can be driven via storage capacitors simultaneously provides more combinations of state and polarity, and allows the data of the more bits of each transformation place coding between state.This can improve the handling capacity of system significantly, and reduces power consumption relative to the way using multiple differential pair to transmit data bit, provides the bandwidth of increase simultaneously.
In one example, scrambler can use 6 wires to transmit code element, wherein for each state, drives 2 pairs of wires.Article 6, wire can be marked as A to F, and to make in a state, wire A and F is just driven to, and wire B and E is driven to negative, and C and D is not driven (or not carrying electric current).For 6 wires, Ke Yiyou:
C ( 6 , 4 ) = 6 ! ( 6 - 4 ) ! · 4 ! = 15
Kind possible by the conductor combination actively driven, wherein for each phase state, have:
C ( 4 , 2 ) = 4 ! ( 4 - 2 ) ! · 2 ! = 6
Plant different combinations of polarities.
These 15 kinds different can being comprised by the conductor combination actively driven:
In 4 driven wires, it may be the combination that two wires are just being driven to (and another two must be driven to negative).Combinations of polarities can comprise:
++--+--++-+--+-+-++---++
Correspondingly, the sum of different conditions can be calculated as 15x6=90.In order to ensure the conversion between each code element, have 89 states to use from any current state, and the bit number that can be coded in each code element can be calculated as: every code element log 2(89) ≌ 6.47 bits.In the example present, a given 5x6.47=32.35 bit, 32 bit words can be encoded into 5 code elements by mapper.
For the bus of any size, can the general equation of number of driven conductor combination be the function of wire count in bus and driven wire count simultaneously:
The equation of the number of the combinations of polarities of driven wire is:
The bit number of every code element is:
Fig. 5 is the diagram 500 of some aspect of explanation 3 line, 3 phase decoder devices.Differential receivers 502 and Lead status demoder 504 are configured to provide three signal conductor 310a, 310b and the 310c numeral of state relative to each other, and detect this three signal conductor 310a, 310b and 310c signaling status compared to the change of the signaling status of this three signal conductor 310a, 310b and 310c in last code-element period.The numeral of the signaling status of this three signal conductor 310a, 310b and 310c during code-element period can be called as raw symbol.Deserializer 506 assembles the sequence of seven continuous raw symbol 514 to obtain one group of 7 code element 516 processed for de-mapping device 508.De-mapping device 508 produces 16 bits and exports data 518, and these output data 518 can be buffered in FIFO510 and export data 620 to provide.
In operation, Lead status demoder 504 can extract the sequence of code element 514 from the signal received at wire 310a, 310b and 310c.Signaling status based on the combination of the phase rotating and polarity or change in polarity that can be represented as the signal received on wire 310a, 310b and 310c carrys out decoded symbol 514, as disclosed herein.Lead status demoder can comprise CDR524, and this CDR524 extracts the clock 526 that can be used to reliably catch code element from wire 310a, 310b and 310c.CDR524 can be configured to carry out generated clock 526 based on the transformation at least one wire in each boundary generation wire 310a, 310b and/or the 310c between continuous symbol section.CDR524 can delayed clock 526 edge with allow all wire 310a, 310b and 310c to settle out if having time and guarantee thus current symbol can for decoding object reliably be captured.
The delay used by CDR524 can be configured to the time period allowing the Non-manifold edges effect being enough to be sequestered in same symbol boundaries, and wherein Non-manifold edges is generated at different time by the different differential receivers in differential receivers 502.These Non-manifold edges may produce when some state transfer makes different differential receivers 502 produce the edge that can relative to each other separate in time.CDR524 can comprise delay element, and this delay element postpones response to the edge in the first appearance in symbol boundaries place, until likely time of having occurred of edge.The performance change that it is expected to the assembly of CDR524 can affect the delay between Non-manifold edges.These performance change of the assembly in suitable CDR524 can be held by the delay taking into account the poorest status conditions for CDR524 configuration.Performance change may such as be caused by the change of power, voltage and heat (PVT) situation.This delay last the performance that may affect communication link, and the maximum clock frequency that can be used for communication link may be limited.If the delay configured is too short, then may create multiple time clock for single code element, this may cause the step-out between transmitter and receiver.If postpone oversize, then symbol time may be overlapping, causes clock recovery circuitry to break down thus or be that two symbol section generate individual pulses.
Fig. 6 comprises the schematic block diagram 600 of some aspect that the clock in explanation 3 line, 3 phase decoder devices generates.The signaling status of other wires in the signaling status of each wire in three signal conductor 310a, 310b and 310c and this three wires 310a, 310b and 310c compares by one group of differential receivers 602a, 602b and 602c.In described example, the signaling status of wire 310a and 310b compares by the first differential receivers 602a, the state of wire 310b and 310c compares by the second differential receivers 602b, and the state of wire 310a and 310c compares by the 3rd differential receivers 602c.As described herein, the signaling status of at least one wire in wire 310a, 310b and 310c changes at each symbol boundaries place.Correspondingly, when the output of at least one differential receivers in differential receivers 602a, 602b and 602c changes in each symbol section end, state change detecting circuit 604 can detect the generation that signaling status changes.
Some signaling status changes and can be detected by single differential receivers 602a, 602b or 602c, and other signaling statuss change and can be detected by two or more differential receivers in differential receivers 602a, 602b and/or 602c.In one example, the signaling status of two wires or relative status can not change after code element changes, and the output of differential receivers 602a, 602b or 602c of correspondence also can not change after code element changes.In another example, wire can be in the first identical state to the wire of two in 602a, 602b and/or 602c in very first time interval, and these two wires can be in the second identical state in the second time interval, can not change after phase transition to make the output of corresponding differential receivers 602a, 602b or 602c.Correspondingly, clock forming circuit 606 can comprise signaling status change detecting circuit and logic 604, and this signaling status change detecting circuit and logic 604 monitor when the output of all differential receivers 602a, 602b and 602c occurs to determine that signaling status changes.This clock forming circuit can generate receive clock 608 based on the transformation of detected signaling status.
Signaling status change on different conductor 310a, 310b and/or 310c can occur at different time or be detected.Can change according to the type of the signaling status change occurred the detection timing of signaling status change.Explain orally in the simplified timing diagram 650 that this variable result provides in figure 6.Be only for the purpose of understanding says clearly, represent that the mark 622,624 and 626 of the output of signaling status change detecting circuit 604 and/or differential receivers 602a, 602b and 602c is assigned different height.The relative height of mark 622,624 and 626 with to generate for clock or the voltage of data decode or current level, polarity or weighted value do not have particular kind of relationship.Sequential chart 650 has explained orally the impact of the timing of transitions be associated with the code element transmitted on three wires 310a, 310b and 310c.In sequential chart 650, the transformation between some code elements can cause period reliably can catch variable Capture window 630a, 630b, 630c, 630d, 630e, 630f and/or 630g (being referred to as code element Capture window 630) of code element.The number of detected signaling status change and their relative timing can cause the shake of clock signal 608.
The size changeability of code element window 630 and the shake that is associated can partly be caused by the electrical specification of wire 310a, 310b and 310c, as in the simple examples 700 described in Fig. 7 explain orally.Fringe time may by signal rise or fall time changeability and/or the testing circuit caused by the variation in manufacturing process tolerance limit, voltage and current source and stability and working temperature be variable affects.Larger fringe time changeability is attributable to there is different voltage or current level in 3 phase signalings.Depict " voltage-level " example of simplification in Fig. 7, it has explained orally the fringe time in single wire 310a, 310b or 310c.First code element (Sym n) 702 can to transmit in the symbol section ending at time 722 place, the second code element (Sym n+1) can transmit in the symbol section ending at time 724 place, and third yard unit (Sym n+2) 706 can to transmit in the symbol section ending at time 726 place, the 4th code element (Sym n+3) 708 transmission start in the time 726.First of threshold voltage 718 and/or 720 spended times can be reached postpone to detect after 712 from by the transformation of the determined state of the first code element 702 to the state corresponding to the second code element 704 being attributable to the voltage in wire 310a, 310b or 310c.This threshold voltage can be used to the state determining wire 310a, 310b or 310c.Second of one of threshold voltage 718 and/or 720 institute spended time can be reached to postpone after 714 detection from by the transformation of the determined state of the second code element 704 to the state of third yard unit 706 being attributable to the voltage in wire 310a, 310b or 310c.The 3rd of threshold voltage 718 and/or 720 spended times can be reached postpone to detect after 716 from by the transformation of the first 706 determined states of third yard to the state of the 4th code element 708 being attributable to the voltage in wire 310a, 310b or 310c.
As depicted, the 3rd postpones 716 can be shorter than the first delay 712, and second postpones 714 and can be most long delay.Second postpones 714, and to can be most long delay be because state 0 is non-driving condition and voltage in wire 310a, 310b or 310c can drift about towards threshold value 720 lentamente, and first postpones 712 and second and postpone 716 and be associated by the transformation being actively pulled to-1 and+1 state respectively with wherein wire 310a, 310b or 310c.
Fig. 8 be explanation 3 line, 3 communicate in an example of link 6 kinds may the constitutional diagram 800 that changes of phase place-polarization state and 30 kinds of possible states.Possible state 802,804,806,812,814 and 816 in constitutional diagram 800 comprises the state shown in diagram 450 of Fig. 4.As shown in example states element 820, often kind of state 802,804,806,812,814 and 816 in constitutional diagram 800 comprises the field 822 of the signaling status that (transmitting on wire 310a, 310b and 310c respectively) signal A, B and C is shown, and the field 824 of the result after deducting wire voltage by differential receivers (differential receivers 602a, 602b, 602c of describing in such as Fig. 6) is shown.Such as, in state 802 (+x), wire A=+1, wire B=-1 and wire C=0, thus produce output (A-B)=+ 2, the output (B-C)=-1 of differential receivers 602b and the output (C-A)=+ 1 of differential receivers 602c of differential receivers 602a.As this constitutional diagram explain orally, transformation done by state change detecting circuit system 604 judges may level based on 5 kinds that are produced by differential receivers 602a, 602b and 602c, and it comprises-2 ,-1,0 ,+1 and+2 voltage statuss.
Fig. 9 is the diagram that the simplification eye pattern that can generate from the overlap of multiple symbol section 902 is shown.Signal limited proportionality 904 represents the ambiguity time period, and wherein variable signal elevating time hinders coding reliably.Status information can be determined in " eye pattern opening " 906, should represent that wherein code element was stablized and the time period that can be received reliably and decode by " eye pattern opening " 906.In one example, can determine that eye pattern opening 906 starts at ending 912 place of signal limited proportionality 904, and terminate at termination 914 place of symbol section 902.In the example that Fig. 9 describes, can determine that eye pattern opening 906 starts at ending 912 place of signal limited proportionality 904, and terminate at time 916 place that the signaling status of connector 310a, 310b, 310c and/or the output of three differential receivers 602a, 602b and 602c start to change over next code element of reflection.
The maximal rate being configured for the communication link 220 that N phase is encoded may be subject to signal limited proportionality 904 compared to the restriction lasted receiving signal eye diagram opening 906.The minimum period of symbol section 902 may be subject to explaining orally with such as Fig. 5 demoder 500 in or Fig. 6 clock forming circuit 606 in the constraint of tight design margin that is associated of ce circuit 524.Different signaling status changes and can be associated from the different variations of the signal fringe time corresponding to two or more wires 310a, 310b and/or 310c, cause the output of differential receivers 602a, 602b and the 602c in receiver equipment to change for the different time of symbol boundaries 908 and/or speed thus, the input wherein to differential receivers 602a, 602b and 602c starts to change at symbol boundaries 908 place.The larger potential difference receiving signal fringe time between the output of multiple differential receivers 602a, 602b and 602c in receiver equipment needs to realize delay element usually in ce circuit 524.The cycle in minimum delay that this delay element can have exceedes the limited proportionality time 904.In one example, can in figure 6 shown in state change detecting circuit 604 and/or clock forming circuit 606 in one or more in delay element is provided.The maximum delay time that this delay element provides is non-extensible exceedes the closed sides of eye pattern opening 906 along 916.In some instances, the maximum delay time that provides of this delay element is non-extensible exceedes the beginning of next symbol section at time 914 place.When with faster data transfer rate, compared with symbol section 902, eye pattern opening 906 can become less, and code element changes variable impact can determine maximum symbol transfer rate.
Any single transformation last unlikely crossover signal limited proportionality (t Δ J) 904 gamut because unlikely occur between single code element tour minimum may signal fringe time and maximum possible fringe time.In one example, for likely code element change, time of the first zero crossing 910 that signal limited proportionality 904 can be detected by the output at differential receivers 602a, 602b or 602c and the time of last zero crossing 912 detected in the output of differential receivers 602a, 602b or 602c are defined.The fringe time observed in the output of differential receivers 602a, 602b and 602c may correspond to and after the input of the driver 308 to this connector and/or wire 310a, 310b or 310c, reaches in connector and/or wire 310a, 310b or 310c the time that NextState spends.Can determine to grow most based on signal conductor and/or the characteristic of connector 310a, 310b or 310c and the type of involved state transfer may fringe time.In one example, the longest possibility fringe time can be determined by the rise or fall time of one or more signal.Rising and falling time can be determined by the essence of original and/or end-state and voltage level.Usually, the longlyest may to correspond to by the transformation between the state that actively drives and non-driving condition by fringe time.
The high t of limited proportionality 904 Δ Jvalue can cause the design difficulty be associated with ce circuit 524 or clock forming circuit 606 to increase.Such as, clock forming circuit 606 can adopt the delay element or the timer that are exported the first zero crossing triggering of 602a, 602b and 602c by three differential receivers.The output state of all these three differential receivers 602a, 602b and 602c possibly cannot be sampled safely before all differential receivers 602a, 602b and 602c have reached its end-state, and this end-state can be defined by eye pattern opening 906.Correspondingly, this timer can preferably expire soon after the ending 912 of limited proportionality 904, now the exportable clock edge being used to sample to the output of these three differential receivers 602a, 602b and 602c of clock forming circuit 606.
In some equipment, the delay element in ce circuit 524 may be subject to the puzzlement of the variation (PVT variation) of manufacturing process, circuit power voltage and die temperature, and may generate the delay of marked change.In such systems, even if the nominal operating conditions of ce circuit 524 is generally arranged in the generated clock edge, middle somewhere of eye pattern opening 906 in design to guarantee that clock edge still occurs after the ending 912 of limited proportionality 904 and before the beginning 916 of the limited proportionality to next code element under worst condition PVT effect.Ensure that the design difficulty of the ce circuit 524 of clock edge in eye pattern opening 906 may occur when limited proportionality 904 is larger compared to eye pattern opening 906.Such as, typical delay element can produce and change the length of delay of 2 times under all PVT conditions, and eye pattern opening 906 must be greater than limited proportionality 904 can be selected to make non-adjustable length of delay.
In some instances, can based on the input change of one or more drivers 308 (see Fig. 3) of transfer circuit with observed by the output of differential receivers 502 (see Fig. 5) in receivers to or the corresponding transformation expected between maximum timing calculate lasting of limited proportionality 904.In other instances, change for all code elements, the maximum difference between last time 914 changed that in the output of receiver 502, modified limited proportionality 916 can be defined as first time 918 changed of the output of a receiver 502 and the output of other receivers 502.
According to some aspect disclosed herein, the ratio that scrambler can be adapted to the symbol section 902 making to be occupied by limited proportionality 904 minimizes and makes the highest percentage of the symbol section 902 occupied by eye pattern opening 906.In one example, the timing of the signaling status transformation when symbol boundaries 910,914 occurs or before occurring on amendment one or more signal conductor 310a, 310b and/or 310c (see Fig. 3) can be changed for some code element.Such as, in scrambler 300, the priori (prior state knowledge) of the concrete N phase symbolic states 802,804,806,812,814 or 816 in coherent code element can be used to predict whether should adjust the timing that one or more N phase driver exports in symbol boundaries 908,914 place between this coherent code element.Also can determine adjustment mode based on prior state knowledge.These adjustment may affect one or more the output in driver 308, and can make adjustment by code element basis.These adjustment can comprise in advance or postpone the transformation of some driver output signal.In some instances, these adjustment can comprise, based on which kind of transformation, the priori (priori transformation knowledge) occurred is added pre-enhancing in code element transformation place of some type to some driver output selectivity.As a result, the edge output from differential receivers 602a, 602b and the 602c in receiver equipment can more accurately about time alignment.
Priori changes knowledge can comprise sign connector to the information of the response of state transfer.This type of information can from the model of connector, driver and receiver and by using these modeling communication links to obtain the response of various types of transformation.In some instances, priori transformation knowledge can comprise the posterior infromation obtained from the test performed at physical equipment and communication link.Priori changes knowledge and can calibrate based on the difference between simulation and measurement result.Priori changes knowledge can comprise the posterior infromation provided during Dynamic System by receiver.
According to some aspect, the less change on signal conductor 310a, 310b and 310c and/or between the fringe time of the output of differential receivers 602a, 602b and 602c can provide significantly larger design margin when the ratio of the symbol section 902 occupied by limited proportionality 904 is minimized.In one example, ce circuit 524 can benefit from the larger timing tolerance supplied by the one or more delay elements used in ce circuit 524.In another example, the maximum symbol transfer rate that M line N communicates link 220 can be minimized in the ratio of the symbol section 902 occupied by limited proportionality 904 and the ratio of the symbol section 902 occupied by eye pattern opening 906 is maximized time improve significantly.
According to some aspect of the present disclosure, by individually considering that each code element changes and optionally to postpone or transformation in advance on one or more signal conductor to reduce the variation of limited proportionality 904 significantly at transmitter place.In some instances, the detection circuitry in transmitter can be adapted to the fringe time determining to change expectation or the calculating be associated with code element.In one example, transmitter can determine whether lasting of limited proportionality 904 or 916 exceedes predetermined maximum or threshold time period.If limited proportionality 904 or 916 exceedes maximum or threshold time period, then the one or more signal can be shifted to an earlier date or be postponed to reduce the limited proportionality 904 or 916 of this code element transformation at receiver place.Maximum or threshold time period based on the tolerance limit of the symbol transmission rate of specifying or expect, ce circuit 524 and/or can be determined for the tolerance limit that other circuit in transmitter or receiver define.Maximum or threshold time period can be defined by the appointment of acquisition eye pattern opening 906 or expect minimum lasting.The shake that maximum or threshold time period can be defined by the receive clock making to derive from institute's transmission signal minimizes.Limited proportionality 904 or 916 can one or more signal can by advance or Delay time reduce significantly.
Figure 10 explains orally according to the transformation of some aspect disclosed herein in advance and the reduced graph 1000 of some aspect postponed.This example depicts three output signals 1002,1004 and 1006, but will understand, and the concept about Figure 10 description is applicable to more than other communication interfaces three signal conductor or connector transmitting code element equally.Transmitter can comprise module or circuit 1010, and this module or circuit 1010 can be configured in advance and/or postpone one or more signal 1002,1004,1006 and produce with the output obtaining the differential receivers (or other receivers) be calculated as in receiver equipment the one group of signal 1032,1034,1036 minimizing limited proportionality.In one example, can shift to an earlier date or postpone one or more signal at transmitter place to aim in time (see Fig. 6, and see the sequential chart 650 in Fig. 6) to make transition detection signal 602a, 602b and 602c.When the corresponding edges in signal 602a, 602b and 602c occur in predefined maximum or threshold value aim in the period time, signal 602a, 602b and 602c can aim in time.Maximum or threshold value is aimed at the period and based on the tolerance limit of the symbol transmission rate of specifying or expect, ce circuit 524 and/or can be determined for the tolerance limit that other circuit in receiver define.Maximum or the threshold value aligning period can be defined by the appointment of acquisition eye pattern opening 906 or expect minimum lasting.Maximum or the threshold value aligning period can be defined by the shake in receive clock 526 is minimized.
In this example, three signals 1002,1004,1006 are provided to the corresponding input 1012,1014,1016 of Circuits System 1010, Circuits System 1010 is configured to the one or more signals optionally shifting to an earlier date and/or postpone in these signals 1002,1004,1006, and produces output signal 1032,1034,1036 at output 1022,1024,1026 place.As shown in input timing Figure 102 0, the input signal 1002,1004,1006 described comprises the transformation 1008 between two symbol section 1040 and 1042.In the first symbol section 1040, signal 1002,1004,1006 is corresponding to having value { "+x " code element 802 (see Fig. 8) of+1 ,-1,0}.In the second symbol section 1042, signal 1002,1004,1006 is corresponding to having value { "+z " code element 806 of-1,0 ,+1}.Only for explanation object, can suppose that the transformation between " 0 " signaling status and "+1 " or "-1 " signaling status changes the soonest, and the transformation of " 0 " signaling status that arrives is most slow-speed change.In some instances, the relative velocity of the transformation between signaling status can be different.
In advance/delay circuitry 1010 can be configured to most slow-speed varying signal and/or postpone the fastest convert signals and change to make receiver generate in the limited proportionality of shortening in advance.In this example, in advance/delay circuitry 1010 can determine that the transformation transformation probably receiver place generation the slowest transition detection and first signal 1002 in of transformation probably in the fastest transition detection of receiver place generation, secondary signal 1004 on the 3rd signal 1006 does not probably produce the soonest or the slowest transition detection at receiver place.In one example, in advance/delay circuitry 1010 can be provided as the output signal 1032,1034,1036 of each version of these three input signals 1002,1004,1006, and the transformation wherein in secondary signal 1034 changes 1028 relative to code element and is shifted to an earlier date, and the 3rd signal is delayed by relative to code element transformation 1028.In some instances, the transformation in the first signal 1032 can be delayed or early by make the transformation in all output signals 1032,1034,1036 produce the transition detection with the edge close alignment of chip clock at receiver place.In other instances, at least one signal in these three output signals 1032,1034 and/or 1036 is not delayed or early by, and is applied to shifting to an earlier date or postponing to be calculated as the aligning of acquisition transition detection and do not consider the chip clock that receiver uses of other output signals 1032,1034,1036.That is, the one or more signals be sent in the signal 1032,1034,1036 of receiver can be shifted to an earlier date relative to other signals 1032,1034,1036 and/or be postponed to make each edge be aimed at more closely when being received by differential receivers 602a, 602b and 602c.Shifting to an earlier date or postpone some decision exported can based on the raw symbol state of value before or after code element transformation.
Figure 11 be explain orally can be used to by the signal 1012,1014 and 1016 that transmits on multi-thread interface in advance/block diagram of the example of delay circuit 1100.In advance/delay circuit 1100 can be included in Figure 10 in advance/delay circuitry 1010 in.Each signal in signal 1012,1014 and 1016 processes respectively by delay cell 1002a, 1002b and 1002c.In one example, each delay cell 1002a, 1002b and 1002c can be manipulated into and an integer unit delay period is applied to corresponding input signal 1012,1014,1016, as with reference to the first input signal 1012 in greater detail.First input signal 1012 is provided to the many tapped delay lines 1112 comprising multiple series connection delay element, and wherein these delay elements provide the version through postponing progressively of input signal 1012.Each delay element can be associated with the unit delay period.Multiplexer 1114 receives each delayed version of input signal 1012 and controls one of each delayed version providing input signal 1012 as output signal 1022 by selection input 1110.Select signal 1110 can be provided as the binary number corresponding with the delay cell number will added to input signal 1012.In some instances, one or more combinational logic gate (obtaining the propagation delay that is associated by these) can be used to realize the delay element of many tapped delay 1112.In other instances, the delay element of many tapped delay 1112 can use trigger to realize, and trigger provides the delay corresponding with the cycle of the clock signal driving this trigger.In other instances, the delay element of many tapped delay 1112 can use analog delay element to realize.
The selection signal 1110 that multiplexer 1114 can be provided by decision logic 1104 controls.Decision logic 1104 can by the signaling status corresponding to three input signals 1012,1014,1016 of next symbol section 1040 (see Figure 10) with correspond to the signaling status (it is stored in register or trigger 1106) that three of current symbol interval 1042 output signal 1022,1024,1026 and compare.Decision logic 1104 can determine the type that the boundary between code element 1040,1042 changes for the signal that every bar wire 310a, 310b, 310c estimate, and can determine whether limited proportionality 904 can exceed threshold value or maximum period by expectability.Decision logic 1104 can provide selects signal 1110 for controlling to process in each unit 1102a, 1102b and 1102c the multiplexer 1114 of one of these three signals 1012,1014,1016.In one example, programmable unit 1102a, 1102b and 1102c can be provided for each signal in these three signals 1012,1014,1016.In another example, programmable unit 1102a, 1102b and/or 1102c can be provided for two signals in these three signals 1012,1014 and/or 1016, and another signal 1012,1014 or 1016 is delayed by set time section.In a rear example, these two unit 1102a, 1102b and/or 1102c can be used to timing relative to the 3rd signal 1012,1014 or 1016 with fixed delay to adjust the timing of two signals in these three signals 1012,1014 and/or 1016.
Other ways can be realized.In one example, one or more driver 310 " driving " optionally can be driven to export to reach necessary transformation fast by the high intensity that drives when changing and starting.Remove or reduce this after can having expired the two-way time between this tour, after this transformation completes and/or on cable and assist.Interim fierce driving " driving " exports the power consumption that can reduce in driver.Except shifting to an earlier date between tour or postponing except edge, also can perform interim driving and " not drive " output.
Figure 12 is representative may change and can be employed one group of sequential chart 1200 of simplification example of the timing adjustment improving signaling performance from the first state to the second state.Original state can be negative load condition, and it is likely converted to another kind of negative load condition or is converted to non-driving condition.Difference before and after sequential chart 1202,1212 and 1222 signal explained orally shown in this picture group table 1250 changes between differential receivers 602a, 602b and 602c place measurable signal conductor 310a, 310b and 310c (being respectively signal A, B and C).Sequential chart 1202 and 1252 relates to from code element (+x) 802 to code element (– x) transformation of 812, wherein signal A is from+1 state transfer to-1 state, and signal B is from-1 state transfer to+1 state, and signal C remains on 0 state.Correspondingly, first differential receivers 602a can record difference+2 and after transformation 1206, record difference-2 before transformation 1206, second differential receivers 602b can record difference-1 and after transformation 1204, record difference+1 before transformation 1204, and the 3rd differential receivers 602c can record difference-1 and record difference+1 after transformation 1204 before transformation 1204.In this example, change to have both 1204 and 1206 in time close, be attributable to the zero crossing that end-state is negative load condition.
Sequential chart 1212 and 1254 relates to the transformation from code element (+x) 802 to code element (+y) 804, and wherein signal A is from+1 state transfer to 0 state, and signal B is from-1 state transfer to+1 state, and signal C is from 0 state transfer to-1 state.Correspondingly, first differential receivers 602a can record difference+2 and after transformation 1216, record difference-1 before transformation 1216, second differential receivers 602b can record difference-1 and after transformation 1214, record difference+2 before transformation 1214, and the 3rd differential receivers 602c can record difference-1 and after transformation 1218, record difference-1 (in fact without transformation) before transformation 1218.In this example, the zero crossing that 1214 and 1216 have the separately remarkable time period is changed.It may be relate to two signals with final negative load condition and AB and change 1216 because BC changes 1214 and relate to a signal with final non-driving condition that this difference occurs.Correction action can be taked by the operation of scrambler 306 (see Fig. 3) or other circuit (such as line drive 308) at transmitter place.In one example, the transformation of signal A starts can be shifted to an earlier date (1260) with the transformation of signal for faster A relative to signal B, and what obtain differential receivers 602a (its comparing signals A and B) thus exports transformation sooner.The transformation of signal C starts also to be shifted to an earlier date (1262) and occurs to prevent transition, because signal A and C both changes and signal A and C compares by differential receivers 602c.
Sequential chart 1222 and 1256 relates to the transformation from code element (+x) 802 to code element (+z) 806, and wherein signal A is from+1 state transfer to-1 state, and signal B is from-1 state transfer to 0 state, and signal C is from 0 state transfer to+1 state.Correspondingly, first differential receivers 602a can record difference+2 and after transformation 1226, record difference-1 before transformation 1226, second differential receivers 602b can record difference-1 and after transformation 1228, record difference-1 (in fact without transformation) before transformation 1228, and the 3rd differential receivers 602c can record difference-1 and record difference+2 after transformation 1224 before transformation 1224.In this example, the zero crossing that 1224 and 1226 have the separately remarkable time period is changed.This difference is attributable to CA and changes 1224 and relate to both and all have signal A and C of final negative load condition and AB and change 1226 and relate to a signal (signal B) with final non-driving condition.Correction action can be taked typically via the scrambler 306 according to adaptation in some disclosed herein, driver 308 or other circuit at transmitter place.Such as, the transformation of signal B starts can be shifted to an earlier date (1264) with the transformation of signal for faster B relative to signal A, and what obtain differential receivers 602a (its comparing signals A and B) thus exports transformation sooner.The transformation of signal C starts also to be shifted to an earlier date (1266) and occurs to prevent transition, because signal A and C both changes and signal A and C compares by differential receivers 602c.
The example explained orally in Figure 12 describes+x Dao – x ,+x and aims to the transformation of these three kinds of state transfer of+z to+y and+x.During the situation occurred in these three kinds of state transfer 18 kinds of may reside in kind of the possible state transformation of 30 shown in Fig. 8 change, and similar correction action can be taked to change to accelerate these additivities by transmitter.The example explained orally respectively describes to these signals when signal A and B is transformed into 0 state do not driven in advance 1260 and 1264.In some instances, transmitter can change the rising edge of delay " B " driver output during 1254 to aim to the detection of these state transfer at such as+x to+y.Transmitter may alternatively or additionally increases the rise or fall time with the signal not driving final purpose state.Such as, the pre-emphasis circuit in one or more driver can be activated or interim stronger driver can be used initially signal is driven into " driving " state.Similar techniques can be applied to+x to+z state transfer.
Optionally advance signal A, B and/or C is carried out by handling the one or more clocks being used for carrying out signal generation timing in transmitters.In one example, can the state of counting wire 310a, 310b or 310c one or more dock cycles be used to accelerate to make this transformation less when lasting before changing.In another example, can the state that wire 310a, 310b or a 310c are added in one or more additional clock circulation to be lasted to postpone this transformation before changing.Usually, the timing of transmitter adjustable subsequent symbol changes beginning to take into account the dock cycles being added or abandoning with delay or signal for faster.
Relate to wire 310a, 310b or 310c and be converted to the fringe time of non-driving condition by initially driving wire 310a, 310b or 310c to accelerate towards non-driving condition.In some instances, passive or active block can be used wire 310a, 310b and/or 310c to be pulled to predetermined " neutrality " voltage level and obtain non-driving condition.
Figure 13 explains orally the concept map 1300 adopting and can be configured to the hard-wired simplification example of the device of the treatment circuit 1302 performing one or more function disclosed herein.According to various aspect of the present disclosure, treatment circuit 1302 can be used to realize the element or any part of element or any combination of element that recover to postpone calibration for three phase clock disclosed herein.Treatment circuit 1302 can comprise one or more processor 1304, and it is controlled by certain combination of hardware and software module.The example of processor 1304 comprises: microprocessor, microcontroller, digital signal processor (DSP), field programmable gate array (FPGA), programmable logic device (PLD) (PLD), state machine, sequencer, gate control logic, discrete hardware circuit and other be configured to perform in the disclosure the various functional appropriate hardware described in the whole text.This one or more processor 1304 can comprise execution specific function and the application specific processor that can be configured, strengthen or be controlled by one of software module 1316.Such as, this treatment circuit 1302 can be configured to as being adapted to the Code And Decode of disposal to data for the processor in one or more transmitted over wireless networks.This one or more processor 1304 configures by the combination of the software module 1316 loaded during initialization, and is configured further by the one or more software module 1316 of load or unload during operation.
In explained orally example, treatment circuit 1302 can use by bus 1310 vague generalization the bus architecture that represents realize.Depend on embody rule and the overall design constraints for the treatment of circuit 1302, bus 1310 can comprise interconnect bus and the bridge of any number.Various electrical chain is connected together by bus 1310, comprises one or more processor 1304 and stores 1306.Store 1306 and can comprise memory devices and mass-memory unit, and can computer-readable medium be called as herein.Bus 1310 also can link other circuit various, such as timing source, timer, peripherals, voltage stabilizer and management circuit.Bus interface 1308 can provide the interface between bus 1310 and transceiver 1312.Transceiver 1312 is provided for the means communicated with other device various by transmission medium.Depend on the essence of this device, also can provide user interface 1318 (such as, keypad, display, loudspeaker, microphone, operating rod), and this user interface directly or by bus interface 1308 can be coupled to bus 1310 communicatedly.
Processor 1304 can be in charge of bus 1310 and general process, comprises the execution to the software be stored in computer-readable medium (it can comprise storage 1306).At this on the one hand, treatment circuit 1302 (comprising processor 1304) can be used to realize any one in method disclosed herein, function and technology.Storage 1306 can be used to the data that storage of processor 1304 is handled when executive software, and this software can be configured to realize any one in method disclosed herein.
One or more processors 1304 in treatment circuit 1302 can executive software.Software should be construed broadly into mean instruction, instruction set, code, code segment, program code, program, subroutine, software module, application, software application, software package, routine, subroutine, object, can executive item, execution thread, code, function, algorithm etc., no matter it is that to address with software, firmware, middleware, microcode, hardware description language or other terms be all like this.Software can reside in storage 1306 by computer-reader form or reside in outer computer computer-readable recording medium.Computer-readable medium and/or storage 1306 can be non-transient computer-readable mediums.Exemplarily, non-transient computer-readable medium comprises: magnetic storage apparatus (such as, hard disk, floppy disk, magnetic stripe), CD (such as, compact disc (CD) or digital multi dish (DVD)), smart card, flash memory device (such as, " flash drive ", card, rod, or Keyed actuator), random access memory (RAM), ROM (read-only memory) (ROM), programming ROM (PROM), erasable type PROM (EPROM), electricity erasable type PROM (EEPROM), register, removable dish, and any other can by computer access and the software of reading and/or the suitable media of instruction for storing.Exemplarily, computer-readable medium and/or store 1306 also can comprise carrier wave, transmission line and any other can by computer access and the software of reading and/or the suitable media of instruction for transmitting.Computer-readable medium and/or storage 1306 can reside in outside in treatment circuit 1302, in processor 1304, at treatment circuit 1302 or distribute across the multiple entities comprising this treatment circuit 1302.Computer-readable medium and/or storage 1306 may be implemented in computer program.Exemplarily, computer program can comprise the computer-readable medium in encapsulating material.Those skilled in the art will recognize that how to depend on that embody rule and the overall design constraints be added on total system realize providing in the disclosure best in the whole text described functional.
Storing 1306 can maintain with can the software that maintain and/or organize such as loading code section, module, application, program, and it can be called as software module 1316 in this article.Each be included in installation in software module 1316 or contribute to the instruction and data of runtime images 1314 when to be loaded on treatment circuit 1302 and to be performed by one or more processor 1304, runtime images 1314 controls the operation of one or more processor 1404.When being performed, some instruction can make treatment circuit 1302 perform function according to some method described herein, algorithm and process.
Some in software module 1316 can be loaded during treatment circuit 1302 initialization, and the configurable treatment circuit of these software modules 1,316 1302 is to realize the execution of various function disclosed herein.Such as, the internal unit of some software module 1316 configurable processors 1304 and/or logical circuit 1322, and ALARA Principle is to the access of external unit (such as, transceiver 1312, bus interface 1308, user interface 1318, timer, math co-processor etc.).Software module 1316 can comprise control program and/or operating system, itself and interrupt handling routine and the mutual and access controlled the various resources provided by treatment circuit 1302 of device driver.These resources can comprise storer, processing time, access, user interface 1318 etc. to transceiver 1312.
One or more processors 1304 for the treatment of circuit 1302 can be multi-functional, and some thus in software module 1316 are loaded and are configured to the different instances performing difference in functionality or identical function.The one or more processor 1304 additionally can be adapted to the background task that managing response is initiated in the input from such as user interface 1318, transceiver 1312 and device driver.In order to support the execution of multiple function, the one or more processor 1304 can be configured to provide multitask environment, and each function thus in multiple function is embodied as the task-set of being served by one or more processor 1304 as required or by expectation.In one example, multitask environment can use timesharing program 1320 to realize, timesharing program 1320 transmits the control to processor 1304 between different task, and each task returns to timesharing program 1320 by the control of one or more processor 1304 when completing any unsettled operation and/or in response to input (such as interrupting) thus.When task has the control to one or more processor 1304, treatment circuit be effectively exclusively used in by the function be associated with controlling party task for object.Timesharing program 1320 can comprise operating system, round-robin basis shifts the major cycle of control, divide according to the prioritization of each function and match the function of control of one or more processor 1304 and/or the drives interrupts formula major cycle by being supplied to disposal function to the control of one or more processor 1304 and responding to external event.
Figure 14 explains orally the process flow diagram according to the coding method of some aspect of the present invention.The method can be performed by equipment 202,230, and this equipment 202,230 can be a kind of assembly of device.In step 1402, equipment 202,230 can to determine the every a pair consecutive code unit in multiple code elements of transmitting on three or more connectors between difference.Difference between every a pair consecutive code unit can be relevant with the signaling status of these three or more connectors.These three or more connectors can comprise at least three wires and at least one wire is in non-driving condition between the transmission period of each code element.
In step 1404, based on this difference, equipment 202,230 can estimate that this is to lasting between the limited proportionality at the symbol boundaries place between coherent code element.
In step 1406, equipment 202,230 lasting between this limited proportionality can be estimated as the operation of the one or more drivers revising these three or more connectors when exceeding threshold time period to reduce lasting between this limited proportionality.Each code element can be a kind of signaling status in each connector definition at least three kinds of signaling statuss in these three or more connectors.Equipment 202,230 aims at by making two or more outputs of the state transfer testing circuit in receiver the operation revising the one or more driver in time.This state transfer testing circuit can be configured to the signaling status comparing each pair of connectors different in these three or more connectors.Make to comprising, transformation to be occurred within the time period being less than threshold time period in time.
In one example, equipment 202,230 initiates to initiate state transfer on the first connector to revise the operation of the one or more driver before corresponding state changes to make driver by configuring one or more delay on the second connector.
In another example, equipment 202,230 initiates to initiate state transfer on the first connector to revise the operation of the one or more driver after corresponding state changes to make driver by configuring one or more delay on the second connector.
In another example, equipment 202,230 postpones by configuring one or more delay to make driver relative to initiating corresponding state change on the second connector or initiates in advance state transfer on the first connector to revise the operation of the one or more driver.
In another example, equipment 202,230 can lasting between this limited proportionality be estimated as when exceeding threshold time period by postponing or initiating the operation that state transfer revises the one or more driver in advance at least one connector.Equipment 202,230 lasting between this limited proportionality can be estimated as suppression delay or advanced condition transformation on these three or more connectors when being less than threshold time period.
In another example, equipment 202,230 lasting between this limited proportionality can be estimated as when exceeding threshold time period and actively drives connector to revise the operation of the one or more driver by the period at least partially between this limited proportionality.Equipment 202,230 lasting between this limited proportionality can be estimated as when being less than threshold time period and to be suppressed to drive this connector when this transmits the second code element in coherent code element.
In one example, equipment 202,203 by determine each connector in these three or more connectors relative to the signaling status fringe time of symbol boundaries and estimate the output of each differential receivers in multiple differential receivers at this symbol boundaries and receiver place change between delay to estimate lasting between this limited proportionality.Each differential receivers in the plurality of differential receivers can be coupled to each pair of connectors different in these three or more connectors.
Figure 15 is the diagram 1500 of the hard-wired simplification example explaining orally the device adopting treatment circuit 1502.Treatment circuit 1502 can with by bus 1520 vague generalization the bus architecture that represents realize.Depend on embody rule and the overall design constraints for the treatment of circuit 1502, bus 1520 can comprise interconnect bus and the bridge of any number.The various electrical chains comprising one or more processor and/or hardware module (by processor 1516, module or circuit 1504,1506 and 1508, can be configured to drive the line drive 1512 of connector or wire 1514 and computer-readable recording medium 1518 to represent) are connected together by bus 1520.Bus 1520 also can link other circuit various, such as timing source, peripherals, voltage stabilizer and management circuit.In one example, bus 1520 provides the access to ce circuit 1524, and this ce circuit 1524 can cooperate with interface circuit 1512 to generate receive clock and the code element caught from multi-thread interface 1514.
Processor 1516 can comprise microprocessor, controller, digital signal processor, sequencer, state machine etc.General process is responsible for by processor 1516, comprises the software performing and be stored on computer-readable recording medium 1516.This software makes treatment circuit 1502 perform above for the various functions that any specific device describes when being performed by processor 1516.Computer-readable recording medium 1518 also can be used to store the data handled when executive software by processor 1516.Treatment circuit 1502 comprises at least one module in module 1504,1506,1508 and 1510 further.Module 1504,1506,1508 and/or 1510 can be run in processor 1516 software module, resident/to be stored in software module in computer-readable recording medium 1518, be coupled to one or more hardware module of processor 1516 or its certain combination.
In one configuration, device 1500 for radio communication comprises the module or circuit 1504 that are configured to determine the difference that the signaling status of these three or more connectors 1514 between the every a pair consecutive code unit in the multiple code elements will transmitted on three or more connectors 1514 is relevant, be configured to estimate that this is to the module of lasting between the limited proportionality at the symbol boundaries place between coherent code element or circuit 1506 based on this difference, and be configured to operation that lasting between this limited proportionality be estimated as the one or more drivers revising these three or more connectors when exceeding threshold time period to reduce the module of lasting between this limited proportionality or circuit 1510.Each code element can be a kind of signaling status in each connector definition at least three kinds of signaling statuss in these three or more connectors.Device 1500 can comprise the module of data and/or circuit 1508 that transmit on these three or more connectors 1514 for encoding and/or decoding and CDR1524 or other circuit for receiving and/or transmit code element on these three or more connectors 1514.Such as, the treatment circuit 1302 (see Figure 13) being configured to operate as certain combination of processor 206 or 236, physical layer driver 210 or 240 and storage medium 208 and 238 can be used to realize aforementioned modules or circuit 1504,1506,1508,1510.
Should be understood that the concrete order of each step in disclosed process or level are the explanations of exemplary way.Should be understood that based on design preference, can the concrete order of each step or level in these processes of layout again.Appended claim to a method presents the key element of various step with example order, and and does not mean that and be defined to given concrete order or level.
Description before providing is to make any person skilled in the art all can put into practice various aspects described herein.The various changes of these aspects will be easily understood by those skilled, and generic principles can be applied to other aspects as defined in this article.Therefore, aspect shown by claim not intended to be are defined to herein, but the four corner consistent with linguistic claim should be awarded, wherein to the citation unless specifically stated otherwise of the singulative of key element, otherwise and not intended to be represents " have and only have one ", but " one or more ".Except non-specifically is stated in addition, otherwise term " some " refers to one or more.The key element of the various aspects that the disclosure describes in the whole text is that equivalents in the current or known from now on all structures of those of ordinary skill in the art and functionally is clearly included in this by citation, and to be intended to contain by claim.In addition, any content disclosed herein all also not intended to be is contributed to the public, and no matter whether such disclosing is described by explicitly in detail in the claims.Device should be interpreted as without any claim element and add function, unless this element be use phrase " for ... device " come clearly describe.

Claims (30)

1. a data transmission method, comprising:
Difference between determining the every a pair consecutive code unit in multiple code elements of transmitting on three or more connectors, wherein said difference is relevant with the signaling status of described three or more connectors;
Estimate that this is to lasting between the limited proportionality at the symbol boundaries place between coherent code element based on described difference; And
The operation of one or more drivers of described three or more connectors is revised to reduce lasting between described limited proportionality when lasting between described limited proportionality is estimated as and exceedes threshold time period,
Wherein each code element be in described three or more connectors each connector definition at least three kinds of signaling statuss in a kind of signaling status.
2. the method for claim 1, it is characterized in that, the operation revising described one or more driver makes two or more outputs of the state transfer testing circuit in receiver aim in time, and wherein said state transfer testing circuit is configured to the signaling status of each pair of connectors different in more described three or more connectors.
3. the method for claim 1, is characterized in that, the operation revising described one or more driver comprises:
Configure one or more delay to initiate to initiate state transfer on the first connector before corresponding state changes on the second connector to make described driver.
4. the method for claim 1, is characterized in that, the operation revising described one or more driver comprises:
Configure one or more delay to initiate to initiate state transfer on the first connector after corresponding state changes on the second connector to make described driver.
5. the method for claim 1, is characterized in that, the operation revising described one or more driver comprises:
Configure one or more delay with make described driver relative on the second connector, initiate corresponding state change and postpone or initiate state transfer on the first connector in advance.
6. the method for claim 1, is characterized in that, the operation revising described one or more driver comprises:
Postpone when lasting when between described limited proportionality is estimated as and exceedes described threshold time period or at least one connector, initiate state transfer in advance; And
Suppress when lasting when between described limited proportionality is estimated as and is less than described threshold time period to postpone on described three or more connectors or advanced condition transformation.
7. the method for claim 1, is characterized in that, the operation revising described one or more driver comprises:
Period at least partially when lasting when between described limited proportionality is estimated as and exceedes described threshold time period between described limited proportionality actively drives a connector; And
Suppressed when this transmits the second code element in coherent code element when lasting when between described limited proportionality is estimated as and is less than described threshold time period to drive a described connector.
8. the method for claim 1, is characterized in that, estimates that lasting between described limited proportionality comprises:
Determine the signaling status fringe time of each connector in described three or more connectors relative to described symbol boundaries; And
Estimate the output of each differential receivers in multiple differential receivers at described symbol boundaries and receiver place change between delay,
Each differential receivers in wherein said multiple differential receivers is coupled to each pair of connectors different in described three or more connectors.
9. the method for claim 1, is characterized in that, described three or more connectors comprise at least three wires, and at least one wire is in non-driving condition between the transmission period of each code element.
10. an equipment, comprising:
The device of the difference between determining the every a pair consecutive code unit in multiple code elements of transmitting on three or more connectors, wherein said difference is relevant with the signaling status of described three or more connectors;
For estimating that based on described difference this is to the device lasted between the limited proportionality at the symbol boundaries place between coherent code element; And
The operation of one or more drivers of described three or more connectors is revised to reduce the device lasted between described limited proportionality when being estimated as exceeding threshold time period for lasting between described limited proportionality,
Wherein each code element be in described three or more connectors each connector definition at least three kinds of signaling statuss in a kind of signaling status.
11. equip as claimed in claim 10, it is characterized in that, the device of the described operation for revising described one or more driver is configured to make two or more outputs of the state transfer testing circuit in receiver to aim in time, and wherein said state transfer testing circuit is configured to the signaling status of each pair of connectors different in more described three or more connectors.
12. equip as claimed in claim 10, it is characterized in that, the device of the described operation for revising described one or more driver is configured to:
Configure one or more delay and initiate state transfer to make described driver on the first connector in the very first time, the described very first time is different from second time of to initiate on the second connector when corresponding state changes.
13. equip as claimed in claim 10, it is characterized in that, the device of the described operation for revising described one or more driver is configured to:
Postpone when lasting when between described limited proportionality is estimated as and exceedes described threshold time period or at least one connector, initiate state transfer in advance; And
Suppress when lasting when between described limited proportionality is estimated as and is less than described threshold time period to postpone on described three or more connectors or advanced condition transformation.
14. equip as claimed in claim 10, it is characterized in that, the device of the described operation for revising described one or more driver is configured to:
Period at least partially when lasting when between described limited proportionality is estimated as and exceedes described threshold time period between described limited proportionality actively drives a connector; And
Suppressed when this transmits the second code element in coherent code element when lasting when between described limited proportionality is estimated as and is less than described threshold time period to drive a described connector.
15. equip as claimed in claim 10, it is characterized in that, described for estimating that the device lasted between described limited proportionality is configured to:
Determine the signaling status fringe time of each connector in described three or more connectors relative to described symbol boundaries; And
Estimate the output of each differential receivers in multiple differential receivers at described symbol boundaries and receiver place change between delay,
Each differential receivers in wherein said multiple differential receivers is coupled to each pair of connectors different in described three or more connectors.
16. equip as claimed in claim 10, it is characterized in that, described three or more connectors comprise at least three wires, and at least one wire is in non-driving condition between the transmission period of each code element.
17. 1 kinds of devices, comprising:
Multiple connectors of two equipment communicatedly in coupling terminal; And
Treatment circuit, it is configured to:
Difference between determining the every a pair consecutive code unit in multiple code elements of transmitting on three or more connectors, wherein said difference is relevant with the signaling status of described three or more connectors;
Estimate that this is to lasting between the limited proportionality at the symbol boundaries place between coherent code element based on described difference; And
The operation of one or more drivers of described three or more connectors is revised to reduce lasting between described limited proportionality when lasting between described limited proportionality is estimated as and exceedes threshold time period,
Wherein each code element be in described three or more connectors each connector definition at least three kinds of signaling statuss in a kind of signaling status.
18. devices as claimed in claim 17, it is characterized in that, the operation of described one or more driver is modified so that two or more outputs of the state transfer testing circuit in receiver are aimed in time, and wherein said state transfer testing circuit is configured to the signaling status of each pair of connectors different in more described three or more connectors.
19. devices as claimed in claim 17, it is characterized in that, described treatment circuit is configured to:
Configure one or more delay with make described driver relative on the second connector, initiate corresponding state change and postpone or initiate state transfer on the first connector in advance.
20. devices as claimed in claim 17, it is characterized in that, described treatment circuit is configured to:
Postpone when lasting when between described limited proportionality is estimated as and exceedes described threshold time period or at least one connector, initiate state transfer in advance; And
Suppress when lasting when between described limited proportionality is estimated as and is less than described threshold time period to postpone on described three or more connectors or advanced condition transformation.
21. devices as claimed in claim 17, it is characterized in that, described treatment circuit is configured to:
Period at least partially when lasting when between described limited proportionality is estimated as and exceedes described threshold time period between described limited proportionality actively drives a connector; And
Suppressed when this transmits the second code element in coherent code element when lasting when between described limited proportionality is estimated as and is less than described threshold time period to drive a described connector.
22. devices as claimed in claim 17, it is characterized in that, described treatment circuit is configured to:
Determine the signaling status fringe time of each connector in described three or more connectors relative to described symbol boundaries; And
Estimate the output of each differential receivers in multiple differential receivers at described symbol boundaries and receiver place change between delay,
Each differential receivers in wherein said multiple differential receivers is coupled to each pair of connectors different in described three or more connectors.
23. devices as claimed in claim 17, is characterized in that, described three or more connectors comprise at least three wires, and at least one wire is in non-driving condition between the transmission period of each code element.
24. 1 kinds of processor readable storage mediums with one or more instruction, described instruction makes at least one treatment circuit described when being performed by least one treatment circuit:
Difference between determining the every a pair consecutive code unit in multiple code elements of transmitting on three or more connectors, wherein said difference is relevant with the signaling status of described three or more connectors;
Estimate that this is to lasting between the limited proportionality at the symbol boundaries place between coherent code element based on described difference; And
The operation of one or more drivers of described three or more connectors is revised to reduce lasting between described limited proportionality when lasting between described limited proportionality is estimated as and exceedes threshold time period,
Wherein each code element be in described three or more connectors each connector definition at least three kinds of signaling statuss in a kind of signaling status.
25. storage mediums as claimed in claim 24, it is characterized in that, when the operation of described one or more driver is modified, two or more outputs of state transfer testing circuit in receiver are aimed in time, and wherein said state transfer testing circuit is configured to the signaling status of each pair of connectors different in more described three or more connectors.
26. storage mediums as claimed in claim 24, is characterized in that, comprise further and make at least one treatment circuit described perform the instruction of following action:
Configure one or more delay with make described driver relative on the second connector, initiate corresponding state change and postpone or initiate state transfer on the first connector in advance.
27. storage mediums as claimed in claim 24, is characterized in that, comprise further and make at least one treatment circuit described perform the instruction of following action:
Postpone when lasting when between described limited proportionality is estimated as and exceedes described threshold time period or at least one connector, initiate state transfer in advance; And
Suppress when lasting when between described limited proportionality is estimated as and is less than described threshold time period to postpone on described three or more connectors or advanced condition transformation.
28. storage mediums as claimed in claim 24, is characterized in that, comprise further and make at least one treatment circuit described perform the instruction of following action:
Period at least partially when lasting when between described limited proportionality is estimated as and exceedes described threshold time period between described limited proportionality actively drives a connector; And
Suppressed when this transmits the second code element in coherent code element when lasting when between described limited proportionality is estimated as and is less than described threshold time period to drive a described connector.
29. storage mediums as claimed in claim 24, is characterized in that, comprise further and make at least one treatment circuit described perform the instruction of following action:
Determine the signaling status fringe time of each connector in described three or more connectors relative to described symbol boundaries; And
Estimate the output of each differential receivers in multiple differential receivers at described symbol boundaries and receiver place change between delay,
Each differential receivers in wherein said multiple differential receivers is coupled to each pair of connectors different in described three or more connectors.
30. storage mediums as claimed in claim 24, is characterized in that, described three or more connectors comprise at least three wires, and at least one wire is in non-driving condition between the transmission period of each code element.
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