CN1098818A - Semiconductor integrated circuit, semiconductor device, transistor and manufacture method thereof - Google Patents

Semiconductor integrated circuit, semiconductor device, transistor and manufacture method thereof Download PDF

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Publication number
CN1098818A
CN1098818A CN94104092A CN94104092A CN1098818A CN 1098818 A CN1098818 A CN 1098818A CN 94104092 A CN94104092 A CN 94104092A CN 94104092 A CN94104092 A CN 94104092A CN 1098818 A CN1098818 A CN 1098818A
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semiconductor region
gate electrode
film
semiconductor
mask
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张宏勇
竹村保彦
大沼英人
须泽英臣
鱼地秀贵
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority claimed from JP07110193A external-priority patent/JP3226655B2/en
Priority claimed from JP1488894A external-priority patent/JPH06314786A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Abstract

A kind of thin-film transistor and manufacture method thereof, comprise: to mix with mask and gate electrode is mask, with Alignment Method, impurity is mixed the semiconductor region that there is insulating coating on its surface, after using the mask etch surface insulation layer, with strong illumination gained surface with mixing.The edge at least a element injection island semiconductor district in the carbon nitrogen oxygen group, its concentration is higher than the mean concentration of semiconductor region, to increase the leakage current between the leakage of resistance and minimizing source.Wherein, the marginal portion in control thin film semiconductor district makes it become intrinsic, or identical with the channel formation region conduction type, prevents that gate insulating film punctures in this part.

Description

Semiconductor integrated circuit, semiconductor device, transistor and manufacture method thereof
The present invention relates to the structure and the manufacture method thereof of thin-film semiconductor device.The present invention be more particularly directed to structure and manufacture method thereof as the thin-film transistor (TFT) of the circuit original paper in the thin film integrated circuit.The thin-film transistor that obtains according to method of the present invention can be formed on the insulating substrate of glass substrate for example, perhaps is formed on the semiconductor chip of the substrate that monocrystalline silicon for example makes.
Up to now, thin-film transistor (being designated hereinafter simply as " TFT ") is made in the following manner, thin film semiconductor district (floor of having chance with) is made for island shape part, adopt chemical vapor deposition (CVD) or sputter to form insulating coating thereon, on described insulating coating, form gate electrode again as gate insulating film.
Yet, have found that because its relatively poor step covers, also there is defective in the insulating barrier according to conventional method is formed by CVD or sputter aspect performance, reliability or the rate of finished products of TFT.Fig. 9 has showed a typical TFT who makes by conventional method, comprises vertical view, and along the A-A ' line of first figure and the sectional view separately of B-B '.Referring to Fig. 9, on substrate 151, form a TFT.The thin film semiconductor district is divided into substantial intrinsic channel formation region 152 and N shape extrinsic range (source or the drain region) 153 that is positioned under the gate electrode 157.Semiconductor region is covered by gate insulating film 155.Contact hole runs through layer insulation 159, thereby on impurity range 153 bonding pad 158 is set.
In typical prior art TFT, as can be seen from Figure 9, gate insulating film 155 is poor especially in the covering of the edge of semiconductor region.Say that more specifically the thickness that is provided at the gate insulating film on the edge has only half of flat part.When the island shape semiconductor district was thicker, it is thinner that the thickness of gate insulating film becomes.Along the section of the A-A ' line of gate electrode, relatively poor covering is just clearer and more definite to the adverse effect of performance, reliability and the rate of finished products of TFT.That is the zone 156 that the with dashed lines circle is represented gives special attention, can find that the electric field of gate electrode 157 is collected at this zone, and this is because the thickness of gate insulating film herein only is half of flat part.Naturally, the electric field that puts on this specific region is the twice of flat part.
The thing followed is, when applying voltage for a long time or applying high voltage, the gate insulating film of this specific region just is easy to damage.And positive signal is imposed on gate electrode 157 can reduce transistorized reliability, this is because regional 156 also be to be made by N shape conductive semiconductor, gate electrode 157 and impurity range 158(be the drain region particularly) between the path become conduction.
After gate insulating film was damaged, certain electric charge just was captured.For example, if this moment, negative electrical charge was captured, regardless of the voltage that is applied to gate electrode, the semiconductor of specific region 156 then becomes N shape conduction.Thereby electric current is flowed, thereby damage the performance of TFT between two impurity ranges 158.Yet the voltage that is applied must be reduced to half of ideal value, and TFT is worked under the situation that does not reduce performance.This performance that shows TFT can not be brought into play fully.
In addition, have the TFT of this class shortcoming, because in charging that each manufacturing step produced etc., and be easy to damage, and this causes the decline of rate of finished products.The objective of the invention is to address this is that.
Adopt laser crystallization or laser active (comprising flash lamp annealing) technology, the existing method that manufacturing makes grid be positioned at the top grid type TFT on the active layer comprises, thin film semiconductor district (active layer) is made for island shape part, adopt CVD or sputtering method, form insulating coating thereon, as gate insulating film, form gate electrode thereon, utilize gate electrode, impurity irradiation is at high speed had the structure of dielectric film to its of gained as mask, press self-aligned manner thus, mix dopant and form impurity range in semiconductor region, for example illuminating laser beam is passed through in source and drain region then, make the impurity activation of mixing in the semiconductor region, thereby finish laser active.
But there are several problems in above-named existing method.These problems comprise the increase contact resistance.More particularly, during laser active, part impurity and the material that constitutes the gate insulator on it (as silica etc.) reaction, form compound, as phosphorus (hydrochlorate) glass and Pyrex, perhaps non-stoichiometry oxide semiconductor (as 2: 1 ratios of the ratio nonstoichiometry of contained oxygen of silica and silicon), this is because the result that the nonequilibrium state reaction produces.When subsequent step formed contact, this stoichiometry or non-stoichiometric compound had increased contact resistance.In addition, also can produce the coarse problem of above-mentioned reacted surface that results from.These problems reduce rate of finished products.
Another problem is, owing to the instability of performance descends device reliability.More particularly and since between active period the gate electrode partly shielding effect laser active, the border of mixing extrinsic region often can not sufficiently be activated.Illustrate in greater detail this problem below in conjunction with example.
Referring to Fig. 5, the example of existing laser active technology is described below.At first, on substrate 50, form the underlying insulation film of making by silica etc. 51, form the island shape crystalline semiconductor area of making by silicon etc. 52 thereon.Then, adopt as CVD or sputter, use formation gate insulating films 53 such as silica, use is mixed phosphorus silicon, aluminium, tantalum etc. and is formed gate electrode 54 thereon.Mix after the impurity, adopt the suitable fully high light of laser beam or intensity and laser that synthetic structure is shone.In this method, impurity range 55a and 55b are activated, simultaneously by making the so instantaneous high temperature that is in of this structure, (shown in circular portion P among the figure) locates to produce chemical reaction on the border between semiconductor and the gate insulating film, as previously mentioned, form insulating material, as the compound of phosphorus (hydrochlorate) glass (or Pyrex) with dopant material.In addition, silica forms the non-stoichiometric silicon oxide compounds that has silicon.This method is shown in Fig. 5 (B).
Referring to Fig. 6, the example of another kind of existing laser active technology is described below.This example is with the afore-mentioned difference of Fig. 5, by the anodic oxidation of gate electrode, forms oxide 65 around gate electrode.The existence of anodic oxide coating has caused the off-set construction between gate electrode and the impurity range (preparing to introduce the district of impurity), promptly shown in Fig. 6 (A), can gate electrode be set apart from impurity range x distance, thereby improve the electrical property of TFT.For example, can significantly reduce based on the back-biased leakage current that grid applied.
Yet the foreign ion that the crystalline texture of the part Q of circle is accelerated during doping treatment in this moment Fig. 6 (B) damages, and owing to herein laser beam irradiation abundance inadequately, has also kept un-activation.Therefore, produce many traps energy utmost points at this position, thereby damage device performance, cause the reliability of TFT inferior thus.Another object of the present invention is to be to address these problems.
The invention provides the way that a kind of manufacture method of utilizing semiconductor device solves the problems referred to above, be included under the situation of not removing gate insulating film impurity is mixed structure, after removing gate insulating film, in laser active step subsequently, activate this structure.Since remove gate insulating film during substrate oxide-film and substrate also can be etched, thereby method of the present invention comprises especially and uses mask to introduce impurity, and uses this mask that gate insulating film etc. is carried out selectively etching subsequently.
By this method, under the condition that does not reduce rate of finished products, can successfully finish doping, and can avoid betiding the semiconductor of follow-up laser active step and the reaction between the insulating coating.And, be the situation that TFT is provided with skew for adopting anodic oxidation as shown in Figure 6, the boudary portion of doping also can carry out laser active.To the etched while of gate insulating film, the antianode oxidation is carried out partially-etchedly can realizing above-mentioned purpose.
An alternative embodiment of the invention provides the semiconductor device that is obtained by a kind of method, it is characterized in that comprising, intrinsic semiconductor with high resistivity is provided, semiconductor to the light current district carries out complementation, perhaps makes this semiconductor in light current district have the conduction type identical with channel formation region.Fig. 7 has showed the typical structure of present embodiment of the present invention.Referring to Fig. 7 (A), across near the island shape semiconductor area edge part, a district 114 is set at gate electrode 111, it can be an intrinsic, perhaps has the conduction type identical with channel formation region.This part is corresponding to the impurity range (source and drain region) of existing TFT.As can be seen, TFT of the present invention comprises, do not have thereon in the island shape semiconductor district outside the part of gate electrode, except impurity range (source and drain region) 113, also have part 114, that it comes down to intrinsic or have a conduction type identical with channel formation region.
Another embodiment of the present invention provides the semiconductor device that is obtained by a kind of method, it is characterized in that comprising, by making at least a element in the group that is selected from oxygen, carbon and nitrogen formation, it improves semi-conductive resistance in the light current district in the concentration at this position mean concentration greater than the island shape semiconductor district.Best, the light current district is formed by semi-insulating or insulating compound, and its chemical formula is SixC 1-x(wherein 0＜X＜1), SiO 2-x(0＜X＜2), Si 3N 4-x(0＜X＜4), or SiC xN yO z
An alternative embodiment of the invention provides the TFT that is obtained by a kind of method, the method is characterized in that and comprise, in semiconductor film, make the flush type semiconductor region, with this replace by semiconductor region (referring to Fig. 9, promptly wherein formed the semiconductor region of impurity range corresponding 153 and channel formation region 152 with source and drain region) make island shape part, provide the active layer structure of TFT, i.e. island shape semiconductor part (source and drain region, channel formation region).In other words, the formation of the active layer structure of TFT, not by semiconductor region being made island shape, formed impurity range corresponding and channel formation region in this semiconductor region, but in semiconductor film, directly form each district of origin and drain region and channel formation region function with source and drain region.
Fig. 1 (A) is to 1(E) represented according to embodiment of the invention 1(example 1) method of TFT, the cross-section structure that substep obtains successively made;
Fig. 2 (A) is to 2(D) represented method by another embodiment of the present invention (example 2) system TFT, substep is the cross-section structure of acquisition successively;
Fig. 3 (A) is to 3(D) represented the doping figure etc. of the TFT that makes by example 2 methods;
Fig. 4 (A) is to 4(D) represented that substep is the cross-section structure of acquisition successively by the method for further embodiment of this invention (example 3) manufacturing TFT;
Fig. 5 (A) is to 5(B) represented the substep that obtains by existing TFT manufacture method cross-section structure successively;
Fig. 6 (A) is to 6(B) represented the substep that obtains by another kind of existing TFT manufacture method cross-section structure successively;
Fig. 7 (A) is to 7(H) represented formation according to TFT of the present invention, and make the cross-section structure that the method substep of TFT obtains successively by the present invention;
Fig. 8 (A) is to 8(D) represented that substep is the cross-section structure of acquisition successively by the method for another embodiment of the present invention (example 4) manufacturing TFT;
Fig. 9 has represented the formation of the TFT of prior art;
Figure 10 (A) and 10(B) be TFT electrical property of the present invention and existing TFT electrical property the contrast schematic diagram;
Figure 11 has represented the formation of TFT of the present invention;
Figure 12 (A) is to 12(D) represented that substep is the cross-section structure of acquisition successively by the method for another embodiment of the present invention (example 8) manufacturing TFT;
Figure 13 (A) is to 13(D) represented that substep is the cross-section structure of acquisition successively by the method for another embodiment of the present invention (example 5) manufacturing TFT;
Figure 14 (A) is to 14(D) represented that substep is the cross-section structure of acquisition successively by the method for another embodiment of the present invention (example 10) manufacturing TFT;
Figure 15 (A) is to 15(D) represented that substep is the cross-section structure of acquisition successively by the method for another embodiment of the present invention (example 6) manufacturing TFT;
Figure 16 (A) is to 16(D) represented that substep is the cross-section structure of acquisition successively by the method for another embodiment of the present invention (example 7) manufacturing TFT;
Figure 17 is the profile of TFT of the present invention;
Figure 18 is the vertical view of TFT of the present invention;
Figure 19 is the variation of conductivity and the graph of relation of nitrogen ion dose;
Figure 20 is the variation of transmissivity and the graph of relation of nitrogen ion dose;
Figure 21 (A) is to 21(D) represented that substep is the cross-section structure of acquisition successively by the method for another embodiment of the present invention (example 9) manufacturing TFT;
Figure 22 (A) is to 22(E) represented that substep is the cross-section structure of acquisition successively by the method for another embodiment of the present invention (example 11) manufacturing TFT;
Figure 23 (A) is to 23(B) be calcspar according to the thin film integrated circuit of example 5;
Figure 24 (A) is to 24(D) represented that substep is the cross-section structure of acquisition successively by the method for the embodiment of the invention (example 5) manufacturing TFT.
Below illustrate in greater detail the present invention.
Fig. 7 has shown a typical structure according to the embodiment of the invention.Referring to Fig. 7 (A), near the part of gate electrode 111, a district 114 is set across the edge in island shape semiconductor district, it can be an intrinsic, perhaps has the conduction type identical with channel formation region.This part is corresponding with the impurity range (source and drain region) of the TFT of prior art.As can be seen, TFT according to the present invention comprises, do not have thereon in the island shape semiconductor district outside the part of gate electrode except impurity range (source and drain region) 113, also have part 114, that it comes down to intrinsic or have a conduction type identical with channel formation region.
Fig. 7 (B) has represented TFT according to another embodiment of the present invention.Except the shape in island shape semiconductor district, this structure is in fact with identical shown in Fig. 7 (A).In the figure, electrode 116 links to each other with leaking with the source respectively.
In conjunction with Figure 10, we can say the effect of bright setting area 114, this district 114 can be intrinsic or have a conduction type identical with channel formation region.The structure of prior art TFT and equivalent electric circuit thereof are shown in Figure 10 (A).Among the figure character X and Y represent respectively gate electrode across part, as previously mentioned, the gate insulating film of arranging in these parts that are designated as X and Y is thinner than the flat part.Therefore can understand, form parasitic TFT in these parts, shown in equivalent electric circuit with low threshold voltage and proof voltage.
If apply too high voltages at grid, main TFT by add high pressure damage before, these parasitic TFT will be destroyed and be become simple conductor.Therefore, the leakage current between source and the leakage, perhaps the leakage current between source and the grid will become big.
Opposite with above-mentioned prior art TFT, the present invention is according to the structure shown in Figure 10 (B), and it is with equivalent electric circuit.TFT is similar with prior art, also forms parasitic TFT according to TFT of the present invention.But, comprised high resistance and connected with parasitic TFT, prevent that with this source or drain voltage directly are added on TFT.When setting has the district of the conduction type identical with channel formation region,, thereby formed the potential barrier of equivalent resistance by PN junction because the conduction type in this district is opposite with leakage with the source.
Therefore as can be seen, even when too high voltages is added on gate electrode, the insertion dead resistance of connecting with source and leakage has reduced voltage, thereby avoids betiding the infringement of parasitic TFT.As a result, adopt structure of the present invention, just can solve the problem that poor device reliability, low rate of finished products and device performance degenerate.
Adopt Fig. 7 (C) to 7(H) method of brief description, just can realize TFT of the present invention.Referring to Fig. 7 (C), on substrate, form island shape semiconductor district 110.Usually, this semiconductor region comes down to intrinsic, but the also weak N type conduction or the semiconductor region of P-type conduction.
After having formed gate insulating film, on synthetic structure, gate electrode is set, shown in Fig. 7 (D).Then, impurity is mixed the district 112 shown in Fig. 7 (E).Use the method, form the impurity range 113 and 114 that is clipped between impurity range and the gate electrode.Best, district 114 is provided with as follows, and its size is in the scope of 2 to 5 μ m.The conduction type in this district 114 is identical with the island shape semiconductor district, if the island shape semiconductor district is an intrinsic, this district 114 also should be an intrinsic.The resistivity in district 114 typically is 10 6Ω-cm or higher.
The structure of Fig. 7 (G) expression is the structure of removing the gate electrode of TFT from the structure of Fig. 7 (F).Can know by this figure and to find out that the conduction type in the district 114 shown in Fig. 7 (F) is identical with channel formation region 115.In source and leakage, form electrode 116, finally make the complete TFT shown in Fig. 7 (H).
Relate to the additional step of photoetching according to the method for present embodiment, for example on substrate, only form a kind of situation in N raceway groove and the P channel TFT.But from other advantage of using method of the present invention to obtain, i.e. the increase of You Yi device performance, reliability and rate of finished products, processing step can not cause obstacle to using this method.
The present invention is applied to comprise in the manufacturing of complementary metal oxide semiconductors (CMOS) (CMOS) circuit of TFT of N raceway groove and P raceway groove, can shows superiority of the present invention more significantly.The simplest method of making cmos circuit comprises, at first mixes N type or p type impurity on the whole surface of substrate, after required part is sheltered, mixes the impurity of films of opposite conductivity then, and its quantity should make first conductive type impurity be neutralized.This method is hereinafter referred to as " first method ".But first method can cause for the disequilibrium between N channel TFT such as proof voltage, threshold voltage and the P channel TFT sometimes, and this is because for example the dosage that requires of p type island region is 5 * 10 15Cm -2, and the dosage that N type district requires is 1 * 10 15Cm -2
More accurate method comprises, forms first mask and N type or p type impurity are mixed structure, and then form second mask and the impurity introducing of impurity conduction type opposite that conduction type and previous step are mixed.This method is hereinafter referred to as " second method ".Because the concentration of N type impurity and the concentration of p type impurity can be set independently of each other, reckon with that this method can realize being used for the desirable device of cmos circuit.But, to compare with first method, this method needs the additional step of photoetching.
When method of the present invention is applied to the manufacturing of the N of cmos circuit and two kinds of TFT of P type, mask must be set independently at every turn, introduce N and p type impurity by given pace respectively mutually.So, from two kinds of methods, select second method natch.Though the manufacturing step of second method is than the first method complexity, as mentioned above, second method can better provide the device of premium properties.As can be seen, because the present invention has further increased intrinsic advantage in the second approach, thereby offset shortcoming fully, so the additional step of photoetching no longer becomes the shortcoming of this method.
Figure 11 has represented the typical TFT that makes by the method for third embodiment of the invention, and it is observed by the top side, and along the profile of top view figure line A-A ' and B-B '.Referring to Figure 11, on substrate 511, form TFT.The thin film semiconductor district is divided into impurity range (that is, can be the source and the drain region of N type or P-type conduction, be N type conduction in this example) 513 and is positioned at the channel formation region 512 of this film in fact under the gate electrode 517.Semiconductor region is covered by gate insulating film 515.Contact hole runs through interlayer dielectric 519, thereby is provided with bonding pad 518 at impurity range 513.
The prior art TFT difference of TFT of the present invention and Fig. 9 is, be selected from least a element in the group that constitutes by nitrogen, oxygen and carbon, it is mixed the peripheral part in the island shape semiconductor district 510 that is positioned at the gate electrode bottom, promptly distinguish 510 marginal portion, its concentration is higher than the mean concentration of semiconductor region, forms special district 514 with this.For example, semiconductor region nitrogenous mean concentration be 1 * 10 18Cm -3, nitrogen is introduced this special section, should make this district's nitrogen concentration rise to 1 * 10 19Cm -3Or higher, preferably reach 1 * 10 20Cm -3Or higher so that the nitrogen of introducing unit can be well with semiconductor in pasc reaction, form Si 3N 4-x(0＜X＜4).As a result, the resistance in this district 514 can improve significantly.Use oxygen or carbon similarly to handle.Introduce oxygen or carbon, make its concentration reach 1 * 10 19Cm -3More than, can set up high resistance area 514, preferably concentration reaches 1 * 10 20Cm -3More than.
Compare with other channel formation region 512, this measure increases the bandwidth of this special section.Therefore, when high voltage is imposed on gate electrode, can set the field intensity between raceway groove and the lateral edge portions to such an extent that be lower than the field intensity of channel formation region wittingly, to prevent to produce electrical breakdown and leakage current.
Below especially referring to the district 516 in the profile of A-A ' along the line, the effect of this special section 514 is described.Similar with the situation of traditional TFT, the covering gate dielectric film is relatively poor in the marginal portion of semiconductor region.Therefore, apply and be about half low-voltage of ideal value, the dielectric film of this part also is easy to be damaged, thereby forms pin hole or trapped charge.But, be provided with district 514 after because the existence of district's resistance of 514 can reduce the voltage that imposes on gate insulating film.In this mode, gate insulating film can be protected and avoid puncturing.And, because special section 514 is kept apart the marginal portion of impurity range 513 under the gate electrode and channel formation region 512 and semiconductor region, these active layer districts can keep not being subjected in the gate insulating film of semiconductor region marginal portion the accidental pin hole that forms or the influence of trap-charge.
Therefore, can reduce the leakage current between gate electrode and the drain region especially, perhaps the leakage current between source and the leakage.And even when gate insulating film is damaged, said structure also can make the use of TFT not have the problem of device performance and reliability aspect.This shows according to TFT of the present invention can not be subjected to the restriction of its working voltage and use freely, suffers damage because product is more unlikely in the mill, and as electrostatic breakdown, thereby the defect rate in making can reduce.Therefore, rate of finished products also can increase.
The situation that Figure 11 represents is, all introduced nitrogen, carbon and oxygen across the whole marginal portion in the thin film semiconductor district 510 of gate electrode thereon.But, can understand by above-mentioned explanation, only be positioned at a district that is provided with under the gate electrode at least, this requirement is just enough.And, should be specifically noted that, use organic material, as photoresist,, can make mask suffer oxidation and final the disappearance because apply the oxygen of too high dose as mask.In addition, the introducing of nitrogen, oxygen and carbon not only can be by adopting the method for photoetching setting area, but also can determine that the position of introducing element realizes by the use etched self-aligned manner of cutting sth. askew.
Referring to Figure 16, below explanation is according to the example of fourth embodiment of the invention.In structure shown in Figure 16, the active area 407 that comprises source and drain region and channel formation region is set.Part except that active area 407 contains nitrogen, oxygen, carbon and the element of insulation characterisitic is provided for semiconductor as additive.That is the method according to this invention comprises and selectively forms active layer, replaces using forming figure, for example adopts ion to inject, and oxonium ion is injected into the part that is not to do active layer.
In the method, the periphery insulation in active layer district 407 can form TFT by making at least.But, by making all SI semi-insulations except that active area 407, the leakage current that can suppress to be harmful to and the generation of parasitic capacitance, and obtain more positive means.When using silicon as semiconductor, the part that is provided insulation characterisitic can convert light transmissive material to, as silica and silicon nitride.Because these materials are at the visible-range printing opacity, so use glass substrate can make them be used for liquid crystal device.
When using silicon as the semiconductor of active layer in the above-mentioned formation, the part with outside oxonium ion, nitrogen ion or the carbon ion bombardment active layer can make it change silica, silicon nitride or silication silicon into.In that the injection ion of insulated part is provided, with 10 18Cm -3Above dosage is introduced impurity, and best is that dosage is 10 20Cm -3More than.
By nitrogen, carbon or oxygen being mixed the whole marginal portion in the thin film semiconductor district that is positioned at gate electrode one side, as mentioned above, can reduce the voltage that imposes on gate insulating film, prevent to produce the puncture of gate insulating film, improve the reliability of device.
In addition, in the semiconductor film district that constitutes active layer except those, insulated part is set selectively, can be arranged on gate insulating film and gate electrode on the flat surfaces of active layer top side.As a result, provide solution for the problems such as step covering, insulation breakdown and a focusing that solve in making.
Example below in conjunction with indefiniteness illustrates in greater detail the present invention.But, should understand, formation of the present invention is not limited to this.
Embodiment 1
Fig. 1 has represented the profile of the structure that obtains successively according to the method for embodiment of the invention substep.Referring to Fig. 1, on Corning#7059 glass substrate 10, form 2000 by sputter
Figure 941040925_IMG2
Thick silicon oxide film is as counterdie 11.Then, by isoionic CVD deposition of amorphous silicon film thereon, thickness is 200 to 2000 , for example be 1500 in this example Subsequently, by the sputter diaphragm, deposition thickness is 200 to 1000
Figure 941040925_IMG5
Silicon oxide film.Then, resulting structures is annealed, make the amorphous silicon film crystallization.Annealing is to carry out in reducing atmosphere 48 hours, and temperature range is 500 to 600 ℃, especially, and for example at 600 ℃.Can adopt high light, finish crystallization steps as laser beam.Afterwards, thus obtained crystal silicon film is made figure, obtain island shape silicon area 12 thus.
Adopt sputter, silicon oxide deposition film 13 is as gate insulating film, and thickness is 850 to 1500
Figure 941040925_IMG6
, for example thick 1000
Figure 941040925_IMG7
Then, adopt low pressure chemical vapor deposition, deposit contains the silicon fiml of 0.01% to 2% phosphorus, and thickness is 6000 to 8000
Figure 941040925_IMG8
, more specifically, for example thickness is 6000 Best, consecutive deposition silicon oxide film and silicon fiml.Subsequently, synthetic silicon fiml is made figure, form the gate electrode 14 shown in Fig. 1 (A).
15 districts of sheltering except that semiconductor region 12 by plasma doping, adopt photoresist mask 15 and gate electrode 14 as mask with photoresist, and phosphorus is injected into silicon area 12 as impurity.Doping figure in this example is shown in Fig. 1 (C).This doping step is performed such, and adopts hydrogen phosphide (PH 3) as impurity gas, apply 60 accelerating voltages to 110KV, for example 80KV, mixing dosage is 1 * 10 16To 5 * 10 16Cm -2Phosphorus, especially, for example dopant dose is 1 * 10 16Cm -2In the method,, obtain N type impurity range 16a and 16b by Alignment Method corresponding to gate electrode 14.Resulting structures is shown in Fig. 1 (B).
The firm doping step of finishing adopts hydrofluoric acid that the structure that still has mask 15 on it is carried out etching.Use the method, the expose portion on the silicon oxide film 13 is etched.But, to use and note, the silica of underlying insulation film is simultaneously by partly etching.After finishing, etching peels off photoresist.
Then, use the laser radiation activator impurity.This routine used laser is KrF excimer laser, and operation wavelength is 248nm, and pulse duration is 20 to 40 nanoseconds.But, also can use other laser, as work in the XeF excimer laser that wavelength is 353nm, operation wavelength is the XeCl excimer laser of 308nm, operation wavelength is the ArF excimer laser of 193nm.The energy density of the laser beam that applies is 250 to 400mJ/cm 2For example be 300mJ/cm 2, 2 to 10 emissions are for example to each position, Secondary Emission.Substrate can be heated to 200 to 450 ℃ temperature range during the laser radiation.But should be noted that by heated substrate and can change best laser energy density.Resulting structures is shown in Fig. 1 (D).
After the activator impurity step, adopt plasma CVD, silicon oxide deposition film 17 is as interlayer insulating film, and thickness is 5000 to 8000 , for example thickness is 6000
Figure 941040925_IMG11
Then, contact hole is set, adopts multilayer film to form bonding pad 18a and 18b, multilayer film is by thick 1000 to 2000
Figure 941040925_IMG12
Metallic material film such as titanium nitride and thick 5000 to 10000
Figure 941040925_IMG13
The aluminium film form.Subsequently, in pressure is 0.1 to 1atm nitrogen atmosphere, synthetic structure is carried out 30 to 120 minutes annealing, temperature is 250 to 400 ℃, more specifically, is in the nitrogen atmosphere of 1atm at pressure, carries out 30 minutes annealing, and temperature is 350 ℃.The NMOS semiconductor circuit of making like this is shown in Fig. 1 (E).
Embodiment 2
Fig. 2 has represented the method by another embodiment of the present invention, the profile of the structure that substep obtains successively.Referring to Fig. 2, on Corning#7059 glass substrate 20, form thick 2000 by sputter Silicon oxide film, as counterdie 21.Then, adopt plasma CVD, deposition of amorphous silicon film thereon, thickness is 200 to 2000
Figure 941040925_IMG15
, be 1000 for example in this example
Figure 941040925_IMG16
Then, under reducing atmosphere, synthetic structure is carried out 48 hours annealing, temperature is 600 ℃, makes the amorphous silicon film crystallization.Finish crystallization steps and can adopt high light, as laser beam.Subsequently, synthetic crystal silicon film is made figure, obtain island shape silicon area 22.The size of single island shape silicon area is 30 μ m * 30 μ m.
By sputter, silicon oxide deposition film 23 is as gate insulating film, and thickness is 800 to 1500
Figure 941040925_IMG17
, for example thick is 1000 Then, contain the aluminium film of 2% silicon by sputtering deposit, thickness is 3000 to 6000
Figure 941040925_IMG19
, more specifically, for example thickness is 6000
Figure 941040925_IMG20
Best, the silicon of interpolation 0.5 to 5% or 0.2 to 2% copper in the aluminium film.If do not add this impurity in the aluminium film, in the heat treatment step that in 250 to 350 ℃ of temperature ranges subsequently, carries out, can produce hillock on the film.Equally preferably silicon oxide film and the deposit continuously of aluminium film.Have been found that after deposited film, in 100 to 300 ℃ of temperature ranges, the aluminium film is heat-treated, can avoid producing hillock.Subsequently, use phosphoric acid that gained aluminium film is carried out etching, form gate electrode 24.Afterwards, apply synthetic structure, make figure with photosensitive polyimides (Photoneece), 250 to 350 ℃ temperature range, for example 300 ℃ cure, selectively form the polyimides mask, provide the anodic oxidation step to use.Be used for forming the part of contact after mask is arranged in the step or be used for separating the part (although not showing the polyimides mask among the figure) of connection.
Then, synthetic structure is carried out anodic oxidation.Dissolving tartaric acid in 1,2 ethylene glycol (ethylene glycol), preparation concentration is 1 to 5%.The pH value that for example 3% solution, and interpolation ammoniacal liquor is controlled synthetic solution is 7.Like this, use substrate 20, constitute negative electrode, apply electric current, carry out anodic oxidation thus by lead 24 by the gauze platinum electrode in the above-mentioned solution as anode.
Anodic oxidation is performed such, and applies electric current at first as follows, and with 3 to 6V/ branches, the speed that routine 4V/ divides is boosted, and when voltage reaches 200 to 250V values, makes voltage remain on this voltage.More specifically, for example voltage keeps constant at 220V, reaches 20 μ m/cm up to current density 2Therefore, forming thickness is 1500 to 3000 Pellumina, for example thick is 2000
Figure 941040925_IMG22
Which is provided with the part of polyimides mask, not shown, because the mask effect of polyimides still keeps not oxidation.Anodic oxidation was carried out 40 to 70 minutes, typically be 55 minutes.The structure that is obtained is shown in Fig. 2 (A).
Then, except island shape silicon area 22, photoresist mask 26 is formed figure.This mask is formed the shape shown in Fig. 3 or Fig. 3 (C), so that gate electrode 24 is doped across the part portion of the step of silicon area 22.
Because the gate insulating film 23 at these step parts is relatively poor than approaching and covering, these parts usually form defective, as pin hole, thereby produce parasitic TFT along these stepped portions.Therefore, often run into the problem of leakage current in existing device, this is considered to result from the parasitic TFT of generation like this.On the contrary, adopt above-mentioned doping figure, stepped portions is got rid of outside TFT according to device of the present invention.According to said method, the device of the present invention problems such as electric current of can stopping a leak.
Then, use aforementioned mask, impurity such as phosphorus and boron injection silicon area 22 by plasma doping.The injection of phosphorus can be adopted hydrogen phosphide (PH 3) as impurity gas, apply 65 to 100KV accelerating voltage, for example 80KV.The injection of boron can be adopted diborane (B 2H 6) as impurity gas, apply 50 to 80KV accelerating voltage, for example 65KV.The dosage of introducing impurity is 1 * 10 16To 5 * 10 16Cm -2, be 3 * 10 as dosage particularly 16Cm -2In this way, with respect to gate electrode part self-aligned manner, form impurity range 27a and 27b, gate electrode partly comprises gate electrode 24 and anodic oxide coating 25.Impurity range forms so-called shift state, and promptly along continuous straight runs leaves gate electrode 24 1 segment distance Y.So the structure that obtains is shown in Fig. 2 (B).
Subsequently, it is partially-etched to use 26 pairs of silicon oxide films of mask 23 to carry out.Remove mask 26 after finishing etching.When forming mask 26 as Fig. 3 (A) shown in during figure, so that the part except that semiconductor region 22 all is exposed, and the substrate silicon oxide film is pressed and example 1 similar mode (can be referring to Fig. 1 (D), wherein circle position X is expressed out), and is etched.But,, shown in Fig. 3 (C), then do not exist following substrate silicon oxide film carried out etched problem when exposure portion is limited to semiconductor region 22.Fig. 3 (B) and 3(D) provided after the etch-gate dielectric film 23 by the obtainable TFT of each figure.Fig. 2 (C) has shown the section of the TFT shown in Fig. 3 (D).Find out that easily anodic oxide coating (aluminium oxide) 25 is an etched and recessed segment distance Z simultaneously, thereby expose the border of impurity range, shown in Fig. 2 (C).
Then, make the impurity activation of injection by laser annealing.Laser beam also shines the boundary member of impurity range, carries out enough effectively activating.This routine used laser is KrF excimer laser, and operation wavelength is 248nm, and pulse duration is 20 nanoseconds.The energy density that laser beam applies at irradiating surface is 250 to 400mJ/cm 2, 300mJ/cm for example 2Substrate can be heated to 200 to 400 ℃ temperature range during the laser radiation, for example 300 ℃.
After laser annealing step, by plasma CVD, silicon oxide deposition film 28 is as interlayer insulating film, and thickness is 5000 to 8000 , for example thickness is 5000
Figure 941040925_IMG24
And, by sputter, deposit tin indium oxide (ITO) film, thickness is 500 to 1500
Figure 941040925_IMG25
, for example 800
Figure 941040925_IMG26
The ITO film of so deposit is made figure, provide ITO pixel capacitors 2P with this.Then, at interlayer insulating film 28 contact hole is set, adopts multilayer film to form bonding pad 30a and 30b, multilayer film comprises metal material, as titanium oxide and aluminium.Resulting structures carried out 30 to 120 minutes annealing in nitrogen atmosphere, pressure is 0.1 to 1atm, and temperature more specifically, is carried out 30 minutes annealing at 250 to 400 ℃ in nitrogen atmosphere, and pressure is 1atm, and temperature is 350 ℃.The semiconductor circuit of making like this is shown in Fig. 2 (D).
Embodiment 3
Fig. 4 has shown the structural profile that obtains successively by the method for another embodiment of the present invention substep.Referring to Fig. 4, on Corning#7059 glass substrate 40, form 2000 by sputter
Figure 941040925_IMG27
Thick silicon oxide film is as basement membrane 41.Then, by plasma CVD, deposition of amorphous silicon film, thickness are 200 to 2000
Figure 941040925_IMG28
, for example be 1500 in this example And by sputter, the silicon oxide deposition film is as diaphragm, and thickness is 200 to 1000 , specifically be 200 in this example Then, under reducing atmosphere, synthetic structure is carried out 48 hours annealing, make the amorphous silicon film crystallization, temperature is 600 ℃.Can use high light such as laser beam to carry out crystallization.Subsequently, the gained crystal silicon film is made figure, thereby obtain island shape silicon area 42P and 42N.
Afterwards, by sputter, silicon oxide deposition film 43 is as gate insulating film, and thickness is 800 to 1500
Figure 941040925_IMG32
, for example thick 1000
Figure 941040925_IMG33
Then, by sputter, deposit contains the silicon fiml of 1 to 5% silicon, and thickness is 3000 to 6000
Figure 941040925_IMG34
, more specifically as thick 6000
Figure 941040925_IMG35
Preferred consecutive deposition silicon oxide film and silicon fiml in this example.The aluminium film is formed figure, form gate electrode 44P and 44N, and carry out anodic oxidation by the method identical with example 2, with anodic oxidation (aluminium oxide) film 45P and 45N covering grid electrode surface, each thickness is 1500 to 3000
Figure 941040925_IMG36
, more specifically, for example the anodic oxidation film thickness is 2000
Figure 941040925_IMG37
Synthetic structure is shown in Fig. 4 (A).
Expose semiconductor region 42N separately, 46N shelters the district except that semiconductor region 42N with photoresist.Then, the gate electrode part that adopts photoresist mask 46N and comprise gate electrode 44N and anodic oxide coating 45N by plasma doping, is injected silicon area 42N to phosphorus as impurity as mask, and the used doping figure of this example is shown in Fig. 3 (C).This doping step is performed such, and adopts hydrogen phosphide (PH 3) as impurity gas, institute adds accelerating voltage in 65 to 110KV scopes, for example 80KV is 1 * 10 to mix dosage 15To 8 * 10 15Cm -2Phosphorus, concrete is 2 * 10 as dosage 15Cm -2In this method, obtain N type impurity range 47N.After finishing this doping step, use mask 46N to etch away partial oxidation silicon fiml 43.Resulting structures is shown in Fig. 4 (B).
Then, only expose semiconductor region 42P, 46P shelters the residue position with photoresist simultaneously, and boron is injected silicon area 42P as impurity.Reuse the doping figure shown in Fig. 3 (C) in this example.Inject boron and can adopt diborane (B 2H 6) as impurity gas, institute's fast voltage that applies in 50 to 80KV scopes, 65KV for example.The dosage of the boron of introducing is 1 * 10 15To 80 * 10 15Cm -2, for example dosage is 2 * 10 particularly 15Cm -2In this method, form p type impurity district 47P.Finish after the doping, use mask 46P to etch away partial oxidation silicon fiml 43.Resulting structures is shown in Fig. 4 (C).
Then, adopt the laser radiation activator impurity.This routine used laser is KrF excimer laser, and operation wavelength is 248nm.But, also can use other laser, for example, operation wavelength is the XeF laser thing laser of 353nm, and operation wavelength is the XeCl excimer laser of 308nm, and operation wavelength is the ArF excimer laser of 193nm.The energy density that laser beam applies is 250 to 400mJ/cm 2, 280mJ/cm for example 2, launch for example each position 2 times 2 to 10 times.
After the activator impurity step, adopt tetraethoxysilane (Si(OC 2H 5) 4) (TEOS) as original material, by plasma CVD, silicon oxide deposition film 48 is as interlayer insulating film, thickness is 5000 to 8000
Figure 941040925_IMG38
, for example thick 6000
Figure 941040925_IMG39
Contact hole is set then, adopts the multilayer film that comprises metal material such as titanium nitride and aluminium, form bonding pad 49a, 49b, 49c and 49d.In nitrogen atmosphere synthetic structure is carried out 30 to 120 minutes annealing, pressure is 0.1 as for atm, and temperature more specifically, is carried out 30 minutes annealing at 250 to 400 ℃ in nitrogen atmosphere, and pressure is 1atm, and temperature is 350 ℃.The cmos semiconductor circuit of making like this is shown in Fig. 4 (D).
Embodiment 4
Fig. 8 has shown the structural profile that obtains successively by the method for another embodiment of the present invention substep.Referring to Fig. 8, on Corning#7059 glass substrate 120, form thick 2000 by sputter
Figure 941040925_IMG40
Silicon oxide film as counterdie 121.Then, by plasma CVD, deposition of amorphous silicon film, thickness are 500 to 1500
Figure 941040925_IMG41
, for example be 1500 in this example In addition, by sputter, deposit thick 200
Figure 941040925_IMG43
Silicon oxide film as diaphragm.Then, under reducing atmosphere resulting structures is carried out annealing in 48 hours, make the amorphous silicon film crystallization, temperature is 600 ℃.Can adopt laser for example laser beam carry out crystallization.Then, the gained crystal silicon film is made figure, obtain island shape silicon area 122P and 122N.
Then, by sputter, deposit thick 1000
Figure 941040925_IMG44
Silicon oxide film 123 as gate insulating film, then, by low pressure chemical vapor deposition, deposit contains the silicon fiml of 0.01 to 2% phosphorus, thickness is 6000 to 8000
Figure 941040925_IMG45
, more specifically for example thick 6000
Figure 941040925_IMG46
Best, consecutive deposition silicon oxide film and silicon fiml.Subsequently, resulting structures is made figure, form gate electrode 124P and 124N shown in Fig. 8 (A).
Make with photoresist and 125 shelter semiconductor region 122P, adopt continuum 124N,, phosphorus is injected silicon area 122N as impurity by plasma doping as mask.In addition, metal material and metal nitride can be used as the material of mask 125, as chromium, titanium, titanium nitride and aluminium.This routine used doping figure is shown in Fig. 7 (E).Adopt hydrogen phosphide (PH 3) finish this doping step as impurity gas, institute's fast voltage that applies for example is 80KV in 60 to 90KV scopes, the dosage of introducing phosphorus is 1 * 10 15Cm -2To 8 * 10 15-2, for example be 1 * 10 particularly 15Cm -2In the method, obtain N type impurity range 126N.After finishing the doping step, apply 300W radio frequency (RF) ashing that power carried out, remove Etching mask 125N by depressing at oxygen.
If activate with laser in subsequent step, then the most handy hydrofluoric acid is selectively removed the silica 123 on the silicon area 122N.This measure for prevent during the laser radiation because of the reaction between silica 123 and the silicon area 122N produce on the surface uneven be effectively (Fig. 8 (B)).
125P only shelters semiconductor region 122N with photoresist, uses bonding pad 124P as mask, and boron is injected silicon area 122P as impurity.Adopt the doping figure shown in Fig. 7 (E) in this example once more.Can use diborane (B 2H 6) injecting boron as impurity gas, the accelerating voltage of being executed is at 20 to 70KV scopes, for example 65KV.The boron dosage that mixes is 1 * 10 15To 8 * 10 15Cm -2, concrete is 1 * 10 as dosage 15Cm -2In this method, form p type impurity district 126P.After finishing doping, remove mask 125P against corrosion by ashing.Resulting structures such as Fig. 8 (C).
In reducing atmosphere, under 600 ℃, carry out annealing in 48 hours,, also can finish this step by laser annealing with this activator impurity.This moment, available laser comprised that operation wavelength is the KrF excimer laser of 248nm, and operation wavelength is the XeF excimer laser of 353nm, and operation wavelength is the ArF excimer laser of 193nm.The energy density that laser beam applies is 200 to 350mJ/cm 2, 250mJ/cm for example 2, launch 2 to 10 times, for example each position emission is 2 times.During laser radiation, substrate can be heated to 200 to 450 ℃ of temperature ranges.But, should be noted that when substrate is heated best laser energy changes.
After impurity activation, by plasma CVD, silicon oxide deposition film 127, as interlayer insulating film, thickness is 3000 to 10000
Figure 941040925_IMG47
, for example thick 6000
Figure 941040925_IMG48
Then, opening contact hole runs through the gained film, adopts the multilayer film of metal material such as titanium nitride and aluminium to form bonding pad 128P and 128N.The complete cmos semiconductor circuit of Huo Deing is shown in Fig. 8 (D) like this.
Embodiment 5
Figure 13 represents the continuous section of structure of substep by the technology acquisition of the another kind of embodiment of the present invention.In the embodiment 6 and 7 of bottom, also comprise embodiment 5, the structure of representing TFT by profile, wherein, the structure on the left side is represented the plane (corresponding to the section of cutting open along B-B ' line in Figure 11 and 9) perpendicular to grid, and the structure on the right side represents to be parallel to the plane (corresponding to along the section of cutting open along A-A ' line among Figure 11 and Fig. 9) of grid.With reference to Figure 13, on Corning#7059 glass substrate 230, by sputter formation 2000 Thick silicon oxide film is as counterdie 231.By plasma CVD deposition of amorphous silicon film, thickness is 500 to 1500 thereon , be 1500 in this example
Figure 941040925_IMG51
After previous process steps, pass through sputtering deposit 200 at once
Figure 941040925_IMG52
Thick silicon oxide film is as diaphragm.The structure of gained, 600 ℃ annealing temperature 48 hours, make the amorphous silicon film crystallization at reducing atmosphere.The high light of utilization resemble the laser beam carries out crystallisation step.The crystalline film of above-mentioned acquisition is made figure, so that obtain the silicon area 232a and the 232b of island.Each island silicon area has photoresist mask 233a and 233b thereon.At this corrosion step, use isotropic etching process, for example use the wet corrosion technology of fluoro nitric acid, at semiconductor region formation chamfered edge as shown in the figure.
Utilize resist as mask, nitrogen is mixed semiconductor region by plasma doping.Utilize ammonia (NH in this step 3) or connect ammonia (N 2H 4) as impurity gas, the accelerating voltage of use is 20 to 60KV, 20KV for example, nitrogen mixes.With 1 * 10 15To 5 * 10 16Cm -2Dosage, particularly utilize 1 * 10 16Cm -2Dosage doping nitrogen.In this way, nitrating district 234a, 234b, 234c and the 234d of formation are shown in Figure 13 (A).
In above-mentioned doping step, also nitrogen is entrained in the counterdie 231 simultaneously.So may transform into silicon oxynitride to bottom 231, in follow-up corrosion step, counterdie is corroded so that prevent.
Then, utilize sputtering deposit 1000
Figure 941040925_IMG53
Thick silicon oxide film is as gate insulating film.Subsequently, adopt the low pressure chemical vapor deposition deposit to contain the aluminium film of 2% silicon, thickness is 6000 to 8000
Figure 941040925_IMG54
, especially be 6000
Figure 941040925_IMG55
Best, silicon oxide deposition film and silicon fiml continuously.Then, the aluminium film of gained is made figure, form grid bonding pad 235a and 235b as gate electrode.The surperficial anodic oxidation of aluminium bonding pad is formed oxide-film 236a and 236b.Before carrying out anodic oxidation, form the part of contact zone thereon, utilize light-sensitive polyimide (Photoneece) to selectively form mask.Part at mask does not form anodic oxide coating by anode oxidation process.
In containing the tartaric ethylene glycol solution of 1-5%, carry out anodic oxidation.Form 2000
Figure 941040925_IMG56
Thick oxide layer.Utilize bonding pad 235a and oxide layer 236a as mask,, the phosphorus as impurity is injected into silicon area by plasma doping.Utilize hydrogen phosphide (PH 3) injecting phosphorus as impurity gas, the accelerating voltage of use is 60 to 90KV, for example, 80KV.With 1 * 10 15To 8 * 10 15Cm -2Dosage, as 5 * 10 15Cm -2Dosage, Doping Phosphorus.N type impurity range 237a and 237b shown in Figure 13 (B) have been obtained.
Then, activate the impurity that injects by laser annealing.The laser of Shi Yonging is KrF excimer laser in this example, is 20nsec in the work of 248nm wavelength place, pulse duration.Other available laser comprises XeF excimer laser, in the work of 353nm wavelength place, and XeCl excimer laser, in the work of 308nm wavelength place, ArF excimer laser is worked at 193nm wavelength place.The energy density of using laser beam is 200 to 350mJ/cm 2, for example, 250mJ/cm 2, each position irradiation 2-10 time, for example 2 times.During laser irradiation, substrate can be heated to 200 to 450 ℃ temperature.Yet, should be noted that when heated substrate optimum laser energy density changes.During irradiation laser, on the aluminium surface, keep polyimides mask 237, sustain damage so that prevent the aluminium that exposes.After the irradiation laser step,, can remove the polyimides mask at an easy rate by it is exposed in the oxygen plasma.
The technology of present embodiment is different from embodiment 1 described technology, wherein, the laser of incident is not added to regional 234c and the 234d that injects nitrogen, this zone be positioned at gate electrode below.Therefore, these zones keep low degree of crystallinity, but as a very large resistance, can reduce leakage current effectively according to the technology of present embodiment, and the structure of gained is shown in Figure 13 (C).
Utilize plasma CVD silicon oxide deposition film 238, thickness is 3000 , as interlayer insulating film.Pass insulating barrier and open a contact hole, the multilayer film that utilization resembles the metal material titanium nitride and the aluminium forms bonding pad 239a and 239b.One of bonding pad 239a and bonding pad 235b and impurity range 237b interconnect.Realize the semiconductor circuit shown in Figure 13 (D).
Embodiment 6
Present embodiment relates to the TFT that is arranged on the glass substrate, and wherein, active layer (promptly by channel formation region, the semiconductor layer that source region and drain region constitute) is set in the crystalline silicon film, so that the gate insulating film and the gate electrode of planar structure are provided on active layer.Figure 15 represents that it comprises P-ditch TFT and the N ditch TFT that is provided with by complementary structure by the plane graph of the substep continuous structure of present embodiment technology acquisition.Structure outside the active layer can be made TFT with this by the processes well known manufacturing.
With reference to figure 15(A), on glass substrate 301, form 2000 by sputter
Figure 941040925_IMG58
Thick silicon oxide film is as counterdie 339.Then, utilize plasma CVD deposition of amorphous silicon film 300 thereon, thickness is 1000
Figure 941040925_IMG59
By prior art processes,, can not be provided for the thick amorphous silicon layer of active layer owing to there is the problem of step covering gate dielectric film.Yet, according to the technology of present embodiment, because needn't consider the problem of step covering gate dielectric film, thickness deposition of amorphous silicon film 300 that can be on demand.In addition, utilize thermal annealing or thereon the irradiation laser bundle can make amorphous silicon film 300 crystallizations of gained.In addition, direct deposit crystal silicon film and do not use amorphous silicon film.
Deposit 200
Figure 941040925_IMG60
Thick silicon oxide film 302 is as diaphragm.Then deposit 8000 Thick aluminium lamination is as mask.The aluminium lamination that obtains is made figure, so that the active layer district is set.The structure that obtains is shown in Figure 15 (B), and this structure comprises the aluminium mask 303 and 304 that is used to limit the active layer district that is arranged on above the silica diaphragm 302.In the ion implantation step of back, silicon oxide film prevents that amorphous silicon surfaces is subjected to because the damage that nitrogen ion bombardment causes.Resist can be used in place in aluminium mask 303 and 304.
With the surface of the total of nitrogen ion bombardment resulting structures, the nitrogen ion is injected into those zones except that the zone that mask 303 and 304 are arranged above it.Accelerating voltage and 6 * 10 with 40KV 17Cm -2Dosage carry out ion and inject.The accelerating voltage value can be selected in 20 to 80KV scope, yet too high voltage can cause the major injury of film, and too low voltage is unsuitable for thick amorphous silicon film 300, because like that low voltage can not be fully film converted to insulator than lower part.The mixing dosage and be preferably 4 of nitrogen ion * 17Cm -2More than.This is after under 600 ℃ of conditions this film being carried out 48 hours thermal annealing, by measuring the conductivity (Scm of this film -1), the conclusion that obtains according to the data that obtain.Relation between conductivity and the ion dose as shown in figure 19.Can see that the active area that does not carry out the ion injection provides one about 10 -5Scm -1Conductivity, insulation layer necessarily provides a conductivity preferably, 10 -11Scm -1Perhaps littler.
So, by the nitrogen ion being injected in the zone that is not the active layer district, obtain two active layers 306 and 308 of TFT.Yet, two active layers 306 and 308 are arranged in the silicon nitride film.Therefore, the zone that becomes insulation layer provides nitrogenize silicon area 305 in this structure, shown in Figure 15 (B).
After removing mask 303 and 304, this structure 600 ℃ of following thermal annealings 48 hours, is made active layer district 306 and 308 crystallizations.By irradiation laser bundle or any desired technology, can carry out crystallization step.Simultaneously, activate the nitrogen ion that mixes in this structure, make zone 305 have insulation characterisitic.Just, when making active layer district crystallization, carry out the annealing of injecting nitrogen ion simultaneously.
After removing silica diaphragm 302, deposit 1000 Silicon oxide film as gate insulating film 307.Because there be not the flat site deposit gate insulating film 307 of step, can solves significantly with step and cover relevant problem.
Then, contain the aluminium film of 2% silicon with the low pressure chemical vapor deposition deposit, thickness is 6000
Figure 941040925_IMG63
, the gained film is made figure, form gate electrode 310 and 311.This gate electrode can be known Si-gate.The surperficial anodic oxidation of the gate electrode of gained, form oxide layer 312 and 313.The length in the skew grid region that is provided with in the later step that forms source region and drain region is decided by the thickness of oxide layer that forms.
Adopt ion inject boron and phosphorus are incorporated into zone that calls PTFT and the zone that calls NTFT respectively thereafter.Obtain p type island region 314 and 316, N type district 317 and 319.Inject by protecting a zone to carry out ion, once just the ion of needs is injected into the zone of appointment.Use the structure of laser beam irradiation gained then, activate the impurity that mixes.So use Alignment Method, obtained to constitute the source region 314 of PTFT active layer and the channel formation region of drain region 316 and PTFT, also obtained to constitute the source region 317 of NTFT active layer and the channel formation region of drain region 319 and NTFT.
After forming silica interlayer dielectric 320, form electrode and metal bonding pad 321,322,323, so that obtain the complete TFT circuit of the complementary structure formed by PTFT and NTFT.On substrate, in the integrated circuit that on glass substrate, is provided with, perhaps in the peripheral circuit of liquid crystal display device, and in the switch element that offers the liquid crystal display device pixel parts, utilize the circuit of this gained especially.
In the structure of present embodiment, gate insulating film 307, gate electrode 310 with 311 and the bonding pad that links to each other with gate electrode can be formed on above the smooth bottom.Therefore, relating to active layer edge part another arena problem concentrated and insulation breakdown may be excluded basically.
Embodiment 7
Present embodiment relates to the TFT that is provided with on the pixel parts of driven with active matrix liquid crystal display device.Figure 16 represents to utilize the continuous section of structure of substep of another embodiment of the present invention technology acquisition.With reference to Figure 16, on glass substrate 401, utilize sputter to form 2000
Figure 941040925_IMG64
Thick silicon oxide film is as counterdie 402.Utilize plasma CVD deposition of amorphous silicon film 403 thereon, thickness is 1000 Needn't necessarily use the plasma CVD deposition of amorphous silicon.Can use any technology in the processes well known that resembles sputter, low pressure hot CVD and the photochemical vapor deposition equally.
Deposit 200 Thick silicon oxide film 404 is as diaphragm.Then deposit 8000
Figure 941040925_IMG67
Thick aluminium lamination, and only the aluminium lamination that obtains is made figure as mask.Mask 405 limits the active layer district of TFT.Under the condition that is similar to embodiment 6,, carry out ion and inject with the whole surface of nitrogen ion bombardment resulting structures.After removing mask 405, carry out thermal annealing with the method for similar embodiment 6, make active layer district 407 crystallizations, simultaneously by activating the nitrogen ion that injects, annealing (further quickening crystallization) insulation layer 406.
With the method identical, form gate electrode 408 with oxidation periphery 409 with embodiment 6.Gate electrode can be well-known Si-gate.Use self aligned method, by ion implanted impurity, it makes injects part and becomes N type conduction, promptly injects phosphonium ion, formation source and drain region 410 and 412 and channel formation region 411, and accelerating voltage is 60KV.And, to source region and drain region 410 and 412 irradiation laser bundles, make its activation.Form interlayer insulating film 412 by silica, then form ITO electrode 416 and metal electrode 414 and 415, finish a complete N-ditch TFT.
The profile structure of representing along A-A ' line in Figure 16 (D) is represented in Figure 17.Figure 18 is simple presentation graphs 6(D) structure that provides.This is the structure of seeing from substrate top.In Figure 18, the profile of B-B ' along the line is provided by Figure 16, and the structure that the figure that A-A ' along the line cuts open represents corresponding to Figure 17.Symbol in Figure 16,17,18 is identical with numeral.Be clear that by Figure 17 the problem that relates to annular section 156 among Fig. 9 is avoided in this structure, because the gate electrode 408 of gate insulating film 407 and expansion forms on smooth zone.Basically, can not be added to highfield partly from gate electrode 408 marginal portion of the channel region of active layer.The basis of this view belongs to basic conception of the present invention, especially, basic conception of the present invention is to form active layer not adopt semiconductor film is made island district (channel formation region of representing) in the profile of Fig. 7, but by making the semiconductor region the zone of removing the appointment active layer have insulation characterisitic.
Figure 20 represents to become by injecting nitrogen ion the observation transmission coefficient (zone 305 among Figure 15 and the zone 406 among Figure 16 and Figure 17) of insulation layer.With 40KV accelerating voltage doping nitrogen ion, under 600 ℃ of conditions, made the ion implanted region thermal annealing 48 hours.Can see by Figure 20, with 3 * 10 17Cm -2Or any zone of higher dosage injecting nitrogen ion, transmission peak wavelength is 380 to 800nm visible light sufficiently.
The above-mentioned fact shows that structure shown in Figure 16 can be used to the pixel parts of driven with active matrix liquid crystal display device well.Just, the insulation layer by the injecting nitrogen ion manufacturing can be retained, because they do not influence the optical characteristics of liquid crystal display device.
As previously mentioned, present embodiment comprises, by material being mixed the semiconductor region except that being appointed as the active layer district, make ion implanted region become insulation layer, limit the active layer district, thus, the relatively poor step that has fundamentally solved by for example gate insulating film, gate electrode, bonding pad and electrode covers the problem that is produced.The semiconductor region of high resistant and transmissive visible light can be provided in addition.This shows the application that can need be used to transmitted light by the device of present embodiment at an easy rate, for example, and the pixel parts of driven with active matrix liquid crystal display device.
Embodiment 8
Figure 12 represents to obtain according to the technology of another embodiment of the present invention the profile of substep continuous structure.With reference to Figure 12, utilize to sputter on the Corning#7059 glass substrate 221, form 2000
Figure 941040925_IMG68
Thick silicon oxide film is as counterdie 221.Utilize plasma CVD deposition of amorphous silicon film thereon, thickness is 500 to 1500
Figure 941040925_IMG69
, for example 1500 Utilize ion microprobe (SIMS) to find that it is 1 * 10 that the amorphous silicon film of deposit contains nitrogen concentration 18Cm -2Perhaps lower.Pass through sputtering deposit 200 after step is finished in front at once
Figure 941040925_IMG71
Thick silicon oxide film is as diaphragm.Then the structure of gained was annealed 48 hours under 600 ℃ of temperature at reducing atmosphere, make the amorphous silicon film crystallization.Also can utilize high light to carry out the step of crystallization resemble the laser beam.The crystal silicon film that obtains is made figure, so that obtain island silicon area 222a and 222b.At each diaphragm 223a and 223b are arranged above the island silicon area.These diaphragms prevent that island silicon area lithography step afterwards from being stain.
Whole surface-coated photoresist, figure is made with known photoetching process in the zone except that photoresist part 224a and 224b.Utilize resist as mask, a kind of element of selecting the group that constitutes from nitrogen, carbon, oxygen is selectively mixed the marginal portion in island semiconductor district, be specially nitrogen in this example.Utilize plasma doping to mix nitrogen in the marginal portion.Utilizing nitrogen as impurity gas, is 10 to 30W with radio frequency (rf) power, and for example 10W produces plasma discharge, carries out plasma doping.Utilize accelerating voltage 20 to 60KV, for example 20KV mixes silicon area to the plasma that produces.The dosage of nitrogen is 1 * 10 16To 5 * 10 16Cm -2, for example, 1 * 10 16Cm -2So form nitrating district 225a, 225b, 225c and 225d.Under these conditions, find that it is 1 * 10 that the concentration of nitrogen is contained in the nitrating district 20To 2 * 10 22Cm -2, for example, approximately be 1 * 10 21Cm -2, showing that this district compares with other semiconductor region, the nitrogen of quite big quantity has been mixed in this district.The structure of gained is shown in Figure 12 (A).
After removing mask 224a and 224b, remove bottom silica diaphragm 223a and 223b again, expose the surface of semiconductor region 222a and 222b, utilize sputtering deposit silicon oxide film 226 as gate insulation layer, thickness is 1000
Figure 941040925_IMG72
Then utilize the low pressure chemical vapor deposition deposit to contain the silicon fiml of 0.1 to 2% phosphorus, thickness is 6000
Figure 941040925_IMG73
To 8000
Figure 941040925_IMG74
, for example be 6000
Figure 941040925_IMG75
Preferably silicon oxide deposition film and silicon fiml continuously.The silicon fiml that mixes impurity of gained is made figure, form semiconductor bonding pad 227a and 227b, gate electrode and lead-in wire are provided.These bonding pads are also as gate electrode.The structure that obtains is shown in Figure 12 (B).
Utilize above-mentioned bonding pad 227a as mask, the phosphorus as impurity is injected silicon area by plasma doping.Can utilize hydrogen phosphide (PH 3) injecting phosphorus as impurity gas, the accelerating voltage of use is 60 to 90KV, for example, 80KV.The dosage that mixes phosphorus is 1 * 10 15To 8 * 10 15Cm -2, for example be 5 * 10 15Cm -2 Form impurity range 228a and 228b.In reducing atmosphere, implanted dopant was annealed 48 hours in 600 ℃.In this step operation of thermal annealing, owing to heat the lateral edge portions of island district 222a and 222b simultaneously, be reflected at this district formation by chemical formula Si by nitrogen and silicon 3N 4-xThe substrate of (0＜x＜4 herein) expression.If replace nitrogen in this district with carbon or oxo, then correspondingly form by chemical formula SixC 1-x(0＜x＜1) or SiO 2-xThe compound of (0＜x＜2) expression.Resulting structures is shown in Figure 12 (C).
Utilizing the plasma CVD deposition thickness is 3000
Figure 941040925_IMG76
Silicon oxide film as interlevel insulator.Opening contact hole passes the gained film, and the formation employing resembles the bonding pad 229a and the 229b of the multiple layer metal material membrane titanium nitride and the aluminium.Interconnecting one of among bonding pad 229a and bonding pad 227b and the impurity range 228b.The semiconductor circuit of having made is shown in Figure 12 (D).
Embodiment 9
The profile of the structure that the substep that Figure 21 is obtained by another embodiment of the present invention technology is continuous.With reference to Figure 21, form 2000 by sputtering at above the Corning#7059 substrate 601
Figure 941040925_IMG77
Thick silicon oxide film is as counterdie 602.Utilize plasma CVD deposition of amorphous silicon film thereon, thickness is 500 to 1500 , for example 1500
Figure 941040925_IMG79
Then at once by sputtering deposit 200
Figure 941040925_IMG80
Thick silicon oxide film is as diaphragm.Resulting structures, in reducing atmosphere, under 600 ℃, annealed 48 hours again, make the amorphous silicon film crystallization.Can utilize high light to carry out crystallization step resemble the laser beam.Utilize known photoetching process that the crystal silicon film that obtains is made figure, obtain island district 603a and 603b.Above the island silicon area diaphragm is arranged at each.On the island silicon area, photoresist mask 604a and the 604b that in corrosion step, uses in addition.Use isotropic etching process, for example, use the chamfered edge of the wet corrosion formation semiconductor region of fluoro nitric acid.Chamfered portion is 30 to 60 ° with respect to the angle of substrate.
Utilize resist as mask, oxygen is mixed silicon area by plasma doping.Utilize oxygen (O 2) gas or nitrogen oxide (N 2O) as impurity gas, using accelerating voltage is 20 to 60KV, and for example 20KV carries out plasma doping.Oxygen dosage is 1 * 10 16To 5 * 10 16Cm -2, for example 1 * 10 16Cm -2The oxygen doped region 605a, 604b, 604c and the 605d that form are shown in Figure 21 (A).
With sputter or plasma CVD silicon oxide deposition film 606, as gate insulating film, thickness is 1000
Figure 941040925_IMG81
Then, contain the aluminium film of 2% silicon by sputtering deposit, thickness is 6000 to 8000
Figure 941040925_IMG82
, for example be specially 6000 Preferably silicon oxide deposition film and aluminium film continuously.Then, the aluminium film is made figure, make bonding pad 607a and 607b.These bonding pads are also as gate electrode.Anodic oxidation is carried out on surface to the aluminium bonding pad, forms oxide layer 609a and 609b.Before carrying out anodic oxidation, the part that will form the contact zone in the later step is applied photosensitive polyimides (Photoneece) mask 608 is provided.Use the method, the part of mask is not covered by anodic oxidation.
In containing the tartaric ethylene glycol solution of 1-5%, carry out anodic oxidation.Obtain 2000
Figure 941040925_IMG84
Thick oxide layer.Utilize bonding pad 607a and oxide layer 609a as mask, phosphorus is injected in the silicon area as impurity with the method for plasma doping.Utilize hydrogen phosphide (PH 3) be 60-90KV, for example 80KV as impurity gas, accelerating voltage, inject phosphorus.Utilize dosage 10 * 10 14To 8 * 10 15Cm -2, for example, be specially 5 * 10 15Cm -2Inject phosphorus.Impurity range 610a that obtains and 610b are shown in Figure 21 (B).
Then, activate the impurity that injects with laser annealing.The laser that uses in this example is KrF excimer laser, and operation wavelength is 248nm, and pulse duration is 20nsec.Other adoptable laser comprises XeF excimer laser, and operation wavelength is 353nm, XeCl excimer laser, and operation wavelength is 308nm, ArF excimer laser, operation wavelength is 193nm.Laser beam uses energy density to be 200-350mJ/cm 2, 250mJ/cm for example 2Each position irradiation 2-10 time, for example 2 times.In irradiation laser period, substrate is heated to 200-450 ℃.But should be noted that optimum laser energy density changes when heated substrate.During irradiation laser, be retained in the lip-deep polyimides mask of aluminium and prevent that the aluminium surface of exposing from producing damage.Behind irradiation laser, polyimides is exposed in the oxygen plasma, can remove the polyimides mask at an easy rate.
The technology of present embodiment and embodiment 8 described technology differences are incoming laser beam is not added to notes oxygen zone below the gate electrode.Therefore, this zone keeps low crystallinity, but plays a very large resistance effect.Therefore, the technology of finding present embodiment reduces leakage current effectively.Resulting structures is shown in Figure 21 (C).
Because the impurity in this situation combination is oxygen, in the activation step of source afterwards and leakage, can form SiO by the reaction between oxygen and the island district Si semiconductor 2-xIn addition, except the technology of this embodiment explanation, other technology can also be proposed.Especially, this technology comprises: provide the island district with chamfered edge part, corresponding to the structure shown in Fig. 2 (A); Selectively carbon, nitrogen or oxygen, particularly carbon, introduce the chamfered edge part; After removing photoresist, utilize laser annealing the structure crystallization of gained.Use the method, can partly convert chamfered edge to represent carborundum by SIxCl-x.Since the carborundum that obtains with the method can be with than island semiconductor district can be with broad, can prevent at marginal portion generation insulation breakdown and leakage current.
With plasma CVD silicon oxide deposition film 611, thickness is 3000 , as interlevel insulator.Opening contact hole passes the gained film then, and the metal material multilayer film that employing resembles titanium nitride and the aluminium forms bonding pad 612a and 612b.Bonding pad 612a is linked to each other with the zone of one of bonding pad 607b and impurity range 610b.The semiconductor circuit of making comprises TFT613a and another TFT613b, shown in Figure 21 (D).
Readily understand by the above embodiments 9, between the impurity range of gate electrode and reservation, unless the source of TFT or an electrode of leakage are set at least, otherwise be easy to form electric capacity.Therefore, make an electric capacity, can obtain to have high reliability and resemble the product of the good device property the high withstand voltage and low-leakage current with the technology that is similar to present embodiment.TFT that obtains according to present embodiment and electric capacity can be assembled into the pixel circuit into the driven with active matrix liquid crystal display device.
Embodiment 10
Figure 14 represents to be obtained by another embodiment of the present invention technology the profile of substep continuous structure.In Figure 14, the structure on the left side represents that corresponding to the TFT along A-A ' line section, the structure on the right is represented corresponding to the TFT along B-B ' line section.With reference to Figure 14, on Corning#7059 glass substrate 240, form 2000 by sputter Thick bottom 241, this bottom comprise the individual layer or the multilayer of silica, silicon nitride or aluminium nitride.Then, utilize plasma CVD deposition of amorphous silicon film thereon, thickness is 500 to 1500
Figure 941040925_IMG87
, for example 1500
Figure 941040925_IMG88
The amorphous silicon film that obtains is made figure, obtain island silicon area 242a and 242b.
The whole surface-coated photoresist of resulting structures, the surface that applies photoresist, the zone except resist 243a and 243b utilizes known photoetching process to make figure.Utilize against corrosionly, mix nitrogen by plasma doping as mask, so that obtain nitrating district 244a, 244b, 244c and 244d are shown in Figure 14 (A).
Be attended by the photoresist of staying special area, utilize sputtering deposit 1000
Figure 941040925_IMG89
Thick silicon oxide film 245a.The structure of gained is shown in Figure 14 (B).
After peeling photoresist off, remove the silicon oxide film that forms thereon.With this kind method, there is not the part of photoresist thereon, can keep silicon oxide film.By resulting structures in reducing atmosphere, 600 ℃ annealing 48 hours down, make the resulting structures crystallization.The high light of utilization resemble the laser beam can carry out crystallization step.
Utilize sputtering deposit silicon oxide film 245b, thickness is 1000
Figure 941040925_IMG90
, as gate insulating film.Utilize the low pressure chemical vapor deposition deposit to contain the silicon fiml of 0.1-2% phosphorus, thickness is 6000-8000 ,, for example be specially 6000
Figure 941040925_IMG92
Best, silicon oxide deposition film and silicon fiml continuously.The silicon fiml of adding impurity of gained is made figure, so that form bonding pad 246a and 246b.Gate electrode is also played in these bonding pads.Pay special attention to the periphery of island silicon area (part of mixing nitrogen promptly), find that the thickness of dielectric film is doubled, this is because silicon oxide film 245a and 245b.Should understand, this structure is effective to preventing that gate insulating film from producing puncture.So the structure that obtains is shown in Figure 14 (C).
Utilize above-mentioned bonding pad 246a as mask,, phosphorus is injected into silicon area as impurity by plasma doping.Utilize hydrogen phosphide (PH 3) can inject phosphorus as impurity gas, by in 600 ℃ of temperature this structure being annealed 48 hours, activate the impurity that so injects in low pressure atmosphere.Form impurity range 247a and 247b with the method.
With plasma CVD silicon oxide deposition film 248, thickness is 3000
Figure 941040925_IMG93
, as interlevel insulator.Opening contact hole passes the gained film, and the multilayer film that employing resembles the metal material titanium nitride and the aluminium forms bonding pad 249a and 249b.Bonding pad 249a and one of bonding pad 246b and impurity range 247b interconnect.The semiconductor circuit of making is shown in Figure 14 (D).
Technology according to present embodiment provides semiconductor circuit, compares with conventional situation, and output is increased to twice or higher.Not observing the TFT characteristic degenerates.On the contrary, maximum actual voltage available is compared with custom circuit and is increased to 1.5 to 2 times.Thus, maximum operating speed increase to traditional circuit 2-4 doubly.
Embodiment 11
Figure 22 represents the profile by the substep continuous structure of the technology acquisition of another embodiment of the present invention.With reference to Figure 22, forming thickness on substrate 160 is 1000
Figure 941040925_IMG94
To 3000
Figure 941040925_IMG95
Silicon oxide film as counterdie.Utilize plasma CVD or LPCVD deposition of amorphous silicon film thereon, thickness is 100 to 5000
Figure 941040925_IMG96
, be preferably 300 to 1000
Figure 941040925_IMG97
Then, deposit immediately 100 to 500
Figure 941040925_IMG98
Thick silicon oxide film is as the diaphragm of amorphous silicon film.Then utilize photoresist to form mask 163a and 163b by known photoetching process.With 50Sccm(per minute standard cubic centimeter) CF 4And 45SccmO 2Mixed airflow, under 100m torr air pressure, carry out dry-etching with radio frequency (RF) power of 500W, to the amorphous silicon film etching.
Island silicon area 162a that obtains and 162b are shown in Figure 22 (A).Can see that the chamfer part becomes 20-60 ° angle with respect to substrate surface.Find when using CF at high proportion 4/ O 2CF 4And O 2Mist the time, above-mentioned chamfered edge can not be provided.
Utilize above-mentioned resist as mask, oxygen, carbon or nitrogen, for example, select nitrogen for use, mix silicon area in this situation by plasma doping.Utilize nitrogen (N 2) as impurity gas, use accelerating voltage to be 20-60KV, for example 20KV carries out nitrating.With 1 * 10 16To 5 * 10 16Cm -2Dosage, for example preferred 1 * 10 16Cm -2The dosage nitrating.Use the method, do not having silicon area marginal portion resist or that resist only is provided thinly to form nitrating district 164a, 164b, 164c, 164d.So the structure that obtains is shown in Figure 22 (A).
By the protective layer of removing photoresist mask 163a and 163b and being provided with below, expose after the island silicon fiml, carry out the crystallization step of amorphous silicon film.By the irradiation operation wavelength is that 248nm, pulse duration are the KrF excimer laser of 20nsec, carries out crystallization step.In addition, can also utilize operation wavelength to be 308nm and pulse duration XeCl excimer laser for 50nsec.
Utilize sputter or plasma CVD deposit 1000 to 1500
Figure 941040925_IMG99
Thick silicon oxide film 165 forms the aluminium film that contains 1% silicon or 0.1-0.3% scandium by weight thereon with electron beam vapour deposition or sputter.
With known rotation coating technique photoresist is added to the surface of resulting structures, the gained film is made figure with known photoetching process.Then, utilize phosphoric acid corrosion aluminium film.In this way, form gate electrode with bonding pad 166a and 166b.Gained gate electrode with bonding pad has photoresist mask mould 167a and 167b in the above.Can see that by Fig. 2 (B) side with gate electrode of bonding pad is positioned at the inboard of photoresist side.
, utilize photoresist mask 167a and 167b, inject, impurity is injected TFT active semiconductor layer 162a and 162b by ion thereafter.Form N type source 168a and leak 168b with the method.Shown in Figure 22 (C), gate electrode 166a is positioned at photoresist mask 167a distance and is the inboard of X, can see, not gate electrode be added to source and leakage above, and realized an off-set construction with the method.This distance X is variable, is decided by the etching time of aluminium bonding pad, yet, X preferably between 0.3-5 μ m.
Peeling off after photoresist mask 167a and the 167b, is that 248nm and pulse duration are the laser beam irradiation resulting structures of the KrF excimer laser of 20nsec with operation wavelength.Use the method, the activator impurity ion.Resulting structures is shown in Figure 22 (D).
At last, deposit 2000 on whole surface
Figure 941040925_IMG100
To the silicon oxide film of 1 μ m as interlayer dielectric 169.In addition, at the source region of TFT 168a and opening contact hole above the 168b of drain region, form aluminium bonding pad 170a and 170b, thickness is 2000
Figure 941040925_IMG101
To 1 μ m, for example 5000 For example, can be below the aluminium bonding pad formation titanium nitride layer, as barrier metal layer, so that further improve the reliability of device.
Embodiment 12
Narrated the technology of making single TFT device at previous embodiment 8-10.But, can provide thin film semiconductor's circuit by further integrated above-mentioned TFT element.In this situation, preferably the present invention is used for on-chip particular electrical circuit.Present embodiment relates to the technology that forms particular electrical circuit.The situation that comprises the active matrix circuit and the liquid crystal display device of the peripheral circuit that drives it at monolithic for example, preferably only is applied to active matrix circuit to the present invention.
In active matrix, must suppress the grid of TFT and the leakage current between the leakage as wide as possible, because must keep electric charge.Satisfy these requirements according to TFT of the present invention.
Especially, manufacturing process comprises, in the marginal portion of oxygen, nitrogen or carbon being introduced TFT island semiconductor district before, at first topped the peripheral circuit part with simple mask resemble the metal mask.In this way, can only mix element the zone of active matrix.An example of above-mentioned situation as shown in figure 23.Structure shown in Figure 23 (A) comprises a substrate 801, is provided with an active matrix circuit 73 and the peripheral circuit 71 and 72 that is used to drive active matrix circuit thereon, with the many bonding pads 75 and 76 that are used to be connected peripheral circuit and active matrix.Many pixels 74 that comprise a TFT are set in active matrix circuit 73.The integrated circuit of this method structure comprises the peripheral circuit 71 and 72 that is covered by mask 77.
If around active matrix, peripheral circuit is set, just be equipped with peripheral circuit on top, bottom, the left side, the right of active matrix, then provide mask 78 by the mode shown in Figure 23 (B).With reference to Figure 24, the technology of this structure integrated circuit is made in narration.Figure 24 provides along perpendicular to the profile on the plane of gate electrode (promptly corresponding to the plane along the section of B-B ' line among Figure 11).
The silica of deposit individual layer, silicon nitride or aluminium nitride on substrate, the perhaps multilayer film of forming by these films, thickness is 1000 to 4000
Figure 941040925_IMG103
, for example 2000
Figure 941040925_IMG104
, as counterdie 802.Form amorphous silicon film, thickness is 200-1500
Figure 941040925_IMG105
, for example 500
Figure 941040925_IMG106
, deposition thickness is 100 to 500 then
Figure 941040925_IMG107
, for example 200
Figure 941040925_IMG108
Silicon oxide film as diaphragm., amorphous silicon film 550 to 650 ℃ between annealed, make the amorphous silicon film crystallization thereafter.
After the method formation Etching mask 805 and 806 with similar embodiment 11, adopt dry etching method corrosion amorphous silicon film.
So, be similar to the situation of embodiment 4, obtain to have the island silicon area 803 and 804 of chamfered edge, shown in Figure 24 (A).
Utilizing above-mentioned resist as mask, is oxygen, carbon or nitrogen, for example present embodiment that nitrogen mixes in the silicon area by plasma doping.Utilize nitrogen (N 2) as impurity gas, use 20 to 60KV accelerating voltage, 20KV for example, nitrating.With 1 * 10 16To 5 * 10 16Cm -2, for example 1 * 10 16Cm -2The dosage nitrating.In the doping process, the peripheral circuit corresponding to 803 zones among the figure is covered with metal mask 807, only expose active matrix district 804.Use the method, only nitrogen is mixed the marginal portion 808 that does not have applying photoresist, or the only very thin marginal portion 808 that is coated with resist.Nitrogen is not mixed the silicon area 803 that covers metal mask 807.So the structure that obtains is shown in Figure 24 (A).
Behind the protective layer of removing Etching mask 805,806 and being provided with in its lower section, form silicon oxide film 809 with sputter or plasma CVD, thickness is 1000
Figure 941040925_IMG109
To 1500
Figure 941040925_IMG110
Then, deposited by electron beam evaporation deposit or sputter form the aluminium film that contains 1% silicon by weight or contain 0.1 to 0.3% scandium by weight thereon.Before formation silicon oxide film 809, with high light, particularly by KrF excimer laser or XeCl excimer laser emitted laser bundle irradiation silicon oxide film, so that make the ion doping silicon fiml carry out crystallization resemble the laser beam.
Its post-etching aluminium film obtains the aluminium bonding pad.Similar embodiment 9 described technologies form anodic oxide coating around the aluminium bonding pad that obtains, so that form the gate electrode with bonding pad 810,811 and 812, shown in Figure 14 (B).
With plasma doping being injected into active semiconductor layer 803 and 804 as the boron of p type impurity with as the phosphorus of N type impurity.Then, the foreign ion that is incorporated into active layer being activated, is that 248nm, pulse duration are that the laser beam of the KrF excimer of 20nsec carries out activator impurity by the irradiation operation wavelength.Form N type impurity range 813 and 814, p type impurity district 815 to 818 with the method.By this step, the ion implanted region 808 that forms is in the past converted to p type island region 819 and 820.Yet the gained district compares with the drain region with the source region, contains nitrogen and high resistance is arranged.This structure is shown in Figure 24 (C).
At last, utilize plasma CVD silicon oxide deposition film on whole surface, thickness is 2000
Figure 941040925_IMG111
To 1 μ m, as interlevel insulator 821.Deposit ITO(tin indium oxide) film, thickness is 500 to 1000
Figure 941040925_IMG112
, for example, 800
Figure 941040925_IMG113
, by corrosion it is made figure, pixel capacitors 822 is provided.
Open the source of TFT and the contact hole of leakage, utilize the multilayer film of aluminium and titanium nitride to form bonding pad 823 and 827.In this way, make the film semiconductor integrated circuit shown in Figure 24 (D), the peripheral circuit that it comprises an active matrix circuit and is used to drive it.
The invention provides and under the situation that improves output, to improve the TFT of reliability, and can make full use of their characteristic.In addition, obtain so huge effect, but do not have a large amount of change technology, do not increase cost of investment, perhaps, much do not study and development.With particular reference to the TFT that forms on insulating substrate, narration is according to TFT of the present invention.Certainly, be also included within according to TFT of the present invention and form TFT on the single crystal semiconductor substrate.
According to thin-film semiconductor device of the present invention, low especially leakage current is arranged at grid and between leaking, between grid and the source.Therefore, its anti-high gate voltage thereby be suitable as the transistor of control pixel in the active matrix for liquid crystal displays circuit.
Can further use the present invention, not only can be used for described those situations that simple structure is arranged of previous embodiment, also be used in its source and leak the TFT that uses silicide, for example, disclosed Japanese patent application, No. puts down (Hei) 5-256567.Needless to say, the present invention also is suitable for other circuit element, for example, thin film integrated circuit, it comprises an island semiconductor district that is provided with many gate electrodes, folded grid TFT, diode, resistance and capacitor.In addition, as described in embodiment 12, the present invention can be used for the specific thin-film component of thin film integrated circuit, so that make the circuit of being made up of each element that shows very good characteristic.
In addition, the present invention includes the marginal portion of active layer is become insulation, do not provide active layer, and make and specify the periphery in active layer zone to have insulation characterisitic by the method for making figure.Use the method, covering relevant problem with the bad step of gate insulating film and gate electrode can be solved, and the result has improved output and the reliability of TFT significantly.
Though with reference to its specific embodiments, detailed narration the present invention, apparent, those skilled in the art under the situation that does not depart from spirit of the present invention and scope, can carry out variations and modifications.

Claims (21)

1, the transistorized method of a kind of manufacturing comprises:
Form the island semiconductor district;
On described semiconductor region, form insulating coating;
Form the grid parts of the described semiconductor region of cross-over connection;
At least the mask that exposes described grid parts and described semiconductor region is provided;
Utilize described mask that impurity is mixed described semiconductor region;
Utilize described mask, selectively remove described insulating coating;
With the described semiconductor region of photoirradiation;
2, according to the process of claim 1 wherein that described grid parts comprise the gate electrode of being made by electric conducting material and cover the oxide of the described electric conducting material of described gate electrode.
3, according to the process of claim 1 wherein that described grid parts comprise aluminium.
4, according to the process of claim 1 wherein, utilize the solution that contains hydrofluoric acid to carry out wet corrosion, carry out the described step of removing.
5, a kind of transistor comprises:
An island semiconductor district, it comprises a source region, a drain region, a raceway groove and the zone that is essentially intrinsic between described source and described drain region;
A gate electrode, the described semiconductor region of its cross-over connection, adjacent with described raceway groove, and between described raceway groove and described gate electrode, have gate insulating film.
Wherein saidly be essentially the zone of intrinsic and the periphery of described semiconductor region is in contact with one another, and be arranged on described gate electrode and described source and leak in one of between.
6, the transistorized method of a kind of manufacturing comprises:
Form the semiconductor region of an island;
Form the gate electrode of the described semiconductor region of cross-over connection;
A mask is set in the marginal portion of described semiconductor region, and it comprises the part that is positioned at the described semiconductor region below the described gate electrode, and impurity is mixed described semiconductor region, forms source region and drain region therein.
7, according to the method for claim 6, also comprise:
After described doping step, utilize described mask, pass through the described gate insulating film of corrosion, expose the surface of described semiconductor region;
After described exposure step, with the described semiconductor region of photoirradiation.
8, a kind of transistor comprises:
An island semiconductor district, it comprises source, leakage and the raceway groove between described source and leakage;
A gate electrode, the described semiconductor region of its cross-over connection, adjacent with described raceway groove, between described raceway groove and described gate electrode, have gate insulating film,
Wherein said semiconductor region further comprises: the peripheral contacted zone with described semiconductor region, and be arranged on described gate electrode and described source and leak in one of between, and have the conduction type identical with described channel type.
9, the transistorized method of a kind of manufacturing comprises:
Form an island semiconductor district;
A kind of element that is selected from least in the group of forming by oxygen, carbon and nitrogen, selectively be incorporated into the periphery at least of described semiconductor region, gate electrode is connected across on this semiconductor region;
Formation is connected across the gate electrode on the described semiconductor region;
Utilize described gate electrode to make mask, impurity is incorporated into described semiconductor region, formation source and leakage in described semiconductor region by Alignment Method.
10, a kind of transistor comprises:
On the insulating surface of substrate, semiconductor film is set,
Wherein, described semiconductor film comprises described transistorized active area, with the zone of active area insulation, its be set at described active area around.
11, according to the transistor of claim 10,
Wherein, with the zone of active area insulation, be arranged on described active area around, form by silica or silicon nitride, and can see through visible light.
12, the transistorized method of a kind of manufacturing comprises:
On the insulating surface of substrate, form semiconductor film;
By the material that can make described semiconductor film become insulator is added to described periphery, make described semiconductor film periphery have insulation characterisitic at least.
13, according to the method for claim 12, wherein said material comprises at least a element that is selected from the group of being made up of oxygen, carbon and nitrogen.
14, a kind of semiconductor device comprises:
The semiconductor region of an island;
Be connected across the gate electrode of described semiconductor region,
Wherein, described semiconductor region comprises an outer peripheral areas, and it comprises at least a element that is selected from the group of being made up of oxygen, carbon and nitrogen, and its concentration is higher than the mean concentration in the described semiconductor region, in the periphery of described semiconductor region, has the described gate electrode that is connected across described outer peripheral areas.
15, according to the device of claim 14, wherein said island semiconductor district comprises a chamfered edge.
16, according to the device of claim 14, wherein said outer peripheral areas has the width of 0.05 to 5 μ m.
17, a kind of method of making semiconductor device comprises:
Form the island semiconductor district;
Selectively at least a element is incorporated into described at least semi-conductive periphery, gate electrode is connected across on the described semiconductor region, and above-mentioned element is selected from the group of being made up of oxygen, carbon, nitrogen;
Form the gate electrode of the described semiconductor region of cross-over connection;
By impurity being incorporated into described semiconductor region, form source region and drain region.
18, a kind of method of making semiconductor device comprises:
Form the semiconductor region of an island, it is made up of the material that is essentially amorphous semiconductor;
Selectively at least a element that is selected from the group of being made up of oxygen, carbon, nitrogen is mixed the periphery of described semiconductor region;
By photoirradiation is arrived described semiconductor region, make described semiconductor region crystallization;
Formation is connected across the gate electrode of described semiconductor region.
19, a kind of method of making semiconductor device comprises:
On the film of non-single crystalline semiconductor material, form mask material directly or indirectly;
Utilize photoetching that described mask material is made figure;
According to the described mask material of making figure,, described erosion is become island by dry corrosion or wet corrosion;
A kind of ion of acceleration is mapped on the described island that has the mask material of making figure on it, and above-mentioned ion comprises at least a element that is selected from the group of being made up of oxygen, carbon, nitrogen;
Formation is connected across the gate electrode on described island.
20, according to the method for claim 19, wherein said island has chamfered edge.
21, a kind of semiconductor integrated circuit, comprising:
Be positioned at an on-chip active matrix circuit;
Be arranged on a described on-chip circuit, be used to drive described active matrix circuit,
Wherein, the transistor of described active matrix circuit comprises a semiconductor film, this film comprises a marginal portion and is connected across the transistor gate of described marginal portion, this marginal portion has at least a element that is selected from the group of being made up of oxygen, carbon, nitrogen, and its concentration is higher than the concentration of the other parts of described semiconductor film.
CN94104092A 1993-03-05 1994-03-05 Semiconductor integrated circuit, semiconductor device, transistor and manufacture method thereof Pending CN1098818A (en)

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JP07110193A JP3226655B2 (en) 1993-03-05 1993-03-05 Method for manufacturing thin film transistor
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JP146997/93 1993-05-26
JP343943/93 1993-12-17
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7696562B2 (en) 2006-04-28 2010-04-13 Semiconductor Energy Laboratory Co., Ltd Semiconductor device
CN1917220B (en) * 2001-02-28 2012-08-15 株式会社半导体能源研究所 Method of manufacturing a semiconductor device
CN103996718A (en) * 2014-06-05 2014-08-20 湘潭大学 Silicon-based ferroelectric grid thin film transistor and preparation method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1917220B (en) * 2001-02-28 2012-08-15 株式会社半导体能源研究所 Method of manufacturing a semiconductor device
US7696562B2 (en) 2006-04-28 2010-04-13 Semiconductor Energy Laboratory Co., Ltd Semiconductor device
US7867838B2 (en) 2006-04-28 2011-01-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN101064321B (en) * 2006-04-28 2012-05-09 株式会社半导体能源研究所 Semiconductor device and method for manufacturing the same
CN103996718A (en) * 2014-06-05 2014-08-20 湘潭大学 Silicon-based ferroelectric grid thin film transistor and preparation method thereof

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