CN1099812C - Digital signalling processor device for program-controlled exchanger - Google Patents
Digital signalling processor device for program-controlled exchanger Download PDFInfo
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- CN1099812C CN1099812C CN99113483A CN99113483A CN1099812C CN 1099812 C CN1099812 C CN 1099812C CN 99113483 A CN99113483 A CN 99113483A CN 99113483 A CN99113483 A CN 99113483A CN 1099812 C CN1099812 C CN 1099812C
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Abstract
The present invention relates to a digital signaling processing device for a program control exchanger, which comprises at most two digital signal processing modules and a programmable logic control element, wherein the two digital signal processing modules are used for executing digital signal processing in a system; the programmable logic control element finishes signal conversion of the digital signal processing modules and the system of the program control exchanger and provides reset signals for the digital signal processing modules. Each digital signal processing modules comprises a memory, a clock crystal oscillator, a debugging interface and a central processing unit, wherein the memory comprises EPROM and SRAM; the clock crystal oscillator provides a required work clock; the debugging interface provides a software debugging interface; the central processing unit is respectively connected with the clock crystal oscillator and the debugging interface in a control connection mode, and the central processing unit is also connected with the memory by a bus.
Description
(1) technical field
The present invention relates to the digital signal processor spare that a kind of stored-program control exchange is used.
(2) background technology
Digital signalling is meant the digital signal of user key-press generation and the multifrequency sender signal equifrequent combined digital signal between the exchange.The S12J type stored-program control exchange that generally uses in the market, its digital signalling is handled and is adopted first generation digital signal processor spare DSPA, the digital signalling that DSPA supported has dual-tone multifrequency sign indicating number DTMF, cno.1 signaling R2, international No. five signaling N5 and conduction test sound etc., it with program controlled switching system between link to each other by pulse code modulation PCM, as shown in Figure 1, described digital signal processor spare DSPA is mainly by digital signalling processing DSP unit (adopting the AD2100 chip), central processing unit (adopting 80186 chips), system interface unit (employing asic chip), and memory is formed.It can be finished:
1) enters system interface unit asic chip the DSPA by the digital signal in the S12J type program controlled switching system from PCM, transferring to DSP unit (adopting the AD2100 chip) through the ASIC buffering handles, result sends to central processing unit 80186 chips by the DSP unit, return S12J type program controlled switching system through the system interface unit asic chip again, promptly finish the acceptance of digital signalling;
2) according to prior agreement digital signal is sent to S12J type program controlled switching system by after the system interface unit asic chip buffering by the DSP unit;
3) the DSP unit will superpose from the voice signal that asic chip is imported, and finishes tripartite and five side's convention businesses.
Because DSPA uses for many years on S12J type stored-program control exchange, one side is along with the development of hardware technology, the needs that device upgrades, it is higher that hardware cost seems, on the other hand, what the digital signal processing unit of DSPA adopted is the AD2100 chip, and this chip also will stop production, therefore, can't keep normal production demand.
(3) summary of the invention
The digital signal processor spare that the object of the present invention is to provide a kind of a kind of stored-program control exchange that can meet the need of market and with low cost to use.
The object of the present invention is achieved like this, the digital signal processor spare that a kind of stored-program control exchange is used, it is connected in series in a kind of program controlled switching system by PCM, and a standard asynchronous serial ports that provides links to each other with debugging acid, its characteristics are that it comprises: two digital signal processing modules at the most, be used for the Digital Signal Processing in the executive system, and the asynchronous serial port of a standard is provided; The FPGA (Field Programmable Gate Array) control element, it carries out synchronous serial interface with described one or two digital signal processing module respectively and is connected, finish the conversion of signals of digital signal processing module and program controlled switching system on the one hand, provide reset signal for digital signal processing module on the other hand.Wherein, described digital signal processing module comprises: holder, it comprises the read-only memory EPROM of erasable programmable, the static holder of read-write arbitrarily SRAM, wherein EPROM is used to deposit the program and the initialized data of needs of curing, download to SRAM after powering on, SRAM provides program and data space for CPU; Clock crystal oscillator provides required work clock; Debugging interface provides the software debugging interface; CPU, it carries out control connection with clock crystal oscillator, debugging interface respectively, is connected by bus with holder.
The digital signal processor spare that described stored-program control exchange is used, its CPU comprises: the acceptance of digital signalling and transmitting element are used to finish the transmission and the acceptance of digital signal; Conference bridge unit is finished tripartite and five side's meeting bridges; The hardware check of entire device is finished in the hardware testing unit; Interface control unit, it links to each other with transmitting element, conference bridge unit and hardware testing unit with the acceptance of described digital signalling respectively, be used to accept the order of program controlled switching system, finish the acceptance of digital signalling and the function that transmitting element, conference bridge unit, hardware testing unit will be finished, execution result is sent program controlled switching system back to the most at last.
Owing to adopted above-mentioned technical solution, the digital signal processor spare that a kind of stored-program control exchange of the present invention is used is with low cost, has satisfied the demand in market.
The present invention is further illustrated below in conjunction with embodiments of the invention and accompanying drawing.
(4) description of drawings
Fig. 1 is the hardware capability block diagram of the digital signal processor spare of existing stored-program control exchange;
Fig. 2 is a hardware capability block diagram of the present invention;
Fig. 3 is the software function block diagram of the CPU among the present invention;
Fig. 4 is the workflow block diagram of the CPU among the present invention.
(5) embodiment
By shown in Figure 2, the digital signal processor spare DSPB that a kind of stored-program control exchange of the present invention is used, it is connected in series in a kind of stored-program control exchange (adopting S12J type stored-program control exchange herein) system by PCM, and a standard RS232 asynchronous serial port that provides links to each other with debugging acid, and its characteristics are that it comprises:
The FPGA (Field Programmable Gate Array) control element, it carries out synchronous serial interface with following one or two Digital Signal Processing (DSP) module respectively and is connected, and finishes the conversion of signals of DSP module and switch on the one hand, provides reset signal for the DSP module on the other hand.It is to communicate by the PCM of two per second 4 megabits (being 4Mb/s) and S12J type program controlled switching system, employing be the EPM7032 chip that U.S. ALTERA company produces;
Digital signal processing module carries out synchronous serial interface with the FPGA (Field Programmable Gate Array) control element and is connected, and the RS232 asynchronous serial port of a standard is provided, and is used for the Digital Signal Processing in the executive system.
Wherein, described digital signal processing module comprises:
CPU, it carries out control connection with clock crystal oscillator, debugging interface respectively, is connected the digital processing chip TMS320C50 that it adopts TIX to produce by bus with holder;
Holder, it comprises the read-only memory EPROM of erasable programmable, the static holder of read-write arbitrarily SRAM, wherein EPROM is used to deposit the program and the initialized data of needs of curing, download to SRAM after powering on, SRAM provides program and data space for CPU, and holder EPROM adopts the 32K byte.Holder SRAM adopts the 128K word length;
Clock crystal oscillator, it is connected with CPU, for it provides required work clock, adopts 57MHz usually;
Debugging interface, it is connected with CPU, for the invention provides the software debugging interface.
By shown in Figure 3, described CPU adopts software to realize its function, and it mainly comprises:
The acceptance of digital signalling and transmitting element are used to finish the transmission and the acceptance of digital signal.Wherein, the signaling method that can send and accept has N5, the R2 forward direction, behind the R2 to, conduction test sound and DTMF the frequency signal of totally five kinds of signaling methods.Because the digital processing chip TMS320C50 that the hardware using TIX of CPU produces, the concurrency that this chip is handled and the high speed of multiplying, two basic filters have been designed altogether, carrying out the filtering of dtmf signal and other signal respectively calculates, these two filters adopt the grand realization of assembler language, handled data all are placed among the interior DARAM of this chip simultaneously, and the disposal ability of this chip is given full play to;
Conference bridge unit is finished tripartite and five side's meeting bridges;
The hardware check of DSPB plate is finished in the hardware testing unit;
Interface control unit, it links to each other with transmitting element, conference bridge unit and hardware testing unit with the acceptance of described digital signalling respectively, is used to accept the order of S12J type machine system, and calls described functional unit, finish relevant business, execution result is sent S12J type machine system back to the most at last.
By shown in Figure 4, the workflow of the software in this CPU is as follows:
The digital signal processor spare DSPB of stored-program control exchange of the present invention, after its energising, hardware check.After self check is passed through, require to carry out hardware testing according to the operator.Treat all EOTs, require to change over to normal operating conditions according to the operator.In normal operation, DSPB provides three kinds of function services simultaneously to the user: meeting bridge, the transmission of digital signalling, the reception of digital signalling.In normal operation, the systemic circulation service never stops.
Claims (2)
1. digital signal processor spare that stored-program control exchange is used, it is connected in series in a kind of program controlled switching system by PCM, and a standard asynchronous serial ports that provides links to each other with debugging acid, it is characterized in that it comprises:
Two digital signal processing modules are used for the Digital Signal Processing in the executive system at the most, and the asynchronous serial port of a standard is provided;
The FPGA (Field Programmable Gate Array) control element, it carries out synchronous serial interface with described one or two digital signal processing module respectively and is connected, finish the conversion of signals of digital signal processing module and program controlled switching system on the one hand, provide reset signal for digital signal processing module on the other hand
Wherein, described digital signal processing module comprises:
Holder, it comprises the read-only memory EPROM of erasable programmable, the static holder of read-write arbitrarily SRAM, wherein EPROM is used to deposit the program and the initialized data of needs of curing, downloads to SRAM after powering on, and SRAM provides program and data space for CPU;
Clock crystal oscillator provides required work clock;
Debugging interface provides the software debugging interface;
CPU, it carries out control connection with clock crystal oscillator, debugging interface respectively, is connected by bus with holder.
2. the digital signal processor spare that a kind of stored-program control exchange as claimed in claim 1 is used is characterized in that: described CPU mainly comprises:
The acceptance of digital signalling and transmitting element are used to finish the transmission and the acceptance of digital signal;
Conference bridge unit is finished tripartite and five side's meeting bridges;
The hardware check of entire device is finished in the hardware testing unit;
Interface control unit, it links to each other with transmitting element, conference bridge unit and hardware testing unit with the acceptance of described digital signalling respectively, be used to accept the order of program controlled switching system, finish the acceptance of digital signalling and the function that transmitting element, conference bridge unit, hardware testing unit will be finished, execution result is sent program controlled switching system back to the most at last.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN99113483A CN1099812C (en) | 1999-02-15 | 1999-02-15 | Digital signalling processor device for program-controlled exchanger |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN99113483A CN1099812C (en) | 1999-02-15 | 1999-02-15 | Digital signalling processor device for program-controlled exchanger |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1264256A CN1264256A (en) | 2000-08-23 |
| CN1099812C true CN1099812C (en) | 2003-01-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99113483A Expired - Lifetime CN1099812C (en) | 1999-02-15 | 1999-02-15 | Digital signalling processor device for program-controlled exchanger |
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| CN (1) | CN1099812C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104331017B (en) * | 2014-11-12 | 2018-04-20 | 深圳市英威腾电气股份有限公司 | A kind of frequency converter Programmable logical controller function realizing method, device and frequency converter |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4922519A (en) * | 1986-05-07 | 1990-05-01 | American Telephone And Telegraph Company | Automated operator assistance calls with voice processing |
| CN1154030A (en) * | 1996-10-22 | 1997-07-09 | 北京市电话局 | Centralized operation and maintenance system of program-controlled exchanger |
-
1999
- 1999-02-15 CN CN99113483A patent/CN1099812C/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4922519A (en) * | 1986-05-07 | 1990-05-01 | American Telephone And Telegraph Company | Automated operator assistance calls with voice processing |
| CN1154030A (en) * | 1996-10-22 | 1997-07-09 | 北京市电话局 | Centralized operation and maintenance system of program-controlled exchanger |
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| Publication number | Publication date |
|---|---|
| CN1264256A (en) | 2000-08-23 |
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Owner name: BELL CO.,LTD., SHANGHAI Free format text: FORMER NAME: BELL TELEPHONE EQUIPMENT CO., LTD., SHANGHAI Owner name: SHANGHAI ALCATEL-LUCENT CO., LTD. Free format text: FORMER NAME: BEIER AERKATE CO., LTD., SHANGHAI Owner name: BEIER AERKATE CO., LTD., SHANGHAI Free format text: FORMER NAME: BELL CO.,LTD., SHANGHAI |
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Address after: 201206 No. 188-189 Baer Road, Jinqiao, Shanghai, Pudong Patentee after: ALCATEL-LUCENT SHANGHAI BELL Co.,Ltd. Address before: 201206 No. 188-189 Baer Road, Jinqiao, Shanghai, Pudong Patentee before: Shanghai Bell Alcatel Co.,Ltd. Address after: 201206 No. 188-189 Baer Road, Jinqiao, Shanghai, Pudong Patentee after: Shanghai Bell Alcatel Co.,Ltd. Address before: 201206 No. 188-189 Baer Road, Jinqiao, Shanghai, Pudong Patentee before: Shanghai Bell Co.,Ltd. Address after: 201206 No. 188-189 Baer Road, Jinqiao, Shanghai, Pudong Patentee after: Shanghai Bell Co.,Ltd. Address before: 201206 No. 188-189 Baer Road, Jinqiao, Shanghai, Pudong Patentee before: SHANGHAI BELL TELEPHONE EQUIPM |
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Granted publication date: 20030122 |