CN1192430C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1192430C
CN1192430C CNB001049275A CN00104927A CN1192430C CN 1192430 C CN1192430 C CN 1192430C CN B001049275 A CNB001049275 A CN B001049275A CN 00104927 A CN00104927 A CN 00104927A CN 1192430 C CN1192430 C CN 1192430C
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layer
barrier layer
conductive barrier
interconnection
window
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Expired - Fee Related
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CN1269607A (zh
Inventor
亚力山大·L·巴尔
苏勒士·梵卡特散
戴维·B·克勒格
勒波卡·G·考尔
奥鲁布恩米·阿德突突
斯杜尔特·E·格力尔
布瑞安·G·安舍尼
拉姆那施·凡卡特拉曼
格勒帼·布雷科尔曼
道格拉斯·M·勒博
斯蒂芬·R·克朗
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN1269607A publication Critical patent/CN1269607A/zh
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Abstract

一种覆盖半导体器件衬底(10)的互连。在一个实施例中，导电势垒层覆盖部分互连，钝化层(92)覆盖导电势垒层，且钝化层(92)具有暴露部分导电势垒层(82)的窗口。在一个变通实施例中，钝化层(22)覆盖互连，钝化层(22)具有暴露互连的窗口(24)，且导电势垒层(32)覆盖窗口(24)中的互连。

Description

半导体器件及其制造方法
技术领域
本发明一般涉及到半导体器件的制作工艺，更确切地说是涉及到包括互连势垒层的半导体器件的制作工艺。
背景技术
随着半导体器件的尺寸和封装件越来越小，在半导体器件键合焊点上制作导电凸块变得越来越普遍。此凸块被用来代替金属丝，以便将键合焊点电连接到其相应的封装引线。一种特定类型的凸块包括受控熔塌芯片连接(C4)凸块。这些凸块通常需要在键合焊点与凸块之间制作焊点限制金属层。焊点限制金属层通常包括铬和铬的合金。但这些含铬的薄膜可以具有诸如裂纹和不规则晶粒边界之类的缺陷，这就限制了铬层恰当地将键合焊点和凸块材料分隔开来的能力。
凸块通常包括锡(Sn)和铅(Pb)之类的元素。当势垒无法保持键合焊点与凸块分隔时，键合焊点材料能够与凸块中的铅或锡发生反应，并能够形成这些材料的金属间合金。若键合焊点包括含铜的材料，则能够导致易碎的金属间合金。易碎的金属间合金随后可能破裂，从而导致凸块失效。此外，由于键合焊点与凸块之间的键合过程和粘合性变坏而可能形成空洞。在极端的情况下，这可以产生高阻，能够对半导体器件的性能造成负面影响，甚至导致半导体器件失效。
发明内容
根据本发明的一方面，提供一种半导体器件，其特征是：在半导体器件衬底上形成的第一互连；在部分第一互连上形成的绝缘势垒层；在另一部分第一互连和部分绝缘势垒层上形成的键合焊点互连；覆盖部分键合焊点互连的导电势垒层，此导电势垒层延伸到该部分键合焊点互连的边沿区以外；导电势垒层上形成的抗氧化层；以及覆盖抗氧化层的钝化层，此钝化层和抗氧化层具有暴露部分导电势垒层的窗口。
根据本发明的另一方面，提供一种制作半导体器件的方法，其特征是：在半导体器件衬底上制作第一互连；在部分第一互连上制作绝缘势垒层；在另一部分第一互连和部分绝缘势垒层上制作键合焊点互连；制作覆盖部分键合焊点互连的导电势垒层，此导电势垒层延伸到该部分键合焊点互连的边沿区以外；制作覆盖导电势垒层的抗氧化层；制作覆盖抗氧化层的钝化层，以及在钝化层和抗氧化层中制作窗口，其中窗口暴露部分导电势垒层。
附图说明
在附图中，用举例而不是限制的方法，描述了本发明，其中相同的参考号表示相同的元件，其中：
图1-7示出了根据第一组实施例制作具有铜互连和凸块的半导体器件的剖面图。
图8-12示出了根据第二组实施例制作具有铜互连和凸块的半导体器件的剖面图。
熟练的技术人员能够理解，各个图中的各个元件是为了简明而示出的，没有必要按比例绘出。例如，为了有助于增进对本发明实施例的了解，图中的某些元件的尺寸可能相对于其它的元件被夸大了。
具体实施方式
根据本发明的实施例，公开了一种半导体器件及其制作方法。在一个实施例中，导电势垒层覆盖互连，钝化层覆盖导电势垒层，且钝化层具有暴露部分导电势垒层的窗口。在一个变通实施例中，钝化层覆盖互连，钝化层具有暴露互连的窗口，且导电势垒层覆盖窗口中的互连。
图1示出了部分半导体器件的剖面图。此半导体器件包括半导体器件衬底100、场隔离区102、以及制作在半导体器件衬底100中的掺杂区104。栅介质层106覆盖部分半导体器件衬底100，而栅电极108覆盖栅介质层106。
在栅电极108和半导体器件衬底100上，制作第一层间介质层(ILD)110。对此第一层间介质层110进行图形化，以形成被粘合/势垒层112和铜填充材料114填充的双重镶嵌窗口。此粘合/势垒层112通常是难熔金属、难熔金属氮化物、或难熔金属或它们的氮化物的组合。铜填充材料114通常是铜或铜的合金，其中铜的含量至少为90％原子比。为了改善互连的粘合性、电迁移或其它性质，铜可以与镁、硫、碳之类形成合金。在淀积粘合/势垒层112和铜填充材料114之后，对衬底进行抛光以清除窗口外面的粘合/势垒层112和铜填充材料114部分。
在制作第一互连层之后，在铜填充的互连和第一ILD层110上制作绝缘势垒层122。此绝缘势垒层122包括氮化硅、氮氧化硅之类。用绝缘材料制作绝缘势垒层122，免除了采用导电势垒层时为了使各个互连彼此电隔离而需要的额外的图形化和腐蚀工序。在绝缘势垒层122上制作第二ILD层124。在第二ILD124中制作包含导电粘合/势垒层126和铜填充材料128的双重镶嵌互连。此双重镶嵌互连用相似于制作第一ILD层110中的双重镶嵌互连结构所用的工艺和材料来制作。
然后，如图2所示，在第二ILD层124和双重镶嵌互连上制作钝化层22。此钝化层可以包括一个或多个由氮化硅、氮氧化硅、二氧化硅之类组成的膜。最靠近铜填充材料128的钝化层22部分，通常包括氮化硅或氮原子相对于氧原子浓度较高的氮氧化硅膜。对钝化层22进行图形化，以便形成穿过钝化层延伸到铜填充材料128的键合焊点窗口24。
如图3所示，在钝化层22和铜填充材料128上淀积导电势垒层32。可以用包括化学汽相淀积、物理汽相淀积、蒸发淀积、电镀、无电镀之类的工艺来制作导电势垒层32。此层的厚度一般在大约50-300nm的范围内。此导电势垒层32通常包括难熔金属、难熔金属的氮化物、或它们的组合。在一个实施例中，此导电势垒层32包括钛(Ti)和氮化钛(TiN)的组合。钛/氮化钛叠层改善了对下方铜填充材料128和钝化层22的粘合性。此外，氮化钛形成势垒，防止了铜填充材料与随后淀积的导电凸块发生反应。作为变通，此导电势垒层32可以包括诸如钽(Ta)、氮化钽(TaN)、钨(W)、氮钨化钛(TiWN)、钨化钛(TiW)、氮化钨(WN)、氮化钼(MoN)、氮化锢(CoN)、或它们的组合之类的其它材料。在其它实施例中，可以使用抗氧的材料。这些材料可以包括铂(Pt)、钯(Pd)、镍(Ni)、导电金属氧化物或它们的相应金属等等。此导电金属氧化物或它们的相应金属还可以包括铱(Ir)和氧化铱(IrO2)；钌(Ru)和氧化钌(RuO2)；铼(Re)和氧化铼(ReO2和ReO3)；或锇(Os)和氧化锇(OsO2)。
然后在导电势垒层32上制作光刻胶层34。此光刻胶层34暴露部分覆盖钝化层22的导电势垒层32。此光刻胶层制作成覆盖键合焊点窗口34。此外，如图3所示，也可以对其进行图形化，以便稍许延伸于位于钝化层22上的导电势垒层32的表面部分。
然后用常规腐蚀工艺对此导电势垒层32进行腐蚀，以便清除覆盖钝化层22的导电势垒层32的暴露部分。腐蚀之后，用等离子体灰化工艺或用使用诸如N-甲基-2-吡咯烷酮、丙酮、甲基异丁基酮(MIBK)之类的有机化学品的湿法化学工艺，来清除图形化的光刻胶层34。
作为变通，若电镀或无电镀之类的镀敷工艺被用来制作导电势垒层，则可以不需要上述的图形化工序。而是可以在制作窗口24之后，直接在铜填充材料128的暴露部分上镀敷导电势垒层。如图4所示，若有需要，镀敷可以进行到镀敷的材料覆盖部分钝化层以形成导电势垒层32的程度。
然后，如图5所示，在半导体器件上制作管芯涂敷层52，并对其进行图形化以形成覆盖键合焊点窗口24的管芯涂敷窗口54。在此特定实施例中，导电势垒层32的外围部分具有暴露在管芯涂敷窗口54中的边沿。此管芯涂敷层52可以制作成可光成象的聚酰亚胺膜或被常规光刻胶和腐蚀工艺图形化的聚酰亚胺膜。
如图6所示，在制作焊点限制金属层62之前，通过射频(RF)溅射清洗对导电势垒层32的暴露部分进行加工。借助于清除可能包含诸如氧、碳、氟和氯之类的杂质的导电势垒层32的最上部分，RF溅射清洗改善了势垒层与焊点限制金属层62之间的接触电阻。在一个实施例中，RF溅射清洗工艺作为在淀积焊点限制金属层(凸块下方)之前的原位加工的一部分被执行。在一个实施例中，执行RF溅射清洗的工艺参数如下：RF功率在大约1200-1500W范围内，直流(DC)偏置电压在大约-300到-600V范围内，压力在大约0.1-0.5帕范围内，而时间在大约150-250秒范围内。此RF溅射清洗工艺从势垒层32的表面清除大约20-40nm的势垒材料。
然后，如图6所示，在管芯涂敷窗口54内制作焊点限制金属层62。焊点限制金属层通常包括能够包括粘合膜、中间耦合/焊接膜和抗氧化势垒膜的各个膜的功能组合。在一个实施例中，焊点限制金属层62包括下列4个不同的膜组成的复合物：铬膜622、铬铜合金膜624、铜膜626和金膜628。铬膜622和铬铜合金膜624的厚度都在大约50-500nm范围内，铜膜626的厚度在大约700-1300nm范围内，而金膜628的厚度在80-140nm范围内。作为变通，焊点限制金属可以包括诸如由钛、铜和金组成的复合物或由钛、镍、铜和金组成的复合物这里的各个膜的组合。通常用使用屏蔽板的蒸发方法来制作焊点限制金属层62。但也可以采用溅射之类的其它方法来制作焊点限制金属。
根据一个实施例，如图7所示，在制作焊点限制金属层之后，在焊点限制金属层62上淀积诸如铅锡焊料材料72之类的凸块材料。可以用屏蔽板方法来蒸发铅锡焊料材料72，或者用诸如镀敷或焊料喷射之类的其它常规方法来制作。然后，如图7所示，执行回流工艺步骤，使铅锡焊料材料72的各个角圆滑，从而形成凸块。
在工艺的这一时刻，已经制造了基本上完成的半导体器件。随后可以将此器件固定到倒装片或网格焊球阵列封装件之类的封装结构。虽然未示出，也可以按需要制作其它的互连层。同样，对栅电极108和掺杂区104也可以制作其它互连。若要制作额外的互连，则可以用制作和淀积绝缘体势垒层122、第二ILD层124、粘合/势垒层126和铜填充材料128的相似的工艺来制作。
图8-12示出了本发明的一个变通实施例。参照图8，在第二ILD层124和铜填充材料128上制作导电势垒层82。用图3首次示出的制作导电势垒层32中所述的任何一种方法或材料来制作导电势垒层82。此导电势垒层82的厚度通常在大约50-300nm范围内。在此特定的实施例中，然后在导电势垒层82上制作可选的抗氧化层84。此抗氧化层可以包括防止下方层氧化的或比下方层更容易被氧化的任何材料。可以使用的材料的例子包括氮化硅、多晶硅、非晶硅、或导电金属氧化物或其相应的导电金属。抗氧化层84的厚度在大约10-50nm范围内。然后在导电势垒层82和抗氧化层84上制作光刻胶层86。对光刻胶层86进行图形化，以覆盖位于铜填充材料128和粘合/势垒层126上的部分导电势垒层82和抗氧化层84。
然后用常规腐蚀工艺清除导电势垒层82和抗氧化层84的未被图形化的部分。然后，如图9所示，清除光刻胶，并在包含导电势垒层82和抗氧化层84的叠层以及部分介质层124上制作钝化层92。此钝化层92相似于图2首先介绍的钝化层22。在此特定的实施例中，对钝化层92进行图形化以形成键合焊点窗口94。如图9所示，不是键合焊点窗口中的所有的钝化层都被清除。因此，在图形化工艺中仅仅局部地形成键合焊点窗口。在完成图形化之后，残留的部分96仍然保留在抗氧化层84上。
然后，如图10所示，制作管芯涂敷层1001，并对其进行图形化以形成管芯涂敷窗口1003。此管芯涂敷层1001相似于图5首次介绍的管芯涂层52。此管芯涂敷窗口1003暴露包括残留部分96的部分钝化层92。在形成管芯涂敷窗口1003之后，执行腐蚀以清除残留部分96和下方的抗氧化层84。如图11所示，这就形成了管芯涂敷窗口1103。在这一腐蚀过程中，正如被清除的钝化层部分1102所示，被管芯涂敷层1001暴露的部分钝化层92也被腐蚀。在一个特定的实施例中，钝化层92包括诸如氮化硅或氮氧化硅之类的硅和氮，而抗氧化层84包括氮化硅。因此，可以用相同的或相似的腐蚀化学来清除钝化层92和抗氧化层84的残留部分96。
继续工艺，以便形成图12所示的基本上完成的器件。与前述相似地制作焊点限制金属层1220，它包括铬膜1222、铬铜合金膜1224、铜膜1226和金膜1228以及铅锡焊料1230。如果需要，与前述相似，可以在制作焊点限制金属层1220之前，用RF溅射清洗工艺来制备势垒层的表面。在此特定的实施例中，如图12所示，回流步骤被执行以便使铅锡焊料的形状圆滑，使其外貌成圆顶状。
在图9-12所述的各个实施例中，绝缘势垒层122被用于最上层互连之外的所有互连层。最上层互连是其上制作键合焊点的互连层。因此，它是使用导电势垒层82的唯一的互连层。
本发明可以有许多其它的实施例。参照图3，导电势垒层32也可以包括相似于图8-12中第二组实施例所述的抗氧化层84的覆盖抗氧化层。同样，由于钝化层92的残留部分96使得能够使用含氧的等离子体而不损伤导电势垒层82，故第二组实施例不一定需要使用抗氧化层84。当导电势垒层82或32包括能够与含氧的等离子体或用来清除或显影光刻胶或聚酰亚胺的其它化学品发生不利的反应的氮化钽、氮化钛之类时，这是很重要的。这些化学品的例子可以包括四甲基氢氧化氨、N-甲基-2-吡咯烷酮、丙酮、MIBK等。
除了如图9-12所示在键合焊点上制作导电势垒层之外，也可以用导电势垒材料在半导体器件的导电区之间制作聚焦能量可改变的即激光可改变的连接。这些连接的电导率可以用激光加以修正，以便对器件电路进行编程或调整。
用导电势垒层制作激光可改变的连接，比现有技术更为优越。比之通常用来形成激光可改变的连接的互连层，这一导电势垒层通常更薄，热导率更低、且反射率更低。比之互连层，此导电势垒层还是自钝化的。因此，激光改变的可靠性由于降低了激光改变后的短路可能性而通常得到改善。此外，激光可改变的连接被制作在更靠近半导体器件的最上表面处。这使激光器能够使用较少的功率来影响激光可改变的连接的电导率，这相应地降低了引起短路、损伤相邻连接和损伤周围钝化层的可能性。而且，可以用同一个层同时制作此导电势垒层和激光可改变的连接。因此，工艺整体不需要额外的加工步骤。
虽然对于焊点限制金属层62列出了具体的材料，但也可以使用其它的材料和此整个方法的其它变种。例如，导电势垒层可以组合成焊点限制金属层的一部分。此时，可以在制作其它各个焊点限制金属层薄膜之前，将其蒸发或溅射到晶片上。在另一个实施例中，焊点限制金属层和焊料材料可以用物理汽相淀积或喷射印刷方法一起制作，从而用喷嘴将各个熔化的焊料液滴淀积就位。
此处所述的各个实施例可以整合成现有工艺而无须使用稀有的材料、开发新的工艺、或采购新的加工设备。导电势垒层32和82足以防止来自互连的铜与来自凸块的铅锡焊料相互发生反应。因此，保持了凸块与互连之间界面处的完整性。这就改善了凸块的机械完整性，并有助于降低凸块与互连之间的电阻。
在上述说明书中，已经参照具体的实施例描述了本发明。然而，本技术领域的熟练人员理解，能够做出各种各样的修正和改变而不超越下列权利要求所述的本发明的范围。因此，本说明书和附图被认为是示例性的而不是限制性的，且所有这些修正都包括在本发明的范围内。对于具体的实施例，已经描述了各种好处、其它的优点以及问题的解决办法。然而，这些好处、优点、问题的解决办法、以及可能引起任何好处、优点或解决办法出现或变得更为明显的任何因素，都不会构成任何一个或所有权利要求的严格的、必要的或主要的特点或因素。

Claims (7)

1.一种半导体器件，其特征是：
在半导体器件衬底(100)上形成的第一互连(114)；
在部分第一互连(114)上形成的绝缘势垒层(122)；
在另一部分第一互连(114)和部分绝缘势垒层(122)上形成的键合焊点互连(128)；
覆盖部分键合焊点互连(128)的导电势垒层(82)，此导电势垒层(82)延伸到该部分键合焊点互连(128)的边沿区以外；
在导电势垒层(82)上形成的抗氧化层(84)；以及
覆盖抗氧化层(84)的钝化层(92)，此钝化层(92)和抗氧化层(84)具有暴露部分导电势垒层(82)的窗口。
2.权利要求1的半导体器件，其中部分所述导电势垒层(82)在至少二个导电区之间形成激光可改变的连接。
3.权利要求1的半导体器件，其中键合焊点互连(128)主要包括铜，而导电势垒层(82)包括含难熔金属的材料。
4.一种制作半导体器件的方法，其特征是：
在半导体器件衬底(100)上制作第一互连(114)；
在部分第一互连(114)上制作绝缘势垒层(122)；
在另一部分第一互连(114)和部分绝缘势垒层(122)上制作键合焊点互连(128)；
制作覆盖部分键合焊点互连(128)的导电势垒层(82)，此导电势垒层(82)延伸到该部分键合焊点互连(128)的边沿区以外；
制作覆盖导电势垒层(82)的抗氧化层(84)；
制作覆盖抗氧化层(84)的钝化层(92)，以及
在钝化层(92)和抗氧化层(84)中制作窗口(1103)，其中窗口暴露部分导电势垒层(82)。
5.权利要求4的方法，其中在钝化层(92)和抗氧化层(84)中制作窗口还包含：
在钝化层(92)中制作局部窗口(94)，其中局部窗口的深度小于形成局部窗口处的钝化层区域中钝化层的厚度；
在钝化层(92)上制作管芯涂敷层(1001)；
在管芯涂敷层中制作窗口(1003)，其中在管芯涂敷层中制作窗口暴露了钝化层(92)中的局部窗口(94)；以及
腐蚀钝化层(92)中的局部窗口，从而在钝化层(92)和抗氧化层(84)中形成窗口(1103)并在形成管芯涂敷层(1001)中的窗口(1003)之后暴露该部分的下方的导电势垒层。
6.权利要求4的方法，其进一步特征是：在导电势垒层(82)上制作导电凸块(1230)。
7.权利要求4的方法，其中键合焊点互连(128)主要包括铜，而导电势垒层(82)包括含难熔金属的材料。
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