CN1299477C

CN1299477C - Method for implementing multiplex line speed ATM interface in multi-layer network exchange

Info

Publication number: CN1299477C
Application number: CNB011316632A
Authority: CN
Inventors: 李锦飞; 张磊; 徐振
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2001-12-28
Filing date: 2001-12-28
Publication date: 2007-02-07
Anticipated expiration: 2021-12-28
Also published as: CN1428978A

Abstract

The present invention relates to a method for realizing a multiplex linear velocity interface in a multilayer network exchanger. The method comprises the following steps: (1) restoring data and a clock from an SONET/SDH flow, extracting and packaging synchronous loads, and framing ATM loads; (2) connecting a cell and a work queue by a channel descriptor, and retransmitting ATM SAR and the cell/a package by the ATM loads in a pipeline mode; (3) framing an Ethernet package, and exchanging and routing an IP package according to an MAC address table or a routing table. The method of the present invention can realize the effect of a multichannel linear velocity ATM interface on the multilayer network exchanger, greatly improve the performance of the ATM interface, and simultaneously, reduce cost and complexity.

Description

In layer network exchange, realize the method for multichannel line speed ATM interface

Technical field

The present invention relates to asynchronous transfer mode (hereinafter to be referred as the ATM) interface of layer network exchange, relate in particular to the method that in layer network exchange, realizes the multichannel line speed ATM interface.

Background technology

The network switch is tie point and the control point of internet from the Access Layer to the core layer, is the important component part of whole internet, is responsible for the packet forward of IP (Internet protocol) bag.The extensive use of the network switch just is with good expansibility the internet.And a large amount of at present ATM nets that exist require the network switch that atm interface must be arranged again, to realize the interconnected of ATM net and Ethernet.

As shown in Figure 1, in existing network switch atm interface card technique, ATM physical layer device 101 is connected to ATM SAR 102 by UTOPIA interface 105, can finish the partition refitting of ATM cell efficiently, and UTOPIA interface 105 wherein is Universal Test ﹠ Operationss PHY Interface for ATM; Finishing cell/bag by universal cpu 104 by software afterwards transmits.CPU 104 is connected with switching processor 103 with ATM SAR102 by pci bus 106, the cell that receives from atm port enters CPU through pci bus, by through pci bus bag being sent into switching processor again after the CPU processing, packet needs twice through pci bus like this, CPU also will come a plurality of real-time tasks such as performer read-write, webmaster by Microprocessor Interface 107 simultaneously, and the performance of obvious this implementation method depends on the performance of pci bus and CPU to a great extent.Adopt pci bus and the high-performance CPU of 66M at present, can realize the linear speed interface of 1 road 155M ATM; If realize multichannel 155M ATM linear speed interface, will duplicate the identical circuit of many covers, use a plurality of independently pci buss and high-performance CPU.Obviously existing method will increase considerably number of devices when realizing multichannel linear speed 155M atm interface, increase complexity, power consumption and the cost of ply-yarn drill.

Summary of the invention

Technical problem solved by the invention is, slow at ATM cell forwarding speed in the layer network exchange technology in the prior art, defectives such as technical sophistication, cost height when realizing the multichannel line speed ATM interface, provide a kind of complexity and cost all lower method, in layer network exchange, realize the multichannel line speed ATM interface.

Basic thought of the present invention is to use one or more pieces network processing units in the atm interface card, utilize the parallel hardware handles engine of network processing unit and the processor of the network optimization, finish the cell/bag of ATM SAR and full duplex with pipeline system and transmit, on layer network exchange, realize the multichannel line speed ATM interface.

Technical scheme of the present invention mainly may further comprise the steps:

(1), flows restore data and clock from SONET (Synchronous Optical Network)/SDH (synchronous digital hierarchy), the encapsulation of extraction synchronized loading, and framing ATM payload;

(2), connect cell and work queue, ATM payload is finished ATM SAR and cell/bag forwarding with pipeline system with the passage descriptor;

(3) framing Ethernet bag carries out exchange and the route that IP wraps according to mac address table or routing table.

Comprise following 3 little steps in (1) step wherein:

(1-1), receive SONET/SDH stream, restore data and clock by serial line interface by physical layer device;

(1-2), extract the synchronized loading encapsulation of carrying ATM cell;

(1-3), utilize cell structure framing ATM payload, send by the Utopia Level2 interface of physical layer device.

Comprise following 8 little steps in (2) step wherein:

(2-1), receive cell by Utopia Level 2 interfaces, set up the inlet flow waterline by network processing unit;

(2-2), extract the cell head, generate the passage descriptor and connect cell by pointer;

(2-3), incoming event is put into the incoming event work queue, startup incoming event processing threads;

(2-4), the incoming event processing threads sets up packet header according to the passage descriptor, changes cell over to the bag formation by ATM SARDMA (direct memory access (DMA)), and revises the tail pointer that the passage descriptor connects table;

(2-5) when the passage descriptor arrived passage descriptor connection table header, processor was set up the output stream waterline;

(2-6), outgoing event is put into the outgoing event work queue, activation outgoing event processing threads;

(2-7), the outgoing event processing threads outputs to SATURN Level 2 interfaces (a kind of POS-PHY interface of standard is by forum's definition that the associating of tens producers is arranged) by bag DMA with bag, and more the new tunnel descriptor connects meter pointer;

(2-8), TSS (The Traffic Scheduling System, business plan module) hardware engine is by the parameter in the prepass descriptor, in the transmission time of arranging next cell, handle with the linear speed that guarantees multichannel, multithreading.

Comprise following 5 little steps in (3) step wherein:

(3-1), receive bag by SATURN Level 2 interfaces, discern its entrained protocol type by switching processor;

Add (3-2) ,/remove that some one of frame heads compositions meet Ethernet (Ethernet) bag V.2;

(3-3), bag is sent to 2 layers of Switching Module, simultaneously with the MAC DA in MAC (medium accesses layer) DA (Destination Address, destination address) of bag and the routing table relatively, judges whether the MAC DA of bag is identical with MAC DA in the routing table;

If (3-4) identical, the formation of then bag being delivered to 3 layers of routing module waits route, and necessary processing is carried out in routing module extraction/parsing packet header, delivers to corresponding ports and equipment according to routing table;

If (3-5) inequality, then bag is delivered to corresponding ports and equipment according to mac address table.

Adopt the method for the invention, but integrated multipath atm interface, simultaneously owing to adopted network processing unit, utilize the parallel hardware handles engine of network processing unit and the processor of the network optimization, realize the pipeline processes of cell/bag, can on layer network exchange, realize the effect of multichannel line speed ATM interface, improve its performance significantly.The present invention compared with prior art when realizing the low speed atm interface, as the 155M atm interface, has significantly reduced cost and complexity; When realizing the high-speed atm interface, during as the 622M atm interface, solved the problem that prior art can't realize.

The invention will be further described below in conjunction with drawings and Examples.

Description of drawings

Fig. 1 is the theory diagram of ATM ply-yarn drill in the existing network switch technology;

Fig. 2 is the theory diagram of ATM ply-yarn drill in the embodiment of the invention one;

Fig. 3 is the theory diagram of ATM ply-yarn drill in the embodiment of the invention two;

Fig. 4 is the flow chart of the inventive method.

Embodiment

In order to implement method of the present invention, need do some changes to the theory diagram of ATM ply-yarn drill in the prior art shown in Fig. 1, mainly be on data path, to use network processing unit to realize ATM SAR and cell/bag forwarding, Utopia Level 2 interfaces and SATURN Level 2 interfaces with network processing unit replace pci bus, have avoided data to need twice through the formed bottleneck of pci bus; Processor with the hardware engine of network processing unit and the network optimization replaces high-performance CPU, has avoided CPU to transmit the formed bottleneck of cell/wrap in the pure software mode.The multichannel hardware pipeline of network processing unit, but a plurality of cells of parallel processing/bag; The RISC of the network optimization that it is embedded (Reduced Instruction Set Computer) processor, but a plurality of threads of executed in parallel simultaneously by intelligent algorithm, are presetted the processing time of next cell/bag, the distribution processor time of implementation, guarantee that the linear speed of multichannel, multithreading is handled.If use the multi-disc network processing unit, can on ply-yarn drill, realize more line speed ATM interface simultaneously, as 16 road 155M line speed ATM interfaces, 4 road 622M line speed ATM interfaces, and only need a slice CPU that all devices are managed.

In the embodiment of the invention one theory diagram of ATM ply-yarn drill as shown in Figure 2, it can realize 4 road 155M line speed ATM interfaces.Line scan pickup coil side is monolithic 4 road 155M ATM physical layer devices 201, and it can carry out data and clock synthesizes/recovers, and SONET/SDH handles.It connects the network processing unit 202 with 622M full duplex disposal ability by UTOPIALevel 2 interfaces 205 of standard, UTOPIALevel 2 interfaces provide the two-way 16bit bit wide of 50M and are the data traffic of 800Mbps to the maximum, can satisfy the requirement of 4 road 155M ATM.Network processing unit is realized ATM SAR, carries out the surface speed forwarding of cell/bag, and connects switching processor 203 by SATURN Level 2 interfaces 206, realizes the exchange and the route of IP bag; SATURN Level 2 interfaces also provide the two-way 16bit bit wide of 50M and are the data traffic of 800Mbps to the maximum, can satisfy the requirement of 4 road 155M ATM.

On the atm interface card, use a slice CPU 204 simultaneously, connect the Microprocessor Interface 207 of above each device, realize functions such as cell configuration, webmaster.Because CPU does not need to carry out real-time forwarding task, burden is little, low performance CPU in can selecting.The implementation method of this processor Network Based among Fig. 2 can realize 4 road 155M line speed ATM interfaces.

In the embodiment of the invention two theory diagram of ATM ply-yarn drill as shown in Figure 3, it can realize 2 road 622M line speed ATM interfaces.Line scan pickup coil side adopts 2 single channel 622M ATM physical layer devices 301,302, carries out data and clock and synthesizes/recover, and SONET/SDH handles.It connects 2 network processing units 303,304 with 622M full duplex disposal ability respectively by UTOPIALevel 2 interfaces 308,309 of standard, UTOPIA Level 2 interfaces provide 50M, two-way 16bit bit wide, are the data traffic of 800Mbps to the maximum, can satisfy the requirement of 1 road 622M ATM; Network processing unit is realized ATMSAR, carries out the surface speed forwarding of cell/bag, and connects 2 switching processors 305,306 respectively by SATURN Level 2 interfaces 310,311, realizes the exchange and the route of IP bag; SATURN Level2 interface also provides 50M, two-way 16bit bit wide, is the data traffic of 800Mbps to the maximum, can satisfy the requirement of 1 road 622M ATM.Connect by special-purpose switch fabric interface 313 between the switching processor.

Use a slice CPU307 simultaneously on the atm interface card, connect the Microprocessor Interface 312 of above each device, realize functions such as cell configuration, webmaster, because CPU does not need to carry out real-time forwarding task, burden is little, low performance CPU in can selecting.The implementation method of this processor Network Based can realize 2 road 622M line speed ATM interfaces.

The handling process of method of the present invention is as shown in Figure 4:

Step 401, ATM physical layer device receive SONET/SDH stream, recovered clock and data by serial line interface;

The synchronized loading encapsulation of ATM cell is carried in step 402, extraction;

Step 403, utilize cell structure framing ATM payload, send by the Utopia Level2 interface of physical layer device;

Step 404, network processing unit receive cell by Utopia Level 2 interfaces, set up the inlet flow waterline;

Step 405, extraction cell head generate the passage descriptor and connect cell by pointer;

Step 406, incoming event is put into the incoming event work queue, start the incoming event processing threads;

Step 407, incoming event processing threads are set up packet header according to the passage descriptor, change cell over to the bag formation by ATM SARDMA (direct memory access (DMA)), and revise the tail pointer that the passage descriptor connects table;

Step 408, when the passage descriptor arrives the passage descriptor and connects table header, processor is set up the output stream waterline;

Step 409, outgoing event is put into the outgoing event work queue, activate the outgoing event processing threads;

Step 410, outgoing event processing threads output to SATURN Level 2 interfaces by bag DMA with bag, and more the new tunnel descriptor connects meter pointer;

Step 411, TSS hardware engine in the transmission time of arranging next cell, are handled with the linear speed that guarantees multichannel, multithreading by the parameter in the prepass descriptor;

Step 412, switching processor receive bag by SATURN Level 2 interfaces, discern its entrained protocol type;

Step 413, add/remove that some frame heads form one and meet Ethernet bag V.2;

Step 414, bag are sent to 2 layers of Switching Module, and MAC DA and the MAC DA in the routing table with bag compares simultaneously, and whether the MAC DA of judgement bag is identical with the MAC DA in the routing table;

If step 415 is identical, the formation of then bag being delivered to 3 layers of routing module waits route, and necessary processing is carried out in routing module extraction/parsing packet header, delivers to corresponding ports and equipment according to routing table;

If step 416 is inequality, then bag is delivered to corresponding ports and equipment according to mac address table.

From the foregoing description as can be seen, but the present invention's integrated multipath atm interface, owing to adopted network processing unit, utilize the parallel hardware handles engine of network processing unit and the processor of the network optimization simultaneously, on layer network exchange, realized the multichannel line speed ATM interface.Method of the present invention is implemented simple, and cost is low, can improve the performance of atm interface significantly.

Claims

1, a kind of method that realizes the multichannel line speed ATM interface in layer network exchange is characterized in that, may further comprise the steps:

(1), from SONET/SDH stream restore data and clock, extract the synchronized loading encapsulation, and the framing ATM payload, by the Utopia Level 2 interfaces output of ATM physical layer device;

(2), connect cell and work queue, ATM payload is finished ATM SAR and cell/bag forwarding with pipeline system, and detailed process is with the passage descriptor:

Receive the cell of being exported by described ATM physical layer by network processing unit by Utopia Level 2 interfaces, set up the inlet flow waterline;

Extract the cell head, generate the passage descriptor and connect cell by pointer;

Incoming event is put into the incoming event work queue, start the incoming event processing threads;

The incoming event processing threads is set up packet header according to the passage descriptor, changes cell over to the bag formation by ATM SAR DMA, and revises the tail pointer that the passage descriptor connects table;

When the passage descriptor arrived passage descriptor connection table header, processor was set up the output stream waterline;

Outgoing event is put into the outgoing event work queue, activate the outgoing event processing threads;

The outgoing event processing threads outputs to SATURN Level 2 interfaces by bag DMA with bag, and more the new tunnel descriptor connects meter pointer;

The TSS hardware engine in the transmission time of arranging next cell, is handled with the linear speed that guarantees multichannel, multithreading by the parameter in the prepass descriptor;

(3), framing Ethernet bag, carry out the exchange and the route of IP bag according to mac address table or routing table.

2, the method that realizes the multichannel line speed ATM interface in layer network exchange according to claim 1 is characterized in that, in described (3) step:

Receive bag by switching processor by SATURN Level 2 interfaces, discern its entrained protocol type;

Add/remove that some one of frame heads compositions meet Ethernet bag V.2;

Bag is sent to 2 layers of Switching Module, and MAC DA and the MAC DA in the routing table with bag compares simultaneously, and whether the MAC DA of judgement bag is identical with the MAC DA in the routing table;

If identical, the formation of then bag being delivered to 3 layers of routing module waits route, and necessary processing is carried out in routing module extraction/parsing packet header, delivers to corresponding ports and equipment according to routing table; If it is inequality then bag is delivered to corresponding ports and equipment according to mac address table.