CN1310311C

CN1310311C - Design of 3D ROM

Info

Publication number: CN1310311C
Application number: CNB021133336A
Authority: CN
Inventors: 张国飙
Original assignee: Individual
Current assignee: Individual
Priority date: 2002-02-05
Filing date: 2002-02-05
Publication date: 2007-04-11
Anticipated expiration: 2022-02-05
Also published as: CN1437248A

Abstract

The present invention puts forward various manufacturing schemes for enhancing the manufacturability of 3D-MPROM, and puts forward a concept of 3D-EPROM synchronous programming. The present invention also increases the capacity of 3D-ROM by folding an electric wiring layer. The methods of embedded interface connection, address selection line fold, etc. are used for favorably realizing the interface between a substrate circuit positioned below the 3D-ROM and an outside circuit. 2F opening mask (2FOM) is widely applied to an integrated circuit.

Description

Improved three-dimensional masking film program read-only memory

Technical field

The present invention relates to integrated circuit, or rather, the design of 3 D ROM (3D-ROM).

Background technology

3 D ROM (3D-ROM) is a low cost, jumbo solid-state memory, its storage element-3D-ROM unit-be distributed in the three dimensions.As seen the basic structure of 3 D ROM authorize the inventor's United States Patent (USP) 5,835,396, U.S. Patent application 60/332,893, Chinese patent application 98119572.5 and 01129103.6.As shown in Figure 1, this 3D-ROM contains two

accumulation layers

100 and 200, has a plurality of address addressing line 20a... and a plurality of 3D-ROM 1aa.... of unit Semiconductor substrate 000 to contain a plurality of transistors on each accumulation layer.Interconnecting channels hole 20av, 30av ... for the peripheral circuit on storage element 1aa... and the substrate provides electrical connection.In the special case of Figure 1A, an interlayer medium is arranged between the memory layer, that is to say that each memory layer all has word line and the bit line of himself.In the another kind of structure of 3D-ROM, share word (or position) line between two accumulation layers.

3D-ROM can be divided into two classes: masking film program 3D-ROM (3D-MPROM) and electricity programming 3D-ROM (3D-EPROM).The digital information of 3D-MPROM is by the mask definition and at factory program; The digital information of 3D-EPROM can electricly be programmed and can be defined by the user.Shown in Figure 1B-Fig. 1 D, 3D-ROM unit 1 by two

electrodes

20 and 30 and the 3D-ROM film that is clipped between them form.Figure 1B and Fig. 1 C represent a logical one and logical zero 3D-MPROM unit respectively.Whether it represents Digital Logic information by the existence of information opening (info-opening) 24.In Figure 1B, the existence of information opening 24 is in contact with one another upper/

lower electrode

20,30 and can conducts electricity in one direction.Here, 3D-MPROM film 22 contains accurate conductive membrane.Accurate conductive membrane has following characteristic: on it added voltage less than read voltage or with read that voltage direction is opposite to be, its resistance is bigger.A kind of common accurate conductive membrane is the diode film, as P+/N-/N+ diode, P+/P-/N+ diode, Schottky diode etc.In Fig. 1 C, owing to do not have the information opening in the block media film 23, upper/

lower electrode

20,30 does not contact mutually and can not conduct electricity.Fig. 1 D represents a 3D-EPROM unit.Different with 3D-MPROM unit is to be a 3D-EPROM film between the

electrode

20,30 of 3D-EPROM unit.The 3D-EPROM film contains accurate conductive membrane 22 and anti-fuse film 22af.3D-EPROM unit represents Digital Logic information by the integrality of anti-fuse film 22af.In above-mentioned 3D-ROM unit,

electrode

20,30 contains layer of conductive material at least, and for example: metal (as aluminium, tungsten, copper etc.), metal alloy (as TiW etc.), metallic compound are (as TiSi _x, WSi _x, CoSi _x, NiSi _xDeng), the semi-conducting material (as silicon, germanium etc.) that mixes.

The present invention has proposed multiple fabrication scheme for the manufacturability that improves 3D-MPROM; And the 3D-EPROM notion of programming synchronously proposed; The present invention also folds the capacity that increases 3D-ROM by wiring layer; And use methods such as embedded interface connects, address selection line is folding to be beneficial to realize at substrate circuitry below the 3D-ROM and the interface between the ambient systems.2F opening mask (2F opening mask abbreviates 2FOM as) is widely used in integrated circuit.

Summary of the invention

Main purpose of the present invention is to improve the manufacturability of 3D-MPROM.

Another purpose of the present invention is to shorten the programming time of 3D-EPROM.

Another purpose of the present invention is the capacity that increases 3D-ROM.

Another purpose of the present invention is conveniently to be positioned at the substrate circuitry of 3D-ROM below and the interface of ambient systems.

According to these and other purpose, the invention provides the design of a 3D-ROM.

The invention provides a 3D-MPROM, it has better manufacturability.There are three kinds of fabrication schemes to reach this purpose: 1, to use self-alignment structure.In self-alignment structure, do not need an independent lithography step to aim at conductive membrane and carry out the figure conversion.Accurate conductive membrane is carrying out forming simultaneously when figure is changed to word line and bit line; 2, use the nature knot.In the storage element that contains the nature knot, there is not an independent accurate conductive membrane.Diode etc. with accurate conductive membrane function intersects the contact position at word line and bit line and forms naturally; 3, (2F info-opening mask abbreviates 2F-IOM as to use 2F information opening mask; Herein, F is the minimum dimension of this photoetching process).Concerning some 3D-MPROM units, the minimum dimension of their information opening figure can preferably double live width greater than the live width of word line or bit line.Correspondingly, the minimum dimension of information opening mask (info-opening mask) can be the minimum dimension of this technology of twice, so be referred to as 2F-IOM.Its another advantage is that adjacent information opening may be incorporated in together, can simplify the design of mask like this.

Concerning the programming of 3D-EPROM, the present invention proposes the notion of programming synchronously, can shorten the chip programming time like this.

The present invention adopts the folding way of a kind of wiring layer that the peripheral circuit of 3D-ROM is arranged in the storage array below, to improve array efficiency.The invention allows for methods such as embedded interface connection and address selection line fold.It provides and extraneous interface for the substrate circuitry that is positioned at 3D-ROM storage array below.

2F-IOM not only can use in masking film program read-only memory, also has other extensive uses.It can use in masking film program gate array (MPGA), field programming gate array (FPGA) based on anti-fuse (antifuse), even can use in general integrated circuit the interlayer contact as interconnection line.。

Description of drawings

Figure 1A is the perspective view of a 3D-ROM; Figure 1B is the sectional view of a logical one 3D-MPROM unit; Fig. 1 C is the sectional view of a logical zero 3D-MPROM unit; Fig. 1 D is the sectional view of a 3D-EPROM unit.

Fig. 2 is the sectional view of an interlayer intersection, autoregistration, platform-type 3D-MPROM (inter-digitatedself-aligned mesa-type 3D-MPROM abbreviates ISM 3D-MPROM as).

Fig. 3 A-Fig. 3 D is a kind of process chart of ISM 3D-MPROM.

Fig. 4 is the sectional view of an interlayer separation, autoregistration, platform-type 3D-MPROM (separateself-aligned mesa-type 3D-MPROM abbreviates SSM 3D-MPROM as).

Fig. 5 is an interlayer intersection, autoregistration, the sectional view of knot 3D-MPROM (inter-digitatedself-aligned natural-junction 3D-MPROM abbreviates ISN 3D-MPROM as) naturally.

Fig. 6 A-Fig. 6 D represents the structure chart of several ISN 3D-MPROM unit.

Fig. 7 A-Fig. 7 D is a kind of process chart of ISN 3D-MPROM.

Fig. 8 is an interlayer separation, autoregistration, the sectional view of knot 3D-MPROM (separateself-aligned natural-junction 3D-MPROM abbreviates SSN 3D-MPROM as) naturally.

Fig. 9 A-Fig. 9 D represents the structure chart of several SSN 3D-MPROM unit.

Figure 10 A represents an information opening figure; Figure 10 B represents an information opening mask; Figure 10 C represents another information opening figure; Figure 10 D represents another information opening mask.

Figure 11 A-Figure 11 D is a kind of process chart of the seamless 3D-MPROM of a use 2F-IOM.

Figure 12 represents that one has the 3D-EPROM of synchronous programming.

Figure 13 A-Figure 13 D represents the structure chart of two kinds of 3D-EPROM storage elements.

Figure 14 A-Figure 14 B has described a 3D-ROM with private wiring layer; Figure 14 C represents that one is folded to the peripheral circuit of storage array below; Figure 14 D-Figure 14 E has described a 3D-ROM with shared wiring layer; Figure 14 F is another peripheral circuit that is folded to the storage array below.

Figure 15 is the sectional view of a 3D-ROM.

Figure 16 A represents a 3D-ROM storage array and is arranged in its interconnecting channels hole all around; Figure 16 B represents along A ' A " interconnecting channels hole " wall " that constitute; Figure 16 C-Figure 16 D describes plane graph and the sectional view that embedded interface connects; Figure 16 E-Figure 16 F describes and folds plane graph and the sectional view that forms the interface channel by address selection line.

Figure 17 A-Figure 17 B represents that one uses 2F opening mask (2F opening mask abbreviates 2FOM as) to realize the masking film program gate array (MPGA) of the interlayer contact of interconnection line.

Figure 18 A-Figure 18 E is a kind of process chart of this MPGA.

Figure 19 represents that one uses 2FOM and based on the field programming gate array (FPGA) of anti-fuse (antifuse).

Embodiment

3D-MPROM

Fig. 2 is an interlayer intersection, autoregistration, platform-type 3D-MPROM (inter-digitatedself-aligned mesa-type 3D-MPROM abbreviates ISM 3D-MPROM as) sectional view.Term used herein " platform-type " is illustrated in that accurate conductive membrane has a platform shape on the address selection line.The accumulation layer of sort memory is intersected mutually, that is to say, two adjacent accumulation layers are shared an address selection line layer (word line layer or bit line layer).In this embodiment, two

word line layer

20a, 20a ' and two

bit line layer

30a, 30a ' are arranged.They form three accumulation layer ML 100, ML200, ML 300.Word line 20a and 3D-MPROM film 22, bit line 30a-30c form accumulation layer ML 100, word line 20a and 3D-MPROM film 22 ', bit line 30a '-30c ' composition accumulation layer ML 200.If the 3D-MPROM film uses the P+/N-/N+ diode, then the hierarchy of 3D-MPROM film 22 is N+, N-, P+ (arranging by the sequencing that forms); And 3D-MPROM film 22 ' hierarchy be P+, N-, N+.After this, the storage element label adopts following convention: storage element 20a/30c represents the storage element between word line 20a and bit line 30c.For logical zero storage element 20a/30c, a block media film 23 is arranged between word line and the bit line, it isolates word line and bit line.For logical one storage element 20a/30b, there is not the block media film between word line and the bit line, electric current can flow to bit line from word line, and is detected by peripheral circuit.In the 3D-ROM with interlayer cross characteristic, the address selection line in a plurality of accumulation layers intercouples, so their read procedure is comparatively special.For example, when reading accumulation layer ML 200, add on word line 20a and read voltage, detecting voltage changes on bit line 30a '-30c '; Wish that simultaneously the address selection line 20a ', the 30a-30c that do not have electric current can flow in other accumulation layer get on.A kind of execution mode is, adds on address selection line 20a ', the 30a-30c in other accumulation layer and reads voltage, and the 3D-

ROM film

22,22 like this " all is in reverse-bias state, thereby can stops electric current to flow through.In the special case of Fig. 2, word line and bit line contain layer of conductive material at least, as the semi-conducting material of metal, metal alloy, metallic compound, doping.

Fig. 3 A-Fig. 3 D is a kind of process chart of ISM 3D-MPROM.Form bit line film and 3D-MPROM film 22 at first, continuously.Then they are carried out first etching to form bit line bar 30a-30c, the space between these bit line bar 30a-30c is filled by medium in the layer 26.After this, by the planarization technology step such as CMP should layer in dielectric planarization, and 3D-MPROM film 22 exposed.Fig. 3 A represents to finish the sectional view after this step.

Except the special case among Fig. 3 A, bit line bar also can be taked another structure.After forming bit line film and 3D-MPROM film 22, form a buffer film 20ab more continuously.This buffer film contains electric conducting material.All these films are formed bit line bar by etching together then.Its cross section is in the middle expression of Fig. 3 A '.This structure has the structure of the seamless 3D-ROM unit described in U.S. Patent application 60/322,893 and the Chinese patent application 01129103.6.

Form block media film 23 and photoresist 23pr on the medium in bit line bar after complanation and the layer then.By information opening mask (info-opening mask abbreviates IOM as) photoresist 23pr is exposed.If wish to form a logical zero storage element at bit line 30a place, then do not remove the photoresist at this place; If wish to form a logical one storage element, then the resist exposure at this place to be removed, so that form information opening 24 at bit line 30b place.Fig. 3 B is the sectional view of finishing behind this processing step.

After this, block media 23 is carried out etching.This etching technics preferably has etching selection ratio preferably to a medium 26 in block media 23 and the layer, i.e. this etching technics etching block media film quickly, and slower to the etching speed of medium in the layer 26.Medium 26 can be used as the etching stopping film of this etching technics in the layer.For example, block media 23 can use silicon nitride or SiN _x/ SiO ₂Sandwich construction (SiN _xAt SiO ₂Below), and medium 26 uses silica in the layer.Prior art can obtain etching selection ratio preferably at an easy rate between them.One of benefit of this technological design is that the size of information opening 24 can be greater than the live width of bit line 30b, so IOM can use more ripe mask technology.Simultaneously, this lithography step requires lower to information opening and the alignment precision that is positioned at rhumb line under it.This will have concrete description in Figure 10 A, Figure 10 B.After this figure switch process is finished, form continuously again word line film 20a and another 3D-MPROM film 22 '.This is represented by Fig. 3 C.

Next step then forms the word line bar by second etching.The sectional view of y-z after this step is represented by Fig. 3 D.Can find out that from this technological process 3D-MPROM film 22 forms when first and second etchings are carried out.It and word line and bit line have self aligned relation.X-z sectional view from Fig. 2 and the y-z sectional view among Fig. 3 D as can be seen, 3D-MPROM film 22 has a platform shape.It and be a rectangle on the x-y plane, (22w1 22w2) equals word line live width (20aw) and bit line live width (30bw) respectively to two length of sides of this rectangle separately.

Fig. 4 is an interlayer separation, autoregistration, platform-type 3D-MPROM (separateself-aligned mesa-type 3D-MPROM abbreviates SSM MPROM as) sectional view.So-called " interlayer separation " is meant that the accumulation layer among this 3D-MPROM is to isolate mutually, and they are the shared address selection wire not.In this embodiment, word line layer 20a and bit line layer 30a form accumulation layer ML 100; Word line layer 20a ' and bit line layer 30a ' formation accumulation layer ML 200.Separate by inter-level dielectric 27 between accumulation layer ML 100 and the accumulation layer ML 200.

Fig. 5 is an interlayer intersection, autoregistration, the sectional view of knot 3D-MPROM (inter-digitatedself-aligned natural-junction 3D-MPROM abbreviates ISN 3D-MPROM as) naturally.The structure of its similar ISM 3D-MPROM in Fig. 2.Their difference is that ISN 3D-MPROM does not have an independent 3D-MPROM film 22.Diode with 3D-ROM film function etc. is formed on the intersection contact position of word line and bit line naturally.This will be specified in Fig. 6 A-Fig. 6 D.

Fig. 6 A-Fig. 6 D represents the structure chart of several ISN 3D-MPROM unit.Two storage elements are arranged in each figure, and one of them is stacked on another.Two storage elements are shared an electrode.Storage element 30a '/20a represents logical one, and storage element 30a/20a represents logical zero.

Fig. 6 A describes a natural P+/N-/N+ diode junction.Word line 20a contains P+ polysilicon (or other semi-conducting material).Bit line 30a ' contains the tri-layer film: N+ polysilicon 30a1 ', N-polysilicon 30a2 ', N-polysilicon 30a3 '.Word line 20a and bit line 30a ' are in contact with one another at its infall, and form a natural P+/N-/N+ diode junction 1nj.N-polysilicon 30a3 ' can another ties (omit and do not draw) naturally herein with word line 20a ' formation.Bit line 30a contains two level films: N-polysilicon 30a1, N+ polysilicon 30a2.Owing to have a block media 23 between word line 20a and the bit line 30a, therefore, can not form the nature knot between them.That is to say that storage element 20a/30a represents logical zero.If the storage element structure among Fig. 6 A is used in Fig. 5, then this 3D-MPROM can bear higher technological temperature.Such as address selection line 20a, the 20a ' among all accumulation layer ML 100, ML 200, the ML 300,30a, 30a ' can be made of the doped polycrystalline silicon 600 ℃ of left and right sides deposits.After all accumulation layers form, can use a high temperature (such as, about 900 ℃) annealing process step to activate impurity, between word line and bit line, form good natural diode junction.Because technological temperature is higher, the interconnection line of substrate integrated circuit preferably uses resistant to elevated temperatures conductor material, such as, the polysilicon of doping, refractory metal and alloy thereof or compound.

Fig. 6 B and Fig. 6 category-A seemingly, its difference contains metal material for the word line among Fig. 6 B, as tungsten, platinum etc.Naturally form a Schottky diode 1nj ' at word line 20a and bit line 30a ' intersection contact position.Similarly, this structure also can be used the high-temperature technology flow process, to form a good Schottky diode.In the case, word line 20a preferably contains refractory metal and alloy or compound.

Fig. 6 C and Fig. 6 category-A seemingly, but the square resistance of its word line and bit line little than among Fig. 6 A.In its word line and bit line, all added at least one metallic material film.In this embodiment, bit line 30a ' contains 5 level films: N-polysilicon 30a2 ', N-polysilicon 30a3 ', metallic material film 30a4 ', N+ polysilicon 30a5 ', N+ polysilicon 30a6 '.Add metal material 30a4 ' and can reduce parasitic series connection bit line resistance.Word line 20a contains 3 level films: metal material 20a1, P+ polysilicon 20a2, P+ polysilicon 20a3.Metal material 20a1 can reduce parasitic series connection word line resistance, thereby improves reading speed.Metal material 20a1,30a4 ', 30a3 can contain metal, metal alloy and/or metallic compound.Another kind of situation is to have only an address selection line to contain metal material in the storage element, and another address selection line still uses polysilicon, such as word line 20a uses the word line film among Fig. 6 C, and the bit line film among bit line 30a ' use Fig. 6 A.Similarly, the polycrystalline bit line among Fig. 6 B also can add metal material.This represents in Fig. 6 D.The another kind of method that reduces address selection line series connection dead resistance is the polysilicon among Fig. 6 A or Fig. 6 B to be carried out metal ion inject (metal ion implant).This method is not used independent metal level, can simplify technological process.

Fig. 7 A-Fig. 7 D is a kind of process chart of ISN 3D-MPROM.This technological process is very similar to the technological process among Fig. 3 A-Fig. 3 D.Fig. 7 A be form bit line bar and with layer in sectional view behind the dielectric planarization.Fig. 7 B is the sectional view after at formation block media 23 with by information opening mask photoresist 23pr being exposed.Fig. 7 C is the sectional view after block media 23 being carried out the figure conversion and forming the word line film.Fig. 7 D carries out y-z sectional view after etching and the complanation to word line.In conjunction with Fig. 6 A-Fig. 6 D, as can be seen, the technological process of ISN 3D-MPROM is very simple, when especially the unit of the ISN 3D-MPROM among Fig. 5 uses the embodiment of Fig. 6 A-Fig. 6 B.Their word line and bit line only contain a kind of material, and its etching is easy to implement.Simultaneously, use the 3D-MPROM of nature knot not need an independent etch step to define 3D-MPROM.Compare with other 3D-MPROM meta structure, simplified technological process.

Fig. 8 is an interlayer separation, autoregistration, the sectional view of knot 3D-MPROM (separateself-aligned natural-junction 3D-MPROM abbreviates SSN 3D-MPROM as) naturally.Similar with Fig. 4, it contains the accumulation layer ML 100 and the ML 200 of two separation, is separated by inter-level dielectric 27 between them.

Fig. 9 A-Fig. 9 D represents the structure chart of several SSN 3D-MPROM unit.Because adjacent accumulation layer does not have shared word line and bit line in SSN3D-MPROM, so their structure simple in structure than among Fig. 6 A-Fig. 6 D.Fig. 9 A represents a natural P+/N-/N+ diode junction 1nj who forms between word line 20a and bit line 30b.Fig. 9 B is illustrated in the natural Schottky diode junction 1nj ' that forms between word line 20a and the bit line 30b.The difference of Fig. 9 C and Fig. 9 A is to have added metallic material film 20a1,30b3 in its word line and bit line.Similarly, also can only in an address selection line (especially word line), add metal material.The difference of Fig. 9 D and Fig. 9 B is to have added among the bit line 30b metallic material film 30b3.These metallic material film 20a1,30b3 can reduce the parasitic series resistance of address selection line, thereby improve reading speed.The another kind of method that reduces address selection line series connection dead resistance is the polysilicon among Fig. 9 A or Fig. 9 B to be carried out metal ion inject (metal ion implant).This method is not used independent metal level, can simplify technological process.

For 3D-MPROM chip A that is loaded with different digital information and chip B, their word-line/bit-line figure is all identical.These figures have very strong repeatability.They can form by existing photoetching technique at an easy rate.The unique figure that can distinguish chip A and chip B is the information opening figure.The mask of word-line/bit-line can be used in all 3D-MPROM product families (chip A and chip B).Because the output of all 3D-MPROM product families is very big, so with after these mask cost sharing are in all chips, the shared ratio of word-line/bit-line mask is very low in each chip cost; On the other hand, information opening mask is only used in chip A or chip B.May be little because of output, the shared ratio of information opening mask may be bigger in each chip cost.Figure 10 A-10D represents to use 2F information opening mask (2F info-opening mask abbreviates 2F-IOM as) to reduce a kind of method of information opening mask cost.

Figure 10 A represents among the 3D-MPROM information opening figure (1ca...) with respect to word line and bit line.Utilize access opening can adopt this information opening figure as the 3D-MPROM (if any access opening presentation logic " 1 ", no access opening presentation logic " 0 ") of information opening (1ca...).These access openings need drop in the intersection region of word line and bit line in general.Thereby the size of information opening (1ca...) preferably is less than or equal to the live width of address selection line, i.e. 1F live width.United States Patent (USP) 5,835, the embodiment in 396 among Fig. 6 B can use this kind information opening.Figure 10 B represents the information opening mask 23msk (info-openingmask abbreviate IOM) corresponding with this information opening.Because its minimum dimension is the live width of address selection line, i.e. 1F (minimum dimension of this technology of F-), we claim that this mask 23msk is a 1F information opening mask (1F-IOM).And with respect to the embodiment among Fig. 2 among the present invention-Fig. 9 D, because of inter-level dielectric 26 can be used as the etching stopping film of etching information opening, the size of information opening can be done than the live width of address selection line wide (seeing Fig. 3 B and Fig. 7 B).And adjacent information opening may be incorporated in together.This information opening figure (1ca+...) is represented by Figure 10 C.Figure 10 D represents corresponding information opening mask 23msk+.The minimum dimension of this mask 23msk+ is 2F.We claim that this mask 23msk+ is a 2F information opening mask (2F-IOM).Simultaneously, the alignment precision of this mask 23msk+ and its INFERIOR GRAPH requires lower.For the 3D-MPROM technology of using 0.25 μ m, information opening mask can be used the technology of 0.5 μ m.This can greatly reduce mask cost and technology cost.

Embodiment in Fig. 2-Fig. 9 D can use the 2F-IOM, and other 3D-MPROM also can use 2F-IOM, as the seamless 3D-MPROM unit in U.S. Patent application 60/332,893, the Chinese patent application 01129103.6.Figure 11 A-Figure 11 C has represented to use a kind of technological process of the seamless 3D-MPROM of 2F-IOM.The front-end process flow process of this 3D-MPROM is existing the description in above-mentioned patent application, omits at this.Figure 11 A among the present invention is right after the Figure 31 in the above-mentioned patent application.After forming 3D-MPROM heap 69, medium 68 in the packed layer in the space between address selection line 64, and with its complanation.This planarization steps exposes top buffer film 60.Then, on the surface of complanation, form block media 67d and photoresist 67pr also by the exposure of information opening mask.Be exposed at logical one storage element place photoresist and remove, to form information opening 67.This is represented by Figure 11 B.Afterwards, etching block media 67d is to form top metal film 65.Top metal film 65 and top buffer film 60 are collectively referred to as top electrode 66.Because the top buffer film has certain thickness, in the process of etching block media film 67d, can allow some overetch; Perhaps, block media 67d and inter-level dielectric 68 can use different materials, and the etching technics that selection has better etching selection ratio in etching process, and like this, this etching technics step is unlikely to have influence on accurate conductive membrane 62.Correspondingly, the size of information opening 67 can be greater than the live width of address selection line 64.That is to say that this is seamless, and 3D-MPROM unit can use 2F-IOM.

3D-EPROM

Concerning 3D-EPROM, the user can in use programme.In order to shorten the chip programming time, hope can be programmed a plurality of storage elements simultaneously.Figure 12 has represented a kind of implementation method of synchronous programming.Symbol 1ca-1cd represents 3D-EPROM unit.In this special case, need programme simultaneously to storage element 1cb and 1cc.Correspondingly, the voltage on the word line 20c rises to V _PpVoltage on bit line 30b, the 30c reduces to 0, and the voltage of all other address selection lines is V _Pp/ 2.Therefore, the voltage that is added on storage element 1cb, the 1cc is a program voltage, and the voltage that is added on other storage element has only V _Pp/ 2.Thereby storage element 1cb, 1cc are programmed simultaneously.

Figure 13 A-Figure 13 B represents two 3D-EPROM units, and is similar with Fig. 6 C-Fig. 6 D and Fig. 9 C-Fig. 9 D, added metallic material film 20a1,30c3 in the polycrystalline address selection line.The parasitic series resistance of address selection line can be reduced like this, thereby programming more easy (under same program conditions, can provide bigger program current) can be made; Simultaneously, reading speed also can accelerate (because RC postpones to shorten).The another kind of method that reduces address selection line series connection dead resistance is the polysilicon among Figure 13 A or Figure 13 B to be carried out metal ion inject (metal ionimplant).This method is not used independent metal level, can simplify technological process.Anti-fuse film 22af can be clipped in (as Figure 13 A, Figure 13 B) between N+ polysilicon 30c2 and the N-polysilicon 30c1, and it also can be clipped between the P+ polysilicon 20a2 and N-polysilicon 30c1 of Figure 13 A, or is clipped between the word line 20a and N-polysilicon 30c1 of Figure 13 B.Anti-fuse film 22af can be one deck ONO film, and it can form by following steps: at first heat grows into a SiO on N+ polysilicon 30c2 ₂Film then, forms a silicon nitride film by CVD again, after this, forms another SiO again by the heat growth ₂Film.

3D-ROM

In order to improve the capacity of 3D-ROM, a kind of method is to improve its array efficiency.Array efficiency is defined as the real area of storage array and the ratio of entire chip area.For the memory that is made of conventional transistor, their storage array and peripheral circuit all are formed in the substrate, and promptly substrate circuitry must form at storage array " outside ".Like this, its array efficiency is generally lower.Usually the numeral of report is about 70%.In 3D-ROM, have only peripheral circuit in substrate, to form, storage array is positioned on the substrate.Therefore, most of peripheral circuit can be folded into the storage array below, promptly peripheral circuit is in storage array " the inside ".Like this, the shared chip area maximum of storage array is almost chip area; Simultaneously, when chip contained a plurality of storage array, the space between the storage array can be littler.Thereby, can obtain being bordering on desirable array efficiency.Figure 14 A-Figure 14 F has described two kinds of implementation methods that improve array efficiency.

Figure 14 A-Figure 14 B has described a 3D-ROM with private wiring layer.The notion of this wiring layer is by United States Patent (USP) 5,835, and 396 propose, and in this special case, four layer address selection wire: 20a ', 30a ', 20a, 30a are arranged.Every layer address selection wire has private wiring layer a: 1r1,1r2,1r3,1r4 respectively,

i.e. word line

20a, and 20a ' uses wiring layer 1r2,1r4 respectively, and

bit line

30a, 30a ' use wiring layer 1r1,1r3 respectively.Here, wiring layer 1r2 is folded to the storage array below with the contact point 20act1 of word line 20a and substrate perimeter circuit 000.Correspondingly, the decoder of word line 20a can be placed on the storage array below; Wiring layer 1r1 is folded to the storage array below with the contact point 30act1 of bit line 30a and substrate perimeter circuit 000.Correspondingly, the decoder of bit line 30a can be placed on the storage array below.Wiring layer 1r3,1r4 also have similar functions.Because use private wiring layer, peripheral circuit can almost be arranged in any position of storage array below.Figure 14 C represents that one is folding and it is disposed to the peripheral circuit of storage array below by wiring layer.In this special case, every address selection line of storage array is all driven by two decoders that are positioned at the address selection line two ends.Use the address selection line of this structure that bigger drive current can be arranged.This structure is particularly suitable for word line and the bit line of 3D-EPROM, and the word line of 3D-MPROM, because these address selection lines need that bigger drive current can be arranged.Here, row decoder 40l, 40r are placed on storage array the right and left, and

column decoder

42t, 42b are placed on storage array both sides up and down.Column decoder on four angles of storage array be placed on storage array slightly in below the position.Wiring connecting line 1r3 gives between these column decoder 42t1 far away and their respective bit line electrical connection is provided.Like this, row decoder and column decoder all are positioned at the border of storage array 00.Because these decoders all are arranged in the address selector two ends, therefore, they can be to address selection line two ends while input current.

Figure 14 D, Figure 14 E have described the 3D-ROM of a shared wiring layer.In this embodiment, two-layer address selection line is shared a wiring layer, such as word line 20a and bit line 30a share wiring layer 1r1; Word line 20a ' and bit line 30a ' share wiring layer 1r2.Here, wiring layer 1r2 is folded to the storage array below with the contact point 20act2 of word line 20a ' and substrate perimeter circuit 000, and the contact point 30act2 ' of bit line 30a ' and substrate perimeter circuit 000 is folded to below the storage array.Wiring layer 1r1 also has similar functions.Figure 14 F is to use this wiring layer method for folding and it is arranged into the peripheral circuit of storage array below.Row decoder is divided into two hemistich decoder 40l ', 40r '.Hemistich decoder 40l ' is responsible for the word line 20m... of storage array the first half is driven, and it is folded the upper left limit that is arranged in storage array; Hemistich decoder 40r ' is responsible for the word line 20p... of storage array the latter half is driven, and it is folded the limit, bottom right that is arranged in storage array.In Figure 14 F, word line is only driven by the decoder that is positioned at word line one end, and promptly word line current is only imported from an end.The situation of bit line, column decoder and word line, row decoder are similar.

Among Figure 14 A-Figure 14 F peripheral circuit is folded to the design of storage array below, is particularly suitable for containing the 3D-ROM of certain scale substrate circuitry.3D-ROM can utilize the ready-made interconnection line layer of substrate circuitry as its wiring layer.Correspondingly, do not need to make extra interconnection layer for its wiring layer.

Figure 15 is the sectional view of a 3D-ROM.Of U.S. Patent application 60/332,893 and Chinese patent application 01129103.6,3D-ROM visits the parasitic capacitance that is proportional to bit line time of delay first.The bit line parasitic capacitance comes from the coupling capacitance between the wall of bit line limit greatly, as the coupling capacitance between bit line 30j and the bit line 30i.Along with development of technology, this coupling capacitance will be in whole bit line parasitic capacitance proportion more and more big.In order to reduce this coupling capacitance, can use thin bit line.Though this can increase bit line resistance to a certain extent, bit line resistance is compared with accurate conductive membrane resistance, and is generally less.The resistance of accurate conductive membrane is the main resistance factor that decision 3D-ROM visits time of delay first.On the whole, use thin bit line can shorten the time of delay of visiting first of 3D-ROM.In read procedure, word line will provide big electric current simultaneously, in order to overcome electromigration problems such as (electromigration), preferably uses thicker word line.

Figure 16 A represents a 3D-ROM storage array and is arranged in its interconnecting channels hole 20av-20dv all around.These interconnecting channels holes 20av-20dv provide electrical connection to 3D-ROM array and peripheral circuit thereof.Figure 16 B represents along A ' A " sectional view.Because distance is the minimum range of this technology between the word line, these interconnecting channels holes 20av-20hv constitutes " wall that can't go beyond " together.As the substrate that stands in storage array below toward around see, these interconnecting channels hole 20av-20hv and storage array form multiple tracks " airtight net ", when a substrate integrated circuit and 3D-ROM integrated, this road " airtight net " was difficult to and extraneous (as pressure welding point, terminal pin) interface the substrate circuitry of 3D-ROM array below.

Figure 16 C, 16D provide a kind of method that addresses this problem.They have adopted the embedded interface connection.This method is particularly suitable for designs such as turning-over of chip (flip-chip), BGA.Figure 16 C is its plane graph, and Figure 16 D is that it is along B ' B " sectional view.Shown in Figure 16 B, leave the gap between many address selection lines.As between word line 20p and 20q, leaving the first gap 20gp, between bit line 30p and 30q, leave the second gap 30gp.Can be used for forming a platform pad (landing pad) 20lp1 by the space that forms between the first gap 20gp and the second gap 30gp.If this class gap is all arranged on this position of each accumulation layer ML 100, ML 200, then by platform pad 20lp1,20lp1 ' and interconnecting channels hole 20lv1,20lv2,20lv3, the substrate circuitry 000 of 3D-ROM array below and extraneous (as pressure welding point, lead-foot-line etc.) interface.So just form interface and connected 20ei.Be embedded in the storage array because these interfaces connect 20ei, so they are known as the embedded interface connection.Embedded interface connects 20ei provides electrical connection on vertical (z) direction to substrate circuitry.It can be distributed in the optional position of chip.It is generally shorter that embedded interface connects the length of 20ei, can improve interface rate like this.

Figure 16 E-Figure 16 F provide the another kind of method that solves extraneous interface problem.It folds by address selection line and forms the interface channel.Figure 16 E is its plane graph, and Figure 16 F is that it is along C ' C " sectional view.Shown in Figure 16 E, word line 20a-20h is divided into two groups of 20a-20d, 20e-20h.Every group of word line all is folded.Like this, interconnecting channels hole 20av-20dv, the position of 20ev-20hv turns to than the position among Figure 16 A.Correspondingly, shown in Figure 16 F,, form interface channel 20gpa, 20gpa ', 20gpb, 20gpb ' between the 20hv at interconnecting channels hole 20dv.These interface channels 20gpa, 20gpa ', 20gpb, 20gpb ' provide and extraneous (as pressure welding point, lead-foot-line etc.) interface to substrate circuitry.

The application of 2FOM

2F-IOM not only can use in masking film program read-only memory, also has other extensive uses.It can use in masking film program gate array (MPGA), field programming gate array (FPGA) based on anti-fuse (antifuse), even can use in general integrated circuit the interlayer contact as interconnection line.In these were used, 2F information opening mask are referred to broadly as 2F opening mask (2Fopening mask abbreviates 2FOM as).

Figure 17 A-Figure 17 B represents that one uses 2FOM to realize the masking film program gate array (MPGA) of the interlayer contact of interconnection line.This method also can be used in general integrated circuit the interlayer contact as interconnection line.Masking film program gate array (MPGA) is widely used in industrial quarters, as the Hardcopy product of altera corp.Similar with read-only memory, it is by programming to chip to the opening mask.Simultaneously, the shared large percentage of each chip cost split shed mask.MPGA also can use 2FOM to reduce opening mask cost.In this embodiment, MPGA carries out the selectivity connection by opening between the first interconnection line 90a-90c and the second interconnection line 80a-80c: the opening 84 at 7bb place links to each other the first interconnection line 90b with the second interconnection line 80b; The block media 83 at 7bc place then separates the first interconnection line 90b and the second interconnection line 80c.Block media 83 can have a side wall (tapered sidewall) that tilts.Can prevent from like this to produce separation structure (spacer) in etching process, this can be clear that in Figure 18 D.In Figure 17 A-Figure 17 B, the size of opening 84 can be done widelyer than the live width of interconnection line, and adjacent opening may be incorporated in together.Simultaneously, the alignment precision of opening mask and its INFERIOR GRAPH requires lower.For the MPGA technology of using 0.25 μ m, the opening mask can be used the technology of 0.5 μ m.This can greatly reduce mask cost and technology cost.

Figure 18 A-Figure 18 E is a kind of process chart of this MPGA.It and Fig. 7 A-Fig. 7 D are very similar.Figure 18 A be form the first interconnected lines 90b-90c and with ground floor in sectional view after medium 86 complanations.Figure 18 B is forming block media 83 and by the sectional view of opening mask after to resist exposure.Figure 18 C is the sectional view after block media 83 being carried out the figure conversion and forming the second interconnection line film 80b.Figure 18 D carries out y-z sectional view after the etching to the second interconnection line film 80b.Here, the inclination side wall (taperedsidewall) of block media 83 can prevent to produce separation structure (spacer) in this step process.This inclination side wall also can use in the embodiment of Fig. 2, Fig. 4, Fig. 5, Fig. 8.Figure 18 E is to the sectional view after medium 88 complanations in the second layer of the second interconnection line 80b.

The another kind of implementation method of Figure 18 D ' demonstration second interconnection line 80b.It uses twice complanation (dual damascene).After Figure 18 C carries out etching to block media 83, form the interior medium 88 of the second layer earlier and it is carried out the figure conversion.This figure conversion had better not excessive damage block media 83 and the interior medium 86 of ground floor.Then, the deposit second interconnection line film 80b and with its complanation to form the structure of Figure 18 E.

Figure 19 represents that one uses 2FOM and based on the field programming gate array (FPGA) of anti-fuse (antifuse).The similar of its structure and Figure 17 B.Unique difference is to have formed an anti-fuse film 96 in opening 84.Like this, form an anti-fuse 7bb of unit between the first interconnection line film 90b and the second interconnection line film 80b.

Though above specification has specifically described examples more of the present invention, those skilled in the art should understand, and under the prerequisite away from the spirit and scope of the present invention not, can change form of the present invention and details.This does not hinder them to use spirit of the present invention.Therefore, except the spirit according to additional claims, the present invention should not be subjected to any restriction.

Claims

1. a manufacture method that contains the three-dimensional masking film program read-only memory (3D-MPROM) of a plurality of accumulation layers comprises the following steps:

1) forms the first address choice lines (30b) by first etching;

2) on the first address choice lines, form a block media film (23), and optionally in this block media film, form information opening (24) according to information opening mask;

3) be etched in the formation second address choice lines (20a) on this block media film by second;

4) this first and second is etched between these first and second address choice lines and forms a 3D-MPROM film (22), and this 3D-MPROM film is rectangular, and two opposite side of this rectangle are formed by this first etching, and another two opposite side is formed by this second etching.

2. three-dimensional masking film program read-only memory (3D-MPROM) that contains a plurality of accumulation layers, its accumulation layer (ML100) is characterised in that and contains:

One first address selection line (30b);

One is positioned at the block media film (23) of this first address selection line top, has information opening (24) in this block media film;

One is positioned at second address selection line (20a) of this block media film top;

One 3D-MPROM film (22) between this first and second address selection line, this 3D-MPROM film is rectangular, and two opposite side of this rectangle are aimed at the two side of this first address selection line, and another two opposite side is aimed at the two side of this second address selection line.

3. a manufacture method that contains the three-dimensional masking film program read-only memory (3D-MPROM) of a plurality of accumulation layers comprises the following steps:

1) forms the first address choice lines (30b);

3) on this block media film, form the second address choice lines (20a), these first and second address choice lines are in contact with one another and form one at the information opening part and tie (1nj naturally, 1nj '), this is tied naturally has accurate on state characteristic: when add thereon voltage less than read voltage or with read voltage direction when opposite, its resistance is bigger.

4. three-dimensional masking film program read-only memory (3D-MPROM) that contains a plurality of accumulation layers, its accumulation layer (ML100) is characterised in that and contains:

One first address selection line (30b);

One is positioned at second address selection line (20a) of this block media film top, this first and second address selection line is in contact with one another and forms one at the information opening part and ties (1nj naturally, 1nj '), this is tied naturally has accurate on state characteristic: when add thereon voltage less than read voltage or with read voltage direction when opposite, its resistance is bigger.

5. three-dimensional masking film program read-only memory (3D-MPROM) that contains a plurality of accumulation layers is characterized in that containing:

One first address selection line (30b);

One is positioned at the first block media film (23) of this first address selection line top, has first information opening in this first block media film;

One is positioned at second address selection line (20a) of this first block media film top;

One is positioned at the second block media film (23 ') of this second address selection line top, has the second information opening in this second block media film;

The one three-address selection wire that is positioned at this second block media film top (30b ');

This first and second address selection line is the address selection line of first accumulation layer (ML 100), this second and the three-address selection wire be the address selection line of second accumulation layer (ML 200).