CN1328794C - EEPROM and its mfg. method - Google Patents
EEPROM and its mfg. method Download PDFInfo
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- CN1328794C CN1328794C CNB031506372A CN03150637A CN1328794C CN 1328794 C CN1328794 C CN 1328794C CN B031506372 A CNB031506372 A CN B031506372A CN 03150637 A CN03150637 A CN 03150637A CN 1328794 C CN1328794 C CN 1328794C
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Abstract
The present invention provides an electric erasable programmable read-only memory which comprises a silicon substrate, a first oxidizing layer formed on the silicon substrate, a second oxidizing layer, a polysilicon floating grid formed on the first oxidizing layer, an oxide / nitride / oxide dielectric layer covering the polysilicon floating grid, a polysilicon control grid and a polysilicon selection grid formed on the second oxidizing layer, wherein the thickness of the second oxidizing layer is larger than that of the first oxidizing layer; the polysilicon control grid formed on the dielectric layer completely covers the floating grid. The present invention also provides a method for manufacturing the electric erasable programmable read-only memory. Because the device of the present invention has no tunnel oxide window, the present invention simplifies manufacturing process and can keep high ratio of grid coupling under the condition of the reduction of device dimension.
Description
Technical field
A kind of Electrically Erasable Read Only Memory of relate generally to of the present invention (EEPROM) and manufacture method thereof more specifically, relate to the Electrically Erasable Read Only Memory and the manufacture method thereof of a kind of cellular construction with simplification and littler cell size.
Background technology
Electrically Erasable Read Only Memory (EEPROM) is a kind of widely used semiconductor storage unit, its existing random-access memory (ram) is the readable characteristic of writing in on-line operation, has non-volatile read-only memory (ROM) still can be preserved all storage data after power down advantage again.Its great advantage is directly to wipe with the signal of telecommunication, and also capable telecommunications number writes.
The EEPROM unit selects transistor and a memory transistor to form by one usually.Wherein memory transistor comprises by the floating boom utmost point and the stacked gate structure that constitutes of control grid, and the floating boom utmost point is used for store electrons, and the control grid is used for the access of control information.Drain region and source region are formed in the substrate, lay respectively at the both sides of stacked gate structure.Between the control grid and the floating boom utmost point, has a dielectric layer.Part at the floating boom utmost point and drain region overlapping has the extremely thin tunnel oxidation layer of one deck.EEPROM utilizes tunnel effect to realize writing and wiping of information.
Figure 1A-1L represents the conventional fabrication processes flow process of EEPROM.At first utilize local oxidation of silicon technology (LOCOS) or shallow ditch groove separation process (STI) on P type silicon substrate 100, to form field oxide 103, thereby define several area of isolation: low pressure peripheral circuit region 110, high-voltage peripheral circuits district 120 and memory block 130.
Set up after the isolated area deposition one deck sacrificial oxide layer 105 on silicon substrate 100.Apply one deck photoresist 106 then and it is carried out graph exposure, develops and carry out the ion injection, the ion that is injected is As or P, forms two n type zones 131.Then, remove photoresist and sacrificial oxide layer, and deposition of thick gate oxide level 132.
Carry out the fenestration procedure of tunnel oxide then.On gate oxide level 105, apply one deck photoresist 107, utilize mask to carry out graph exposure, development, thereby form an opening 135, the gate oxide at tunnel oxide window reserved location place is come out, prepare to carry out wet etching.
Carry out wet etching then.The gate oxide of opening 135 bottoms eroded expose silicon substrate, form tunnel oxide window 134.In window region 134 deposition thin layer of tunnel oxide 136.
Next, deposit first polysilicon layer 137 and carry out photoetching, corrosion, form and select grid 141, the floating boom utmost point 142 and high pressure grid 121.Deposition oxide/nitride/oxide (ONO) structure sheaf 138 and etching form the dielectric layer 138a that covers above the floating boom utmost point 142 then.Deposition low-pressure area oxide.Deposit second polysilicon layer again and carry out photoetching, corrosion, form control grid 143 and low pressure grid 111.
Pass through n at last again
+Or p
+Subsequent treatment process such as ion injects, the deposition of interlayer dielectric and complanation are finished the manufacture process of EEPROM.
Fig. 3 shows the plane graph of the EEPROM cellular construction made from traditional handicraft, wherein use with Fig. 1 in identical Reference numeral refer to part identical in the device.As can be seen, there is a tunnel oxide window region 134 the floating boom utmost point 142 belows from Fig. 1 and Fig. 3, and control grid 143 covers on the floating boom utmost point 142 fully to keep higher gate coupled ratio.
There is a shortcoming in the conventional fabrication processes of EEPROM: promptly, an operation that forms the tunnel oxide window below the floating boom utmost point is arranged in this manufacturing process.Deposited the very thin tunnel oxide of one deck at described window place, and other position is a thick oxide layer.In order to form this tunnel oxide window, need in manufacturing process, increase a plurality of steps such as photoetching, corrosion, thereby cause EEPROM manufacturing process complexity.In addition, because the restriction of the technological limits in forming described tunnel oxide window procedure causes the device cell size bigger, restricted the further microminiaturization of device.In addition, in traditional handicraft, form with first polysilicon layer earlier and select the grid and the floating boom utmost point, and then form the control grid that covers the floating boom utmost point with second polysilicon layer.Because the restriction of optical registration promptly, keeps enough spaces between the control grid that must constitute at the selection grid and second polysilicon layer of first polysilicon layer formation, the difficulty that defines second polysilicon layer is bigger.Owing to have these defectives, need traditional EEPROM manufacturing process and cellular construction thereof be improved.
Summary of the invention
The objective of the invention is to address the above problem, a kind of improved electrically erasable programmable read-only memory (EEPROM) cell and manufacture method thereof are provided, so that simplified manufacturing technique, the reduction of device cell size still keeps higher gate coupled ratio simultaneously.
For this reason, the invention provides a kind of Electrically Erasable Read Only Memory, comprising: silicon substrate; Be formed on first oxide layer and second oxide layer of its thickness on the described silicon substrate greater than first oxide layer; Be formed on the floating polysilicon grid on described first oxide layer; Cover the oxide/nitride/oxide dielectric layer on the described floating polysilicon grid; Be formed on the polysilicon control grid utmost point that covers the described floating boom utmost point on the described dielectric layer, fully; And the polysilicon that is formed on described second oxide layer is selected grid.
Correspondingly, the present invention also provides a kind of method of making Electrically Erasable Read Only Memory, comprises step: provide silicon substrate; On described silicon substrate, form first oxide layer; On described first oxide layer, deposit first polysilicon layer, and it is carried out photoetching and corrosion, to form the floating boom utmost point; Carry out ion with the described floating boom utmost point as mask and inject, with below described first oxide layer, floating boom utmost point both sides form source region and drain region; Deposition oxide/nitride/oxide layer, and it is carried out photoetching and corrosion form to cover the dielectric layer of the floating boom utmost point; Form second oxide layer of thickness in the surface of silicon zone that is not covered greater than first oxide layer by described oxide/nitride/oxide dielectric layer; Deposit second polysilicon layer, and carry out photoetching and corrode being positioned at the selection grid on described second oxide layer and being positioned at the control grid that covers the described floating boom utmost point on the described dielectric layer, fully with formation.
Silicon substrate wherein can be that p type silicon substrate also can be a n type silicon substrate.Wherein first thickness of oxide layer as tunnel oxidation layer is 60～100 .The method that wherein forms tunnel oxide is deposition (chemical vapour deposition (CVD) or physical vapour deposition (PVD)) or thermal oxidation.The ion that the ion implantation step uses is As or P.
The manufacture method of Electrically Erasable Read Only Memory also should comprise some preliminary treatment and subsequent treatment operation.The formation of preliminary treatment such as n trap, p trap, the foundation of isolated area, the deposition of subsequent treatment such as interlayer dielectric and planarization etc.These treatment process all are the technology that well known to a person skilled in the art, the present invention does not improve these treatment process, so repeat no more the concrete operations of these treatment process.
Technical scheme disclosed according to the present invention owing to do not contain the tunnel oxide window in the unit, has been saved the steps such as needed photoetching, wet etching of windowing, and has simplified cellular construction and the manufacture process of EEPROM.On the other hand, because in the cellular construction that does not comprise the tunnel oxide window of the present invention, the control grid still cover fully floating boom extremely above, the two has still kept bigger overlapping area, so can reduce under the situation of device size, keep higher gate coupled ratio.
In addition, in EEPROM manufacturing process according to the present invention, after forming the floating boom utmost point, carry out ion at once and inject formation source region and drain region, the masking layer that so just can utilize the floating boom utmost point to inject as ion, therefore formed source region and drain region have self alignment effect with respect to floating boom, have good electrical properties.
In addition, use second polysilicon layer to form among the present invention and select grid, rather than resemble use first polysilicon layer in the traditional handicraft, simplified the definition of second polysilicon layer pattern like this.
Description of drawings
Fig. 1 is the cross-sectional view of each step in the traditional EEPROM manufacturing process flow.
Fig. 2 is the cross-sectional view of each step in the EEPROM manufacturing process flow of the present invention.
Fig. 3 is the schematic plan view according to the EEPROM cellular construction of traditional handicraft manufacturing.
Fig. 4 is the schematic plan view according to the EEPROM cellular construction of technology manufacturing of the present invention.
Embodiment
By below in conjunction with the detailed description of accompanying drawing to the preferred embodiment of the present invention, above-mentioned feature and advantage of the present invention will become clearly.
Fig. 2 A-2H illustrates the schematic cross section of each step in the manufacturing process flow of EEPROM unit according to the preferred embodiment of the invention.Need to prove, for some with prior art in identical pre-treatment step, do not described among the figure.For example, at first needing to utilize the photoresist pattern to carry out ion as mask injects to form n trap, p trap on silicon substrate, and utilize foregoing LOCOS or STI technology to form field oxide, limit low pressure peripheral circuit region, high-voltage peripheral circuits district and memory cell array zone.And the threshold voltage V that injects adjustment higher-pressure region N channel element and P channel element by ion
TThese pre-treatment step are to well known to a person skilled in the art technology, and the present invention does not improve these treatment process, so no longer be described in detail the concrete operations of these treatment process.
Improvement for more outstanding the present invention has done only shows the structure of an EEPROM unit that is positioned at the memory block in the accompanying drawing, and has omitted the demonstration in low pressure peripheral circuit region and high-voltage peripheral circuits district.Shown in Fig. 2 A, at first depositing a layer thickness by thermal oxidation or chemical vapor deposition (CVD) technology on the surface of P type silicon substrate 200 for example is the thin oxide layer 201 of 60～150 , and it will be used as the tunnel oxidation layer of EEPROM memory cell.Deposit first polysilicon layer by for example CVD technology on thin oxide layer 201 then, its thickness for example is 500～4000 .And through technologies such as photoetching, corrosion this first polysilicon layer is defined, to form the floating boom utmost point 202, shown in Fig. 2 B.
Then, carrying out the autoregistration ion injects.On device surface, apply one deck photoresist (not shown) and patterned, will carry out the zone that ion injects to expose.Photoresist with this patterning carries out the ion injection as mask then, and the ion that is injected is n type material such as As or P, and its dosage is generally 1E13～5E15/cm
2Thereby, below thin oxide layer 201, floating polysilicon grid 202 both sides form drain region 203a and source region 203b, shown in Fig. 2 C.Because this ion implantation step carries out after forming the floating boom utmost point 202 immediately, formed drain region 203a and source region 203b have self aligned effect with respect to the floating boom utmost point 202.
Utilize CVD to carry out the deposition of oxide/nitride/oxide (ONO) structure sheaf then, and utilize photoresist this ONO structure sheaf to be corroded, form the dielectric layer 204 that covers above the floating boom utmost point 202 as the mask (not shown).
Then, shown in Fig. 2 E, form the high pressure oxidation layer 205 that a layer thickness for example is 100～500 by for example thermal oxidation or CVD technology in the zone that is not covered by ONO dielectric layer 204, it will be as the transistorized grid oxic horizon of the selection that is used for the EEPROM memory cell.And then for example be second polysilicon layer of 500～4000 by CVD technology at the device surface deposit thickness, and through steps such as photoetching, corrosion this second polysilicon layer is defined, to form control grid 207 and to select grid 206.
Utilize traditional shallow doped-drain to handle (LDD) technology then, and technologies such as the deposition of interlayer dielectric, complanation, promptly can obtain electrically erasable programmable read-only memory (EEPROM) cell of the present invention.Need to prove that for simplicity's sake, top description concentrates on the forming process of EEPROM memory cell, and has omitted the description to the forming process of high pressure, low-voltage device.The cross section of the memory cell structure of Xing Chenging is shown in Fig. 2 H at last, and Fig. 4 shows its plane graph.As can be seen, do not contain the tunnel oxide window in the unit.Below the floating boom utmost point 202, the whole channel region 208 that is limited by drain region 203a and source region 203b utilizes the uniform same tunnel oxide 201 of thickness.And, be to select grid 206 to constitute by second polysilicon layer, thereby reduced the complexity that defines second polysilicon layer with different in the existing technology with control grid 207.On the other hand, in unit constructed in accordance, control grid 207 still covers on the floating boom utmost point 202 fully, has kept higher gate coupled ratio when simplifying cellular construction.
The preferred embodiments of the present invention have more than been described.Although described the present invention in a particular embodiment, the present invention also can other alternative well known to those skilled in the art realize, and can be applied in the manufacturing of integrated circuit.The above embodiment only to be for principle of the present invention and main points are described, and to be not to be in order limiting the scope of the invention.Those skilled in the art is in the scope of know-why of the present invention and spirit, and the various modifications that embodiment is carried out are all within protection scope of the present invention.
Claims (4)
1. method of making Electrically Erasable Read Only Memory may further comprise the steps:
Silicon substrate is provided;
On described silicon substrate, form first oxide layer;
On described first oxide layer, deposit first polysilicon layer, and it is carried out photoetching and corrosion, to form the floating boom utmost point;
Carry out ion with the described floating boom utmost point as mask and inject, with below described first oxide layer, floating boom utmost point both sides form source region and drain region;
Deposition oxide/nitride/oxide layer, and it is carried out photoetching and corrosion form to cover the dielectric layer of the floating boom utmost point;
Form second oxide layer of thickness in the surface of silicon zone that is not covered greater than first oxide layer by described oxide/nitride/oxide dielectric layer;
Deposit second polysilicon layer, and carry out photoetching and corrode being positioned at the selection grid on described second oxide layer and being positioned at the control grid that covers the described floating boom utmost point on the described dielectric layer, fully with formation.
2. the manufacture method of Electrically Erasable Read Only Memory as claimed in claim 1, wherein said first thickness of oxide layer is 60～150 .
3. the manufacture method of Electrically Erasable Read Only Memory as claimed in claim 2, wherein said second thickness of oxide layer is 100～500 .
4. as the manufacture method of each described Electrically Erasable Read Only Memory in the claim 1 to 3, the method that wherein forms described first oxide layer and second oxide layer is chemical vapour deposition (CVD) or thermal oxidation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031506372A CN1328794C (en) | 2003-08-29 | 2003-08-29 | EEPROM and its mfg. method |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031506372A CN1328794C (en) | 2003-08-29 | 2003-08-29 | EEPROM and its mfg. method |
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| CN1591879A CN1591879A (en) | 2005-03-09 |
| CN1328794C true CN1328794C (en) | 2007-07-25 |
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| CNB031506372A Expired - Lifetime CN1328794C (en) | 2003-08-29 | 2003-08-29 | EEPROM and its mfg. method |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101170064B (en) * | 2006-10-23 | 2010-05-12 | 上海华虹Nec电子有限公司 | Method for flash technology high-voltage bar oxygen and tunnel-penetration oxidation layer |
| CN101944511B (en) * | 2009-07-09 | 2012-07-25 | 中芯国际集成电路制造(上海)有限公司 | Method for making storage unit |
| CN102044545B (en) * | 2009-10-20 | 2013-03-27 | 中芯国际集成电路制造(上海)有限公司 | Flash memory of discrete gate and manufacturing method thereof |
| CN105870067B (en) * | 2015-01-22 | 2019-07-16 | 中芯国际集成电路制造(上海)有限公司 | The production method of P-channel flash memory |
| CN112563322A (en) * | 2020-12-01 | 2021-03-26 | 珠海博雅科技有限公司 | Field effect transistor and method for manufacturing the same |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5066992A (en) * | 1989-06-23 | 1991-11-19 | Atmel Corporation | Programmable and erasable MOS memory device |
| US5424232A (en) * | 1990-12-18 | 1995-06-13 | Sharp Kabushiki Kaisha | Method for manufacturing a non-volatile memory having a floating gate oxide type fet provided with a tunnel oxide film |
| CN1218294A (en) * | 1997-10-09 | 1999-06-02 | 美商常忆科技股份有限公司 | Nonvolatile PMOS two transistor memory cell and array |
| CN1228600A (en) * | 1998-02-18 | 1999-09-15 | 日本电气株式会社 | Nonvolatile semiconductor memory device having program area |
| CN1268248A (en) * | 1997-04-11 | 2000-09-27 | 硅芯片公司 | Nonvolatile semiconductor memory |
| CN1345466A (en) * | 1999-03-26 | 2002-04-17 | 硅芯片公司 | Nonvolatile memory |
| CN1380699A (en) * | 2001-04-11 | 2002-11-20 | 华邦电子股份有限公司 | Electrically-erasable programmable internal storage device and its production method |
-
2003
- 2003-08-29 CN CNB031506372A patent/CN1328794C/en not_active Expired - Lifetime
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5066992A (en) * | 1989-06-23 | 1991-11-19 | Atmel Corporation | Programmable and erasable MOS memory device |
| US5424232A (en) * | 1990-12-18 | 1995-06-13 | Sharp Kabushiki Kaisha | Method for manufacturing a non-volatile memory having a floating gate oxide type fet provided with a tunnel oxide film |
| CN1268248A (en) * | 1997-04-11 | 2000-09-27 | 硅芯片公司 | Nonvolatile semiconductor memory |
| CN1218294A (en) * | 1997-10-09 | 1999-06-02 | 美商常忆科技股份有限公司 | Nonvolatile PMOS two transistor memory cell and array |
| CN1228600A (en) * | 1998-02-18 | 1999-09-15 | 日本电气株式会社 | Nonvolatile semiconductor memory device having program area |
| CN1345466A (en) * | 1999-03-26 | 2002-04-17 | 硅芯片公司 | Nonvolatile memory |
| CN1380699A (en) * | 2001-04-11 | 2002-11-20 | 华邦电子股份有限公司 | Electrically-erasable programmable internal storage device and its production method |
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| CN1591879A (en) | 2005-03-09 |
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Effective date of registration: 20111202 Address after: 201203 No. 18 Zhangjiang Road, Shanghai Co-patentee after: Semiconductor Manufacturing International (Beijing) Corp. Patentee after: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Address before: 201203 No. 18 Zhangjiang Road, Shanghai Patentee before: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. |
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Granted publication date: 20070725 |