CN1360738A - 具有低导通电阻的高压功率金属氧化物半导体场效应晶体管 - Google Patents

具有低导通电阻的高压功率金属氧化物半导体场效应晶体管 Download PDF

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CN1360738A
CN1360738A CN00808381A CN00808381A CN1360738A CN 1360738 A CN1360738 A CN 1360738A CN 00808381 A CN00808381 A CN 00808381A CN 00808381 A CN00808381 A CN 00808381A CN 1360738 A CN1360738 A CN 1360738A
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理查德·A·布兰查德
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Abstract

提供一种功率MOSFET,包含第一导电类型的衬底。也是第一导电类型的外延层淀积在衬底上。第一体区和第二体区位于外延层中,在其间限定漂移区。体区具有第二导电类型。第一导电类型的第一源区和第二源区分别位于第一体区和第二体区中。在外延层的漂移区中位于体区下面的多个沟槽。沟槽从第一体区和第二体区向衬底延伸,用包含第二导电类型的掺杂剂的材料填充沟槽。掺杂剂从沟槽扩散到与沟槽相邻的外延层的部分中。

Description

具有低导通电阻的高压功率金属氧化物半导体场效应晶体管
相关申请
本申请与1999年6月3日提交的名称为“具有相当低的导通电阻的高压MOS栅结构(A High Voltage MOS-Gated Structure with aRelatively Low On-Resistance)”的美国临时专利申请No.相关。
发明领域
本发明总的来说涉及半导体器件，更具体地说涉及功率MOSFET器件。
发明背景
在如机动车电子系统、电源和电源管理方面采用功率MOSFET器件。这种器件在截止的状态应耐高压，在导通的状态应产生低压和高的饱和电流密度。
图1显示了N沟道功率MOSFET的典型结构。在该器件中，对于两个MOSFET单元来说，形成在N+硅衬底2上的N-外延硅层1包含p体区5a和6a、N+源区7和8。p体区5和6还可以包含深的p体区5b和6b。源-体电极12跨越外延层1的某些表面部分延伸，以接触源区和体区。在图1中，由N外延层1延伸到半导体上表面的部分形成两个单元的N型漏区。在N+衬底2的底部设置漏极(未独立示出)。包括氧化物和多晶硅层的绝缘栅极18位于体的沟道和漏区部分上。
图1所示的传统MOSFET的导通电阻很大程度上由外延层1中的漂移区电阻决定。该漂移区电阻又由外延层1的掺杂和层厚决定。然而，为了增加器件的击穿电压，外延层1的掺杂浓度必须减小，而层厚增加。图2显示了传统的MOSFET每单位面积的导通电阻与击穿电压之间的函数曲线图。遗憾的是，如曲线20所示，当击穿电压增加时，器件的导通电阻快速增加。当MOSFET工作在高压、特别是比几百伏更高的电压时，这种电阻的快速增加会产生问题。
图3显示了所设计的工作在更高电压、具有减小的导通电阻的MOSFET。该MOSFET公开于1998年的IEDM会刊(Proceedings of theIEDM，1998)26.2期第683页。除了该MOSFET包含从器件的体区5和6下面延伸到漂移区的p型掺杂区40和42之外，该MOSFET与图2所示的传统MOSFET相同。上述P型掺杂区40和42引起反压，该反压将不仅像传统的MOSFET一样在垂直方向建立，而且在水平方向也建立了反压。结果该器件可以得到与传统器件一样的反压，并具有减小的外延层1的厚度和增加的漂移区掺杂浓度。图2中的曲线25显示了图3所示的MOSFET每单位面积的导通电阻与击穿电压之间的函数关系。从图中可以清楚地看出，在更高的工作电压下，相对于图1所示的器件，基本上减小了该器件的导通电阻，器件的导通电阻与击穿电压主要是线性增加关系。
可以用包含多个外延淀积步骤的工艺顺序来制造图3所示的结构，每个淀积步骤后接着引入适当的掺杂剂。遗憾的是，进行外延淀积步骤很昂贵，因此制造的该结构的成本较高。
因此，希望提供一种制造图3所示的MOSFET结构的方法，该方法只需要最少数量的淀积步骤，以便能够制造廉价的器件。
发明综述
根据本发明，提供了一种功率MOSFET，该功率MOSFET包含第一导电类型的衬底。在该衬底上淀积第一导电类型的外延层。第一体区和第二体区位于外延层中，并在它们之间限定了漂移区。体区具有第二导电类型。第一导电类型的第一源区和第二源区分别位于第一体区和第二体区中。在外延层的漂移区中，多个沟槽位于体区下面。从第一体区和第二体区向衬底延伸的沟槽用包含第二导电类型的掺杂剂的材料填充。掺杂剂从沟槽扩散到与沟槽相邻的外延层的部分中，这样就形成了P型掺杂区，该P型掺杂区将在水平方向和垂直方向建立反压。
根据本发明的一个技术方案，填充沟槽的材料是多晶硅。
根据本发明的另一个技术方案，填充沟槽的多晶硅至少局部氧化。可选的是，该多晶硅可以接着再结晶以形成单晶硅。
根据本发明的另一个技术方案，填充沟槽的材料是电介质，例如二氧化硅。
根据本发明的再一个技术方案，填充沟槽的材料可以既包含多晶硅又包含电介质。
根据本发明的再一个技术方案，提供一种用于形成功率MOSFET的方法。该方法由提供第一导电类型的衬底和在衬底上淀积外延层开始。上述外延层具有第一导电类型。第一体区和第二体区形成在外延层中，以在其间限定漂移区。上述体区具有第二导电类型。第一导电类型的第一源区和第二源区分别形成在第一体区和第二体区中。在外延层的漂移区中形成多个沟槽。用具有第二导电类型的掺杂剂的材料填充沟槽。沟槽从第一体区和第二体区向衬底延伸。至少一部分掺杂剂从沟槽扩散到与沟槽相邻的外延层部分中。
附图的简要说明
图1显示了传统的功率MOSFET结构的截面图。
图2显示了对于传统的功率MOSFET和根据本发明构造的MOSFET来说，作为击穿电压的函数的每单位面积的导通电阻。
图3显示了一种MOSFET结构，与图1所示的结构相比，在相同的电压下工作，该MOSFET结构具有更低的每单位面积的导通电阻。
图4-6显示了根据本发明构造的功率MOSFET的各种实施例的相关部分。
图7显示了根据本发明构造的完整的功率MOSFET。
详细描述
根据本发明，通过首先蚀刻一对沟槽形成图3所示的P型区40和42，该对沟槽位于P型区40和42将要形成的位置的中心处。接着用富含掺杂剂的材料填充沟槽。材料中的掺杂剂扩散到沟槽的外面并进入形成器件漂移区的相邻的外延层中。所得到的外延层的掺杂部分形成P型区。填充沟槽的材料随着没有扩散到沟槽外面的掺杂剂一起留在最后的器件中。因此，该材料应选择那些不会对器件特性产生不利影响的材料。可以被用于填充沟槽的典型材料包括多晶硅或诸如二氧化硅之类的电介质。
图4-6显示了用来填充形成在外延硅层1中的沟槽44和46的材料的几种不同的组合。图4-6显示了沟槽44和46、外延层1和衬底2，为了清楚图4-6没有显示包含p体区和源区的功率MOSFET结构的上部。
在图4中，用掺杂的电介质，例如掺硼的二氧化硅，填充沟槽44和46。填充沟槽之后，硼扩散到相邻的外延层1中，以形成p型区40和42。填充沟槽的掺硼的二氧化硅留在最后的MOSFET器件中。
在图5中，至少用掺硼的多晶的硅即掺硼的多晶硅部分填充沟槽。填充沟槽之后，硼扩散到相邻的外延层1中以形成p型区40和42，填充沟槽所留下来的掺硼的多晶硅保留在最后的MOSFET器件中。或者，在进行扩散步骤之后可以全部或部分氧化多晶硅，以形成二氧化硅。因此用电介质即二氧化硅和所有残留的多晶硅填充留在最后的MOSFET器件中的沟槽。或者，在升高的温度下使沟槽中所有掺硼的多晶硅再结晶以形成单晶硅。在这种情况下，遗留在最后的MOSFET器件中的沟槽用单晶硅或与二氧化硅或其它的电介质相结合的单晶硅填充。
在图6中，首先用掺杂的多晶硅部分填充沟槽44和46，接着通过淀积电介质来完全填充沟槽。填充沟槽之后，硼扩散到相邻的外延层1中以形成p型区40和42。填充沟槽而遗留下来的掺硼的多晶硅和电介质保留在最后的MOSFET器件中。在某些情况下，在升高的温度下使掺硼的多晶硅再结晶以形成单晶硅。因此，遗留在最后的MOSFET器件中的沟槽用单晶硅和电介质填充。
图7显示了根据本发明构造的功率MOSFET。该MOSFET包含衬底2、外延层1、p体区5a和6a、深的p体区5b和6b、源区7和8和p型区40和42，其中沟槽44和46分别定位。图中还示出了栅极和源—体电极，栅极包含氧化物层48和多晶硅层49，源-体电极包含金属化层50。
图7所示的本发明的功率MOSFET可以根据任何传统的加工技术来制造。例如，可以进行下面一系列的典型步骤来形成图7所示的MOSFET。
首先，通过用氧化物层覆盖外延层1的表面形成氧化物掩模层，然后进行通常的曝光和构图以留下限定沟槽44和46的位置的掩模部分。利用活性离子蚀刻通过掩模开口将沟槽干蚀到一般10-40微米的深度。可以使每个沟槽的侧壁光滑。首先，采用干化学蚀刻从沟槽侧壁除去氧化物的薄层(一般大约500-1000埃)，以消除由活性离子蚀刻工艺而引起的损伤。然后在沟槽44和46以及掩模部分上生长牺牲二氧化硅层。通过缓冲氧化物蚀刻或HF蚀刻除去该牺牲层和掩模部分以便使所得到的沟槽侧壁尽可能光滑。
用先前提到的任何材料，例如多晶硅、二氧化硅或其组合填充沟槽44和46。在淀积过程中，通常用掺杂剂，例如硼，掺杂多晶硅或氧化物。接着进行扩散步骤以使掺杂剂扩散到沟槽的外面并进入周围的外延层中。如果遗留在沟槽中的材料是多晶硅，可以使其氧化或再结晶。
然后，在传统的N+掺杂的衬底2上生长N-掺杂的外延层1。对于400-800V器件，外延层1一般厚15-50微米，电阻率为15-60欧姆-厘米。然后，在淀积、掺杂和氧化有源区掩模和多晶硅层之后生长栅氧化物。如果需要，利用传统的掩模、离子注入和扩散工艺形成深的p体区5b和6b。深的p体区的剂量一般在大约1×1014-5×1015/cm2。然后，在传统的掩模、注入和扩散步骤中形成p体区5a和6a。在40-60KeV用大约1×1013-5×1014/cm2的剂量将硼注入到p体区中。
然后，采用光致抗蚀剂掩模工艺形成布图的掩模层，限定源区7和8。然后通过注入和扩散工艺形成源区7和8。例如，可以在80KeV将砷注入到源区中，浓度一般达到2×1015-1.2×1016/cm2的浓度。注入之后，砷扩散到大约0.5-2.0微米的深度。深p体区的深度一般在大约2.5-5微米范围内，而体区的深度在大约1-3微米的范围内。最后，以传统的方式除去掩模层，形成图7所示的结构。
以传统的方式通过形成和布图氧化物层以形成接触开口来实现DMOS晶体管。并且淀积和遮蔽金属化层50以限定源-体和栅电极。而且，采用焊盘掩模来限定焊盘接触。最后，在衬底的下表面上形成漏接触层(未示出)。
应注意当在先前提到的工艺中沟槽在形成p体区和深p体区之前形成时，本发明更普遍的是包含以下工艺，在该工艺中沟槽先于或后于任何或所有遗留的掺杂区形成。另外，在公开了用于制造功率MOSFET的特定的工艺顺序的同时，也可以采用其它的工艺顺序，而落入本发明的范围内。
与由传统技术构造的现有技术的器件相比，根据本发明构造的功率MOSFET器件具有许多优点。例如p型区的垂直掺杂剂梯度非常接近于0。通过改变引入的掺杂剂的量和用于扩散步骤的热循环的数量和周期可以精确地控制水平掺杂剂的梯度。此外可以改变引入的掺杂剂的量和水平掺杂剂梯度来优化器件的击穿电压和导通电阻。
在图7所示的本发明的实施例中，在体区的下面形成了p型沟槽。然而不是每一个p型沟槽都需要与其相结合的体区，特别是在管芯的周边或在含有焊盘或互连线的区中。
尽管这里已经具体说明和描述了各种实施例，但是应当理解在不离开本发明的精神和所要求的范围的情况下，本发明的修改和变化由上述教导所覆盖，并在附加的权利要求范围内。例如可以提供根据本发明的功率MOSFET，其中各种半导体区的导电类型与从这里所公开的相反。

Claims (23)

1.一种功率MOSFET，包括：
第一导电类型的衬底；
衬底上的外延层，所述外延层具有第一导电类型；
位于外延层中的第一体区和第二体区，在它们之间限定了漂移区，所述体区具有第二导电类型；
分别位于第一体区和第二体区中的第一导电类型的第一源区和第二源区；和
在外延层的漂移区中，位于所述体区下面的多个沟槽，所述沟槽用具有第二导电类型的掺杂剂的材料填充，所述沟槽从第一体区和第二体区向衬底延伸，所述掺杂剂从所述沟槽扩散到与沟槽相邻的外延层的部分中。
2.权利要求1的功率MOSFET，其中，所述填充沟槽的材料是多晶硅。
3.权利要求1的功率MOSFET，其中，所述填充沟槽的材料是电介质。
4.权利要求3的功率MOSFET，其中，所述电介质是二氧化硅。
5.权利要求1的功率MOSFET，其中，所述掺杂剂是硼。
6.权利要求2的功率MOSFET，其中，所述多晶硅至少局部被氧化。
7.权利要求2的功率MOSFET，其中，接着使所述多晶硅再结晶以形成单晶硅。
8.权利要求1的功率MOSFET，其中，所述填充沟槽的材料包含多晶硅和电介质。
9.权利要求1的功率MOSFET，其中，所述体区包含深体区。
10.一种形成功率MOSFET的方法，包括步骤：
提供第一导电类型的衬底；
在衬底上淀积外延层；所述外延层具有第一导电类型；
在外延层中形成第一体区和第二体区，以在其间限定漂移区，所述体区具有第二导电类型；
分别在第一体区和第二体区中形成第一导电类型的第一源区和第二源区；和
在外延层的所述漂移区中形成多个沟槽；
用具有第二导电类型的掺杂剂的材料填充沟槽，所述沟槽从第一体区和第二体区向衬底延伸；和
至少一部分所述掺杂剂从所述沟槽扩散到与沟槽相邻的外延层的部分中。
11.权利要求10的方法，其中，所述填充沟槽的材料是多晶硅。
12.权利要求10的方法，其中，所述填充沟槽的材料是电介质。
13.权利要求12的方法，其中，所述电介质是二氧化硅。
14.权利要求10的方法，其中，所述掺杂剂是硼。
15.权利要求11的方法，还包括至少部分氧化所述多晶硅的步骤。
16.权利要求11的方法，还包括在所述多晶硅再结晶以形成单晶硅的步骤。
17.权利要求10的方法，其中，所述填充沟槽的材料包含多晶硅和电介质。
18.权利要求10的方法，其中，所述体区包含深体区。
19.权利要求10的方法，其中，通过提供限定至少一个沟槽的掩模层和蚀刻由掩模层限定的沟槽来形成所述沟槽。
20.权利要求10的方法，其中，通过将掺杂剂注入和扩散到衬底中来形成所述体区。
21.一种根据权利要求10的方法制造的功率MOSFET。
22.权利要求6的功率MOSFET，其中，接着使所述多晶硅再结晶以形成单晶硅。
23.权利要求15的方法，还包括使所述多晶硅再结晶以形成单晶硅的步骤。
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US6689662B2 (en) 2004-02-10
US20040036138A1 (en) 2004-02-26
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