CN1688980A - 具有内部行高速缓存的内存集线器及访问方法 - Google Patents
具有内部行高速缓存的内存集线器及访问方法 Download PDFInfo
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Abstract
一种计算机系统,包括耦合到多个内存模块的一个控制器,每一个内存模块包括一个内存集线器和多个内存设备。内存集线器包括一个当从内存设备读取数据时存储数据的行高速缓存。当控制器不访问内存模块时,内存模块中的一个序列发生器生成从一行存储单元读取数据的请求。响应该生成的读取请求而读取的数据也存储在行高速缓存中。因此,在所访问的行中的读取数据可以存储在行高速缓存中,即使以前没有响应来自控制器的内存请求从内存设备读取该数据。
Description
技术领域
本发明涉及计算机系统,更具体地讲,本发明涉及一种具有把多个内存设备耦合到处理器或其它内存访问设备的内存集线器的计算机系统。
发明背景
计算机系统使用诸如动态随机访问存储器(“DRAM”)设备这样的内存设备存储由处理器所访问的指令与数据。通常把这些内存设备用作计算机系统中的系统存储器。在一个典型的计算机系统中,处理器通过处理器总线和内存控制器与系统存储器进行通信。处理器发布一个内存请求,该内存请求包括诸如读取命令这样的内存命令,以及指出将从其读取数据或指令的位置的地址。内存控制器使用命令与地址生成适当的命令信号,以及将施加于系统存储器的行与列地址。响应该命令与地址,在系统存储器和处理器之间传送数据。通常,内存控制器为系统控制器的一部分,而且内存控制器还包括用于把处理器总线耦合到诸如PCI总线这样的外部总线的总线桥电路。
尽管内存设备的操作速度正在不断增加,然而这一增加不能与处理器的操作速度的增加保持同步。把处理器耦合到内存设备的内存控制器的操作速度增加得更为缓慢。内存控制器和内存设备的相对慢的速度,限制了处理器和内存设备之间的数据带宽。
除了处理器和内存设备之间受限的带宽外,计算机系统的性能还受到延迟问题的限制,该延迟问题增加了从系统存储器设备读取数据所需的时间。更具体地讲,当把内存设备读取命令耦合到系统存储器设备时,例如耦合到同步DRAM(“SDRAM”)设备时,仅在多个时钟周期的延迟之后才能够从SDRAM输出读取数据。因此,尽管SDRAM设备能够同时以高数据率输出突发数据,但最初提供数据过程中的延迟可能会明显减慢使用这样的SDRAM设备的计算机系统的运行速度。
缓解内存延迟问题一种方案是,使用多个通过内存集线器耦合到处理器的内存设备。在内存集线器体系结构中,把系统控制器或内存控制器耦合到多个内存模块,每个内存模块包括一个耦合到多个内存设备的内存集线器。内存集线器有效地在控制器和内存设备之间路由内存请求和响应。使用这一体系结构的计算机系统可以具有较高的带宽,因为处理器可以在另一个内存设备响应先前的内存访问的同时,访问一个内存设备。例如,处理器可以把写入数据输出到系统中的内存设备之一,同时系统中的另一个内存设备正准备把读取数据提供给处理器。尽管使用内存集线器的计算机系统可以提供较优的性能,但出于多种原因,它们常常不能以最佳速度操作。例如,即使内存集线器可以向计算机系统提供较大的内存带宽,但它们仍会遭遇以上所描述的类型的延迟问题。更具体地讲,尽管处理器可以与一个内存设备进行通信,而同时另一个内存设备正准备传送数据,但有时在可使用来自另一个内存设备的数据之前,必须从一个内存设备接收数据。在这一情况下,在可以使用从另一个内存设备所接收的数据之前,必须从一个存储器设备接收数据,延迟问题继续减慢这样的计算机系统的操作速度。
已用于减小内存设备中延迟的一种技术是高速缓存,高速缓存保存最近从系统内存中访问的数据。高速缓存通常以静态随机访问存储器(“SRAM”)的形式出现,与通常用作系统存储器的动态随机访问存储器(“DRAM”)相比,SRAM具有较短的访问时间。另外,与DRAM系统存储器通过系统控制器等耦合到处理器不同,SRAM高速缓存通常直接耦合到处理器。由于高速缓存较快的速度以及高速缓存与处理器更为靠近,所以使用高速缓存可大大减小内存读取操作的延迟。
尽管传统的高速缓存已经减少了传统计算机系统中的内存访问延迟,但尚未以在使用内存集线器的计算机系统中提供最佳性能的方式,来使用高速缓存。特别是,与典型的内存集线器系统存储器的大得多的容量相比,典型的高速缓存的有限的存储容量使高速缓存不受重视,因为高速缓存的命中率偏低。这一问题由于难于将数据传送给高速缓存而加剧,该难于将数据传送给高速缓存可能成为随后内存请求的问题。更具体地讲,难以通过内存控制器从所有的内存模块把随后需要的数据耦合到处理器,并且然后从处理器耦合到高速缓存。另外,在使用内存集线器和通过处理器总线耦合于处理器的高速缓存的计算机系统中,维持高速缓存的一致性也可能是困难的,并且其可能要求大量的硬件资源维持高速缓存的一致性。而且,维持高速缓存的一致性所需的时间,可能会把存储器的性能减慢到这样的程度:可能损失使用高速缓存的性能优势。
因此,需要一种计算机体系结构,其提供内存集线器体系结构的优点,并且最小化了这样的系统中所共有的这种延迟问题,从而提供了一种具有较高带宽和低延迟的内存设备。
发明概述
把多个内存模块耦合于计算机系统中的控制器。每一个内存模块包括多个内存设备和一个内存集线器。内存集线器包括一个耦合于控制器的链路接口和一个耦合于内存设备的内存设备接口。链路接口从控制器接收用于访问至少一个该内存设备中的一行存储单元的多个内存请求。链路接口把该多个内存请求传送到内存设备接口,然后内存设备接口把该多个内存请求耦合到该多个内存设备,用于访问至少一个该内存设备中的一行存储单元。接下来,内存设备接口从该多个内存设备接收对至少一些该内存请求进行响应的读取数据。每一个内存集线器还包括耦合到内存设备接口的行高速缓存,用于接收和存储响应至少一个该内存请求的读取数据。包括在内存集线器中的序列发生器耦合到链路接口、内存设备接口以及行高速缓存。序列发生器生成内存请求,并且把该内存请求耦合到内存设备接口,以从响应从链路接口到内存设备接口所传送的内存请求而访问的一行存储单元中的存储单元读取数据。将来自响应所生成的内存请求而访问的行存储单元中的存储单元的读取数据也存储在行高速缓存中。较佳的做法是,当不从控制器接收内存请求时,序列发生器生成内存请求。
附图简述
图1是根据本发明的一个实例的计算机系统的结构图,在该计算机系统中,内存集线器包括在多个内存模块的每一个中。
图2是用于图1的计算机系统中的内存集线器的结构图。
发明详述
图1中描述了根据本发明的一个实例的计算机系统100。计算机系统100包括处理器104,用于执行各种计算功能,例如运行那些执行具体计算或任务的具体的软件。处理器104包括处理器总线106,处理器总线106通常包括地址总线、控制总线以及数据总线。通常把处理器总线106耦合到高速缓存108,如以上所提到的,高速缓存108通常为静态随机访问存储器(“SRAM”)。最后,把处理器总线106耦合于系统控制器110,有时也把系统控制器110称为“北桥芯片”或“内存控制器”。
系统控制器110充当各种其它部件通向处理器104的通信路径。更具体地讲,系统控制器110包括图形端口,通常把该图形端口耦合于图形控制器112,而图形控制器112耦合于视频终端114。还把系统控制器110耦合于一或多个输入设备118,例如键盘或鼠标器,以允许操作员与计算机系统100相接。通常,计算机系统100还包括一或多个诸如打印机这样的输出设备120,通过系统控制器110把输出设备120耦合于处理器104。通常,还通过系统控制器110把一或多个数据存储设备124耦合于处理器104,以允许处理器104向内部或外部存储媒介(未示出)存储数据或者从内部或外部存储媒介检索数据。典型的存储设备124的例子包括硬和软盘、盒式磁带、光盘只读存储器(CD-ROM)。
系统控制器110耦合到多个内存模块130a、b、…n,它们用作计算机系统100的系统存储器。较佳的做法是,通过高速链路134把内存模块130耦合于系统控制器110,高速链路134可以为光或电通信路径,或某一其它类型的通信路径。在高速链路134实现为光通信路径的情况下,例如,光通信路径可以呈现为一或多条光纤的形式。在这样的情况下,系统控制器110和内存模块将包括耦合于光通信路径的光输入/输出端口或独立的输入和输出端口。内存模块130示出为以多点配置的方式耦合于系统控制器110,在该多点配置的方式中,把单一的高速链路134耦合于所有内存模块130。然而,应该认识到,也可以使用其它的拓扑结构,例如点到点耦合配置,其中使用独立的高速链路(未示出)把每一内存模块130耦合于系统控制器110。也可以使用切换拓扑结构,其中通过交换器(未示出)有选择地把系统控制器110耦合于每一内存模块130。本领域技术人员将会明显意识到,也可以使用其它拓扑。
每一个内存模块130均包括内存集线器140,该内存集线器140用于控制对6个内存设备148的访问,在图2中举例说明的例子中,这6个内存设备为同步动态随机访问存储器(“SDRAM”)设备。然而,也可以使用更少或更多数目的内存设备148,当然,也可以使用除SDRAM设备之外的内存设备。通过总线系统150,内存集线器140耦合到系统存储器设备148的每一个,通常,总线系统150包括控制总线、地址总线以及数据总线。
图2中示出了图1的内存集线器140的一个实例。内存集线器140包括耦合到高速链路134的链路接口152。链路接口152的特性将依赖于高速链路134的特征。例如,在使用光通信路径实现高速链路134的情况下,链路接口152将包括光输入/输出端口,并且把通过光通信路径耦合的光信号转换成电信号。在任何情况下,较佳的做法是令链路接口152包括缓冲器,例如先进先出缓冲器154,用于当通过高速链路134接收内存请求时,接收和存储该内存请求。把内存请求存储在缓冲器154中,直至可由内存集线器对它们进行处理。
当内存集线器140能够处理内存请求时,把存储在缓冲器154中的内存请求之一传送到内存序列发生器160。内存序列发生器160把内存请求从输出于系统控制器110的格式转换成具有可以由内存设备148所使用的格式的内存请求。这些重新格式化的请求信号通常包括内存命令信号,这些内存命令信号从包括在由内存集线器140接收的内存请求中的内存命令获得;以及行和列地址信号,行和列地址信号从包括在由内存集线器140接收的内存请求中的地址获得。在内存请求是写入内存请求的情况下,重新格式化的请求信号通常包括写入数据信号,写入数据信号从包括在由内存集线器140接收的内存请求中的写入数据获得。例如,在内存设备148为传统的DRAM设备的情况下,内存序列发生器160将输出行地址信号、行地址选通(“RAS”)信号、激活高写/激活低读信号(“W/R*”)、列地址信号以及列地址选通(“CAS”)信号。较佳的做法是,把重新格式化的内存请求按内存设备148将使用它们的顺序从序列发生器160输出。
内存序列发生器160把重新格式化的内存请求施加到内存设备接口166。内存设备接口166的特性也将依赖于内存设备148的特征。在任何情况下,较佳的做法是令内存设备接口166包括缓冲器,例如FIFO缓冲器168,用于当从链路接口152接收内存请求时,接收和存储一或多个内存请求。把内存请求存储在缓冲器168中,直至可以由内存设备148对它们进行处理。然而,在内存设备接口166存储内存请求的情况下,内存设备接口166可以对该内存请求重新进行排序,以便能够按某种其它顺序把它们施加到内存设备。例如,可以按这样一种方式把内存请求存储在接口166中:使对诸如读取请求这样的一种请求的处理先于诸如写入请求这样的其它类型的请求。
以上把内存请求描述为由内存集线器140以一种格式进行接收,该格式不同于把内存请求施加到内存设备148的格式。然而,系统控制器110也可以把来自处理器104的内存请求(图1)重新格式化为一种可以由内存设备148进行使用的格式。在这样的情况下,序列发生器160不需要重新格式化内存请求。取而代之,序列发生器160可以按内存设备148使用所需的顺序,简单地调度重新格式化的内存请求信号。然后,把一或多个内存请求的内存请求信号传送到内存设备接口166,从而能够把它们随后施加到内存设备148。
如以上所解释的,使用内存集线器的缺点之一在于,增大了它们有时可以引发的延迟。同样如以上所解释的,作为减少内存读取延迟的传统的方案,处理器104中或耦合到处理器总线106的高速缓存(图1)不十分适合于使用内存集线器的内存系统。图2中所示的内存集线器140实例,通过把行高速缓存170包括在每一内存集线器140中,提供了相当低的内存读取延迟。在设计上,行高速缓存170类似于包括数据存储器(未示出)、标记存储器(未示出)以及传统地址比较逻辑(未示出)的传统高速缓存系统。行高速缓存170存储包括在模块140中的一或多个内存设备148的以前被寻址的一或多行存储单元中的数据。高速缓存170从链路接口152接收形成内存请求的一部分的地址,把这些地址与所高速缓存的地址加以比较。在地址匹配的情况下,即表明内存请求所索取的数据存储在行高速缓存170中,高速缓存170输出所请求的数据以及指示高速缓存命中的“ROW HIT”信号。把ROW HIT信号施加到多路复用器176,以使来自高速缓存170的数据耦合到链路接口152。在行高速缓存未命中的情况下,多路复用器176把来自内存设备接口166的数据耦合到链路接口152。也把ROW HIT信号施加到内存序列发生器160,以便在行命中的情况下,序列发生器不把内存请求耦合到内存设备接口166,因为行高速缓存170已经提供内存请求所调用的数据。
尽管行高速缓存170可以存储仅来自一行中先前被访问的各列的数据,但较佳的做法是,当内存集线器不忙于响应来自系统控制器110的内存请求时,高速缓存170从所高速缓存的行中的多个或全部列中预取数据。更具体地讲,内存序列发生器160包括传统的电路,以追踪所访问的行的哪些列已经将数据传送到行高速缓存170并存储在其中。当序列发生器160不忙于向来自链路接口152的内存请求提供服务时,序列发生器160生成施加到内存设备接口166的内存请求,以使存储在被寻址的行的其余各列中的数据传送到行高速缓存170。因此,由于内存访问通常为相同行中的一系列内存位置,所以行高速缓存170很可能存有在随后的内存请求中将被取出的数据。
内存集线器140可以使用各种程序,处理指向存储器设备148之一中的一新行存储单元的随后的内存请求。例如,如果行高速缓存170能够存储来自一行以上的数据,则序列发生器160可以简单地使存储在随后被访问的行中的数据传送到行高速缓存170。如果行高速缓存170能够存储仅来自单个行的存储单元的数据,或行高速缓存170已经达到了其存储容量,则可以简单地把存储在新近被访问的行的存储单元中的数据覆盖在先前所存储的数据上。
尽管图2中未加以描述,也未在以上加以讨论,但较佳的做法是令内存集线器140包括用于维持使用传统高速缓存技术的高速缓存的一致性的电路。例如,在向一个位置写入的内存请求之后跟随从同一位置读取的内存请求的情况下,集线器140可以使用“写通(write through)”操作模式或“写回”操作模式。
从以上的描述可以看出,尽管此处已说明性地描述了本发明的具体的实施例,然而在不背离本发明的构思与范围的情况下,可以对本发明进行多方面的修改。因此,本发明仅受所附权利要求的限制。
Claims (45)
1.一种内存模块,包括:
多个内存设备;以及
一个内存集线器,包括:
一个链路接口,接收用于对至少一个该内存设备中的一行存储单元进行访问的多个内存请求;
一个耦合到该多个内存设备的内存设备接口,该内存设备接口用于把多个内存请求耦合到该多个内存设备,以对至少一个该内存设备中的一行存储单元进行访问,并且接收对至少一些该内存请求进行响应的读取数据,耦合到该多个内存设备的至少一些内存请求的是对从该链路接口传送到该内存设备接口的多个内存请求的响应;
一个耦合到该内存设备接口的行高速缓存,用于接收和存储来自一行存储单元的读取数据,该一行存储单元响应从该内存设备接口耦合到所述至少一个内存设备的至少一个内存请求被访问;以及
一个序列发生器,耦合到该链路接口、该内存设备接口以及该行高速缓存,该序列发生器用于生成内存请求,并且把该内存请求耦合到该内存设备接口,以从所访问的行存储单元中的多个存储单元读取数据,将从所访问的行存储单元中的多个存储单元所读取的读取数据存储在该行高速缓存中。
2.根据权利要求1所述的内存模块,其中所述内存设备接口还包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储从所述链路接口和从所述序列发生器接收的内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述至少一个内存设备。
3.根据权利要求1所述的内存模块,其中所述链路接口包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述内存设备接口。
4.根据权利要求3所述的内存模块,其中所述内存设备接口还包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储从所述链路接口和从所述序列发生器接收的内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述至少一个内存设备。
5.根据权利要求1所述的内存模块,其中所述链路接口包括一个光输入/输出端口。
6.根据权利要求1所述的内存模块,其中所述内存设备包括动态随机访问存储器设备。
7.根据权利要求1所述的内存模块,其中所述序列发生器用于输出包括在从所述链路接口接收的每一读取内存请求中的地址,而且其中所述行高速缓存用于从所述序列发生器接收该地址,以判断内存请求所调用的数据是否存储在所述行高速缓存中,如果内存请求所调用的数据存储在所述行高速缓存中,则所述行高速缓存输出该读取数据,并生成命中信号,如果内存请求所调用的数据未存储在所述行高速缓存中,则生成行未命中信号。
8.根据权利要求7所述的内存模块,还包括一个多路复用器,该多路复用器具有耦合到所述行高速缓存和耦合到所述内存设备接口的数据输入端、耦合到所述链路接口的数据输出端、以及耦合用以从所述行高速缓存接收所述行高速缓存命中和行高速缓存未命中信号的控制输入端,该多路复用器响应所述行高速缓存未命中信号,耦合来自所述内存设备接口的读取数据,以及响应所述行高速缓存命中信号,耦合来自所述行高速缓存的读取数据。
9.根据权利要求1所述的内存模块,其中所述序列发生器用于仅当未把内存请求从所述链路接口传送到所述内存设备接口时,生成内存请求并把该内存请求耦合到所述内存设备接口,以从所访问的行存储单元中的存储单元读取数据。
10.一种内存模块,包括:
多个内存设备;以及
一个内存集线器,包括:
一个链路接口,接收用于对至少一个该内存设备中的一行存储单元进行访问的内存请求;
一个耦合到该多个内存设备的内存设备接口,该内存设备接口用于把多个内存请求耦合到该多个内存设备,以对至少一个该内存设备中的一行存储单元进行访问,并且接收对至少一些该内存请求进行响应的读取数据,耦合到该多个内存设备的至少一些内存请求是对从该链路接口传送到该内存设备接口的多个内存请求的响应;
一个序列发生器,耦合到该链路接口、该内存设备接口以及行高速缓存,该序列发生器用于输出包括在从该链路接口接收的每一读取内存请求中的地址;
一个耦合到该内存设备接口的行高速缓存,用于接收和存储来自一行存储单元的读取数据,该一行存储单元响应从该内存设备接口耦合到该至少一个内存设备的一个内存请求被访问,该行高速缓存还可用于从该序列发生器接收地址,以判断该内存请求所调用的数据是否存储在该行高速缓存中,如果该内存请求所调用的数据存储在该行高速缓存中,则该行高速缓存输出读取数据,并生成命中信号,如果该内存请求所调用的数据未存储在该行高速缓存中,则生成行未命中信号;以及
一个多路复用器,该多路复用器具有耦合到该行高速缓存和耦合到该内存设备接口的数据输入端、耦合到该链路接口的数据输出端、以及耦合用以从该行高速缓存接收该行高速缓存命中和行高速缓存未命中信号的控制输入端,该多路复用器响应该行高速缓存未命中信号耦合来自该内存设备接口的读取数据,以及响应该行高速缓存命中信号耦合来自该行高速缓存的读取数据。
11.根据权利要求10所述的内存模块,其中所述内存设备接口还包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储从所述链路接口和从所述序列发生器接收的内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述至少一个内存设备。
12.根据权利要求10所述的内存模块,其中所述链路接口包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述内存设备接口。
13.根据权利要求12所述的内存模块,其中所述内存设备接口还包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储从所述链路接口和从所述序列发生器接收的内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述至少一个内存设备。
14.根据权利要求10所述的内存模块,其中所述链路接口包括一个光输入/输出端口。
15.根据权利要求10所述的内存模块,其中所述内存设备包括动态随机访问存储器设备。
16.一种内存集线器,包括:
一个链路接口,接收多个内存请求,至少一些该内存请求包括行地址;
一个内存设备接口,用于输出多个内存请求以及接收对至少一些该内存请求进行响应的读取数据,由该内存设备接口输出的至少一些内存请求是对从该链路接口传送到该内存设备接口的多个内存请求的响应;
一个耦合到该内存设备接口的行高速缓存,用于接收和存储响应从该内存设备接口输出的至少一个内存请求而从该内存设备接口接收的读取数据;以及
一个序列发生器,耦合到该链路接口、该内存设备接口以及该行高速缓存,该序列发生器用于生成内存请求,并且把该内存请求耦合到该内存设备接口,以读取与响应从该链路接口传送到该内存设备接口的内存请求的、由该内存设备接口接收的读取数据相关联的数据,将响应来自该序列发生器的内存请求所读取接收的读取数据存储在该行高速缓存中。
17.根据权利要求16所述的内存集线器,其中所述内存设备接口还包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储从所述链路接口和从所述序列发生器接收的内存请求,并且把该存储的内存请求按接收它们的顺序进行输出。
18.根据权利要求16所述的内存集线器,其中所述链路接口包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述内存设备接口。
19.根据权利要求18所述的内存集线器,其中所述内存设备接口还包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储从所述链路接口和从所述序列发生器接收的内存请求,并且把该存储的内存请求按接收它们的顺序进行输出。
20.根据权利要求16所述的内存集线器,其中所述链路接口包括一个光输入/输出端口。
21.根据权利要求16所述的内存集线器,其中所述序列发生器用于输出包括在从所述链路接口接收的每一读取内存请求中的地址,以及其中所述行高速缓存用于从所述序列发生器接收地址,以判断由内存请求所调用的数据是否存储在所述行高速缓存中,如果由内存请求所调用的数据存储在所述行高速缓存中,则所述行高速缓存输出该读取数据,并生成命中信号,如果由内存请求所调用的数据未存储在所述行高速缓存中,则生成行未命中信号。
22.根据权利要求21所述的内存集线器,还包括多路复用器,该多路复用器具有耦合到所述行高速缓存和耦合到所述内存设备接口的数据输入端、耦合到所述链路接口的数据输出端、以及耦合用以从所述行高速缓存接收所述行高速缓存命中和行高速缓存未命中信号的控制输入端,该多路复用器响应所述行高速缓存未命中信号,耦合来自所述内存设备接口的读取数据,以及响应所述行高速缓存命中信号,耦合来自所述行高速缓存的读取数据。
23.根据权利要求16所述的内存集线器,其中所述序列发生器用于仅当内存请求未从所述链路接口传送到所述内存设备接口时,生成内存请求并把该内存请求耦合到所述内存设备接口以读取数据。
24.一种计算机系统,包括:
一个中央处理器(“CPU”);
一个系统控制器,耦合到该CPU,该系统控制器具有一个输入端口和一个输出端口;
一个输入设备,通过该系统控制器耦合到该CPU;
一个输出设备,通过该系统控制器耦合到该CPU;
一个存储设备,通过该系统控制器耦合到该CPU;
多个内存模块,每一个内存模块包括:
多个内存设备;以及
一个内存集线器,包括:
一个链路接口,具有一个输入端口和一个输出端口,该链路接口通过该输入端口接收用于对至少一个该内存设备中的一行存储单元进行访问的多个内存请求,并且通过该输出端口输出响应该多个内存请求的数据;
一个耦合到该多个内存设备的内存设备接口,该内存设备接口用于把多个内存请求耦合到该多个内存设备,以对至少一个该内存设备中的一行存储单元进行访问,并且接收对至少一些该内存请求进行响应的读取数据,耦合到该多个内存设备的至少一些内存请求是对从该链路接口传送到该内存设备接口的多个内存请求的响应;
一个耦合到该内存设备接口的行高速缓存,用于接收和存储来自一行存储单元的读取数据,该一行存储单元响应从该内存设备接口耦合到所述至少一个内存设备的至少一个内存请求被访问;以及
一个序列发生器,耦合到该链路接口、该内存设备接口以及该行高速缓存,该序列发生器用于生成内存请求,并且把该内存请求耦合到该内存设备接口,以从所访问的行存储单元中的多个存储单元读取数据,将从所访问的行存储单元中的多个存储单元所读取的读取数据存储在该行高速缓存中;以及
一个通信链路,把该系统控制器的输出端口耦合到每一个内存模块中的内存集线器的输入端口,并且把该系统控制器的输入端口耦合到每一个内存模块中的内存集线器的输出端口。
25.根据权利要求24所述的计算机系统,其中所述内存设备接口还包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储从所述链路接口和从所述序列发生器接收的内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述至少一个内存设备。
26.根据权利要求24所述的计算机系统,其中所述链路接口包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述内存设备接口。
27.根据权利要求26所述的计算机系统,其中所述内存设备接口还包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储从所述链路接口和从所述序列发生器接收的内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述至少一个内存设备。
28.根据权利要求24所述的计算机系统,其中所述内存设备包括动态随机访问存储器设备。
29.根据权利要求24所述的计算机系统,其中所述序列发生器用于输出包括在从所述链路接口接收的每一读取内存请求中的地址,而且其中所述行高速缓存用于从所述序列发生器接收该地址,以判断内存请求所调用的数据是否存储在所述行高速缓存中,如果内存请求所调用的数据存储在所述行高速缓存中,则所述行高速缓存输出该读取数据,并生成命中信号,如果内存请求所调用的数据未存储在所述行高速缓存中,则生成行未命中信号。
30.根据权利要求29所述的计算机系统,还包括一个多路复用器,该多路复用器具有耦合到所述行高速缓存和耦合到所述内存设备接口的数据输入端、耦合到所述链路接口的数据输出端、以及耦合用以从所述行高速缓存接收所述行高速缓存命中和行高速缓存未命中信号的控制输入端,该多路复用器响应所述行高速缓存未命中信号,耦合来自所述内存设备接口的读取数据,以及响应所述行高速缓存命中信号,耦合来自所述行高速缓存的读取数据。
31.根据权利要求24所述的计算机系统,其中所述序列发生器用于仅当未把内存请求从所述链路接口传送到所述内存设备接口时,生成内存请求并把该内存请求耦合到所述内存设备接口,以从所访问的行存储单元中的存储单元读取数据。
32.根据权利要求24所述的计算机系统,其中所述系统控制器的输入和输出端口包括一个耦合到所述通信链路的组合的输入/输出端口,而且其中每一内存集线器的输入和输出端口也包括一个耦合到所述通信链路的组合的输入/输出端口。
33.根据权利要求32所述的计算机系统,其中所述通信链路包括一个光通信链路,其中所述系统控制器的输入和输出端口包括一个耦合到该光通信链路的输入/输出端口,而且其中每一内存集线器的输入和输出端口也包括一个各自的耦合到该光通信链路的光输入/输出端口。
34.一种计算机系统,包括:
一个中央处理器(“CPU”);
一个系统控制器,耦合到该CPU,该系统控制器具有一个输入端口和一个输出端口;
一个输入设备,通过该系统控制器耦合到该CPU;
一个输出设备,通过该系统控制器耦合到该CPU;
一个存储设备,通过该系统控制器耦合到该CPU;
多个内存模块,每一个内存模块包括:
多个内存设备;以及
一个内存集线器,包括:
一个链路接口,接收用于对至少一个该内存设备中的一行存储单元进行访问的多个内存请求;
一个耦合到该多个内存设备的内存设备接口,该内存设备接口用于把多个内存请求耦合到该多个内存设备,以对至少一个该内存设备中的一行存储单元进行访问,并且接收对至少一些该内存请求进行响应的读取数据,耦合到该多个内存设备的至少一些内存请求是对从该链路接口传送到该内存设备接口的多个内存请求的响应;
一个序列发生器,耦合到该链路接口、该内存设备接口以及行高速缓存,该序列发生器用于输出包括在从该链路接口接收的每一读取内存请求中的地址;
一个耦合到该内存设备接口的行高速缓存,用于接收和存储来自一行存储单元的读取数据,该一行存储单元响应从该内存设备接口耦合到该至少一个内存设备的一个内存请求被访问,该行高速缓存还可用于从该序列发生器接收地址,以判断内存请求所调用的数据是否存储在该行高速缓存中,如果内存请求所调用的数据存储在该行高速缓存中,则该行高速缓存输出该读取数据,并生成命中信号,如果内存请求所调用的数据未存储在该行高速缓存中,则生成行未命中信号;以及
一个多路复用器,该多路复用器具有耦合到该行高速缓存和耦合到该内存设备接口的数据输入端、耦合到该链路接口的数据输出端、以及耦合用以从该行高速缓存接收该行高速缓存命中和行高速缓存未命中信号的控制输入端,该多路复用器响应该行高速缓存未命中信号耦合来自该内存设备接口的读取数据,以及响应该行高速缓存命中信号耦合来自该行高速缓存的读取数据。
一个通信链路,把该系统控制器的输出端口耦合到每一个内存模块中的内存集线器的输入端口,并且把该系统控制器的输入端口耦合到每一个内存模块中的内存集线器的输出端口。
35.根据权利要求34所述的计算机系统,其中所述内存设备接口还包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储从所述链路接口和从所述序列发生器接收的内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述至少一个内存设备。
36.根据权利要求34所述的计算机系统,其中所述链路接口包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述内存设备接口。
37.根据权利要求36所述的计算机系统,其中所述内存设备接口还包括一个先进先出缓冲器,该先进先出缓冲器用于接收和存储从所述链路接口和从所述序列发生器接收的内存请求,并且把该存储的内存请求按接收它们的顺序传送到所述至少一个内存设备。
38.根据权利要求34所述的计算机系统,其中所述链路接口包括一个光输入/输出端口。
39.根据权利要求34所述的计算机系统,其中所述内存设备包括动态随机访问存储器设备。
40.根据权利要求34所述的计算机系统,其中所述系统控制器的输入和输出端口包括一个耦合到所述通信链路的组合的输入/输出端口,而且其中每一内存集线器的输入和输出端口也包括一个耦合到所述通信链路的组合的输入/输出端口。
41.根据权利要求40所述的计算机系统,其中所述通信链路包括一个光通信链路,其中所述系统控制器的输入和输出端口包括一个耦合到该光通信链路的输入/输出端口,而且其中每一内存集线器的输入和输出端口也包括一个各自的耦合到该光通信链路的光输入/输出端口。
42.一种使用耦合到多个内存模块的控制器读取在该多个内存模块的每一个中的数据的方法,该方法包括:
由该多个内存模块中第一内存模块从该控制器接收多个内存请求,至少一个该内存请求是访问多个内存设备中的至少一个内存设备的一行存储单元中的存储单元的请求,该多个内存设备包括在该第一个内存模块中;
把该接收的多个内存请求耦合到该第一个内存模块中的该至少一个内存设备;
响应对该至少一个内存设备的一行存储单元中的存储单元进行访问的请求,生成从所访问的行存储单元中的存储单元读取数据的请求,当来自该控制器的内存请求未耦合到该至少一个内存设备时,生成该请求;
把该生成的内存请求耦合到该至少一个内存设备;以及
在该第一内存模块中的高速缓存中存储响应该接收的若干内存请求和该生成的内存请求的读取数据。
43.根据权利要求42所述的方法,还包括响应来自所述控制器的从所述第一内存模块读取数据的内存请求:
判断所述读取数据是否存储在所述高速缓存中;
如果所述读取数据存储在所述高速缓存中,则把所述请求的读取数据从所述高速缓存传递到所述控制器中;
如果所述读取数据未存储在所述高速缓存中,则把所述请求的读取数据从所述至少一个内存设备传送到所述控制器。
44.根据权利要求42所述的方法,其中,由所述第一内存模块从所述控制器接收内存请求的动作,包括接收与所接收的请求相对应的光信号。
45.根据权利要求42所述的方法,其中包括在所述第一内存模块中的多个内存设备包括多个动态随机访问存储器设备。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102187669A (zh) * | 2008-08-14 | 2011-09-14 | 豪威科技有限公司 | 多媒体处理中设计可扩展的群集式存储集成电路的系统、方法和计算机可读媒介 |
WO2015024418A1 (zh) * | 2013-08-20 | 2015-02-26 | 华为技术有限公司 | 一种数据拷贝方法、设备和系统 |
CN109240596A (zh) * | 2017-07-10 | 2019-01-18 | 爱思开海力士有限公司 | 存储系统及其操作方法 |
CN109240596B (zh) * | 2017-07-10 | 2021-09-14 | 爱思开海力士有限公司 | 存储系统及其操作方法 |
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AU2003258015A1 (en) | 2004-02-23 |
CN100334564C (zh) | 2007-08-29 |
US20050223161A1 (en) | 2005-10-06 |
EP1546885A2 (en) | 2005-06-29 |
WO2004013897A3 (en) | 2004-05-06 |
JP2005535038A (ja) | 2005-11-17 |
TWI325110B (en) | 2010-05-21 |
US8954687B2 (en) | 2015-02-10 |
KR20050084797A (ko) | 2005-08-29 |
EP1546885A4 (en) | 2008-03-19 |
TW200421087A (en) | 2004-10-16 |
JP4517237B2 (ja) | 2010-08-04 |
KR100950871B1 (ko) | 2010-04-06 |
US7117316B2 (en) | 2006-10-03 |
US20040024978A1 (en) | 2004-02-05 |
EP1546885B1 (en) | 2017-05-17 |
WO2004013897A2 (en) | 2004-02-12 |
AU2003258015A8 (en) | 2004-02-23 |
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