CN1770133A - Universal serial transmission system - Google Patents

Universal serial transmission system Download PDF

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Publication number
CN1770133A
CN1770133A CN 200410092201 CN200410092201A CN1770133A CN 1770133 A CN1770133 A CN 1770133A CN 200410092201 CN200410092201 CN 200410092201 CN 200410092201 A CN200410092201 A CN 200410092201A CN 1770133 A CN1770133 A CN 1770133A
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data
signal
status signal
control signal
serial
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CN100395740C (en
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洪浩峰
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BenQ Corp
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BenQ Corp
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Abstract

Disclosed is a serial transmission control system which comprises: a sequence register for storing basic cycle width, preset multiple and preset trigger frequency; a data register for storing data; a sequence status machine for outputting preset signal on receiving start signal repeatedly until receiving a termination signal and stopping outputting status signal when completing status signal with preset trigger frequency; a converting circuit for reading from the data register according to the status signal generated by the sequence status machine.

Description

Universal serial transmission system
Technical field
The invention provides a kind of serial transmission system, refer in particular to a kind of serial transmission system that can be used for being operated in different sequential (timing).
Background technology
Electronic product now is as mobile phone, personal digital aid (PDA) (PDA) or personal computer, for having made up many microprocessor systems, to organize out various data processing function.In microprocessor system, the normal mode of order (sequential) control that will trigger with clock is coordinated in the microprocessor system each different structure square in the different specific functions of time performance, to finish the specific function of whole microprocessor system.For instance, in the time of will finishing certain function as if a microprocessor system, elder generation, reach B circuit again, continue to finish follow-up data processing by B circuit by the first circuit treatmenting data in this microprocessor system.This moment, microprocessor system just can utilize the mode of sequential control, trigger the first circuit earlier and begin deal with data, and trigger in proper order the first circuit with the data transmission handled to B circuit, the person of connecing triggers B circuit again and receives data, begins further deal with data etc.By the triggering of sequential control, just can coordinate the order that each structure square successively operates in the microprocessor system, finish the function that microprocessor system should be use up.
Microprocessor system is being delivered to data before the transmission interface, mostly be to be that unit transmits in system with the hyte, but in order effectively to save transmission line, sometimes system can split into data the mode that a position connects a position and transmits, reconfigure during reception, this is that the transmission mode of unit is called the string type transmission with the position again.
Routine is arranged at each interior integrated circuit of microcomputer system, and (mostly Integrate circuit, the IC) serial transmission between are to use specific transfer protocol, such as I at the required data mode of each serial transmission signal 2C, SPI or the like, or the series form transmission structure that defines voluntarily of application integrated circuit (ASIC), that is to say, that is the deviser defines the clock signal of serial transmission voluntarily, serial data signal and serial control signal, as saving data transfer signal number between IC and the IC, and realize the purpose of exchanges data between the IC.Usually the form of serial transmission is along with the difference of range of application, definition on clock signal, serial data signal and serial control signal is different with the big footpath mutually of sequential, so that when the interface of design serial transmission signal, usually adopt following two kinds of ways: first kind promptly is at the required data mode of each serial transmission signal, design special hardware, to meet the demand of particular serial transmission time sequence control.Another kind of then be at the required data mode of each serial transmission signal, use 1 to set the demand that meets the control of particular serial transmission time sequence to several microcontrollers (micro-controller).
The act ink-jet printer is an example, and in order to realize designing the purpose of simplifying and reducing cost, the IC number in the system has been reduced to the design about 3 to 4 at present.See also Fig. 1, Fig. 1 is the functional block diagram of conventional printer 10.On function, printer 10 can be divided into the main control module 12 that (1) is responsible for finishing view data control and calculating, motor control, storer control; (2) as the memory module 14 of purposes such as view data register, program code register, ink gun status data register; (3) direct supply conversion and the motor driving module of using with motor driven as providing of power supply in the system design (DC-DCconverter and motor driver module) 16; (4) ink gun driver module (Pen drivermodule) 18 is responsible for ink-jet head driving.In ink-jet printer 10, the module that each function is different can be divided into the serial transmission signal following three kinds of signals each other and link up each other and deal with data: (1) serial transmission clock signal (Clock), be used for becoming the triggering of data-signal, just in general have and trigger and the triggering of positive negative edge along triggering, negative edge.(2) serial transmit control signal (Control) is generally the purposes of enabling (enable) desire control IC in the simple type serial transmission.(3) serially-transmitted data signal (Data), the register data for desire control IC can be the data of unidirectional (uni-directional) or two-way (bi-directional).
Though each intermodule all is to use the mode of serial transmission to transmit signal, but the IC module of different manufacturers design might not be used identical serial transmission mode, difference for comprehensive each intermodule, the main control module 12 of being responsible for integral printer 10 runnings just must be at the required data mode of each serial transmission signal, design special hardware, or at the required data mode of each serial transmission signal, use 1 to several microcontrollers (micro-controller) are set the demand that meets the control of particular serial transmission time sequence.So, once system design is when needing to need in response to model change other IC modules such as change direct supply conversion and motor driving module or ink gun driver module, original serial signal form of using need be made or have much ado with regard to no longer being suitable for and be adjusted, and causes the puzzlement in the design.
Summary of the invention
The invention provides a kind of can be according to the serial transmission control system of status signal access data, it comprises a sequential register, is used for storing a prearranged multiple of a basic cycle width, and a default triggering times; One data register is used for storing data; One sequential state machine (timing control statemachine), be used for opening the beginning during signal in receiving one, repeat to export the status signal of this prearranged multiple that meets this basic cycle width of this default triggering times, after receiving a termination signal, when finishing the status signal of this default triggering times of exporting, stop output status signal; And a change-over circuit, be used for the data of this data register of status signal access of producing according to this sequential state machine.
The present invention also provides a kind of printer, and it comprises a sequential register, is used for storing a prearranged multiple of a basic cycle width, and a default triggering times; One sequential state machine, be used for opening the beginning during signal in receiving one, repeat to export the status signal of this prearranged multiple that meets this basic cycle width of this default triggering times, after receiving a termination signal, when finishing the status signal of this default triggering times of exporting, stop output status signal; One logical circuit is used for producing one first control signal and one second control signal according to the status signal that this sequential state machine produces; One control signal selector switch is connected to this logical circuit, is used for controlling this logical circuit and exports this first control signal or this second control signal; And an ink gun, be connected to this logical circuit, be used for according to this first control signal of this logical circuit output or the time of this second control signal control heating ink.
Description of drawings
Fig. 1 is the functional block diagram of conventional printer.
Fig. 2 is the structural representation of system of the present invention.
Fig. 3 is the sequential chart of signal of the present invention.
Fig. 4 is the arrange in pairs or groups synoptic diagram of other subsystem of system of the present invention.
Fig. 5 sends the sequential chart of signal for other subsystem for the system of Fig. 4.
Fig. 6 is the functional block diagram of the system of another embodiment of the present invention.
Fig. 7 is the synoptic diagram of ink gun.
Fig. 8 is the sequential chart of first and second control signal of control ink gun.
Fig. 9 is the layout of logic gates of the combinational logic of Fig. 6.
Figure 10 is the Karnaugh map of combinational logic output.
The reference numeral explanation
10: printer 12: the main control module
14: memory module 16: motor driving module
18: ink gun driver module 20,150: system:
22: sequential register 24: data register
25: first-in first-out register array (first ln first out buffer array)
26: sequential state machine
28: change-over circuit 30: storer
31: system bus 32: the parallel serial circuit that changes
34: transformation from serial to parallel circuit 36: selected cell
40：I/O 42：DMA
44: data sorting module 70: ink gun
72: ink container 74: pipeline
76: inkjet ink chamber 78: heating element
80: bubble 82: jet orifice
100,120: subsystem 152: counter
154: logical block 156: combinational logic
Embodiment
Carry as preceding institute, the signal content of employed serial transmission and sequential may be not too consistent between each module, so system of the present invention can be used to signal contents different between the Comprehensive Control disparate modules and sequential.
See also Fig. 2 and Fig. 3, Fig. 2 is the structural representation of system 20 of the present invention, and Fig. 3 is the sequential chart of signal of the present invention.System 20 comprises a sequential register 22, a data register mode area 24 and a sequential state machine 26.System 20 operates in the clock T of a basic cycle.22 in sequential register is used for storing a prearranged multiple m of a basic cycle width, and a default triggering times n.During the data of in system 20 needs output storage 30, being stored, be sent to data sorting module (data swap module) 44 with after the data order rearrangement via a system bus 31, be resent to data register 22, or directly the data in the storer 30 deposited in to register 24 by a direct store access controller (DMA controller) 42.The data that array (FIFO bufferarray) 25 can storage be transmitted by storer 30 or the content of other relevant transmit signal data are deposited in first in first out in the data register 24, that is required clock signal (Clock) content and control signal (Control) content of serial transmission.Sequential state machine 26 opens the beginning during signal receiving one, can give a change-over circuit 28 by the continuous status signal that has periodic width m*T for n time of exporting of beginning, and change-over circuit 28 will go data in the access data register 24 according to status signal, till receiving a termination signal.For instance, supposing the system 20 will the mode with serial give another system with one group of data output in a special time.When receiving, sequential state machine 26 opens the beginning during signal, the prearranged multiple m of the basic cycle width T that can be stored according to sequential register 22 (just every m*T the time interval) sends status signal, and the control first in first out is deposited array 25 with the parallel serial conversion circuit 32 of changeing of the data transmission to that will transmit, and the parallel serial conversion circuit 32 of changeing will export data to an output port 40 every the mode that the time of m*T exports with serial, data is delivered to another system that is connected to output port 40 at last again.If the output number of times of status signal has met default triggering times n, but does not but receive termination signal as yet, this moment, status signal still can continue to export n time once more, till receiving termination signal.When sequential state machine 26 receives a termination signal, will stop output status signal, if when at this time the output number of times of status signal was still less than n time, sequential state machine 26 just stopped output status signal after still can working as the status signal of finishing output n time.In addition, synchronous in order to ensure the content and the clock signal of transmission data, so an initial position hyte can be set before transmission of data signals.
Similarly, the data of input system 20 also can be controlled with similar method.When data were desired to import into to data register 24 by an input port 40, sequential state machine 26 also can be suitably adjusted the speed that transformation from serial to parallel change-over circuit 32 converts serial data to parallel data by the multiple of the basic cycle width of output status signal.
System 20 also comprises a selected cell 36, it can be a multiplexer (multiplexer) or three-state buffer (tri-state buffer), the selection control signal decision of being transmitted with foundation sequential state machine 26 will be changeed data after serial conversion circuit 32 convert serial data to via parallel by data register 24, be stored to data register 24 after converting parallel data again by output port 40 output, or with the data input to via transformation from serial to parallel change-over circuit 34.
At different sequential demands, the sequential state machine 26 of system 20 can be by preset multiple m that adjusts the basic cycle width that sequential register 22 stored and the speed that default triggering times n comes Adjustment System 20 outputs or input data.Supposing the system 20 is considered as a main control IC module, if will control the IC module that other works in different sequential, just several corresponding microcontrollers must be set additionally.See also Fig. 4 and Fig. 5, Fig. 4 is the synoptic diagram of system of the present invention 20 other subsystems of collocation.Fig. 5 sends the sequential chart of signal for other subsystem for the system 20 of Fig. 4.Supposing the system 20 can be used to coordinate a plurality of subsystems 100,120 (only indicate 2 subsystems at this, but in fact can coordinate plural subsystem simultaneously), and subsystem 100,120 works in different sequential respectively.Because the function of subsystem 100,120 is not quite similar, so need the control signal of different content to be enabled respectively.In order to allow system 20 coordinate these the two kinds subsystems 100,120 that work in different sequential respectively simultaneously, data register 24 can be stored in a plurality of clock data content CLK1, CLK2 or control signal content CTL1, CTL2 that correspond respectively to subsystem 100,120 simultaneously, and sequential register 22 is then stored the prearranged multiple m corresponding to the basic cycle width of subsystem 100,120 respectively 1, m 2And default triggering times n 1, n 2, suppose that subsystem 100 sends an initial request at t0, this moment, sequential state machine 26 meetings were according to initiation requests, every m 1* the time interval of T is sent status signal, and change-over circuit 28 will be every m 1* conversion of the time interval of T and output originally were stored in the clock signal content CLK1 or the control signal content CTL1 of data register 24, met the clock signal or the control signal of subsystem 100 demands with output.Status signal can meet triggering times n at the number of times of output signal 1, or just stop output when receiving a termination signal.That is to say that at time point t0-t1 during this period of time, the output port 40 of system 20 can output have m 1* the clock signal content CLK1 of T periodic width or control signal content CTL1, or every m 1* T exports the data that storer 30 is deposited in the data register 24 via output port 40.Suppose that at time point t1, system 20 receives the initiation requests from subsystem 120, this moment, sequential state machine 26 meetings were according to initiation requests, every m 2* the time interval of T is sent status signal, and change-over circuit 28 will be every m 2* conversion of the time interval of T and output originally were stored in the clock signal content CLK2 or the control signal content CTL2 of data register 24, met the clock signal clk 2 or the control signal CTL2 of subsystem 120 demands with output.Status signal can meet triggering times n at the number of times of output signal 2, or just stop output when receiving a termination signal.That is to say that at time point t1-t2 during this period of time, the output port 40 of system 20 can output have m 2* the clock signal content CLK2 of T periodic width or control signal content CTL2, or every m 2* T exports the data that storer 30 is deposited in the data register 24 via output port 40.And arrived time point t2, and system 20 receives the initiation requests 102 from subsystem 100 once more, and sequential state machine 26 also can be exported m once more by above-mentioned mechanism 1* the clock signal clk 1 of T Cycle Length, control signal CTL1 or the data content that will transmit.
Generally speaking, though these two subsystems, 100,120 employed serial transmission sequential and inconsistent, but still 100,120 output ports 40 with system 20 of subsystem that operate in different sequential can be linked together.System 20 can utilize multiplex's characteristic, utilize same output port 40 to export clock signal, control signal or other serially-transmitted data of different sequential in the different operating time, so, just the pin number that system 20 is occupied can be saved, nor too many usefulness can be reduced.In addition, if the work schedule of subsystem adjust to some extent, only need be with the prearranged multiple m of the basic cycle width in the sequential register 22 1, m 2And default triggering times n 1, n 2Setting adjust meeting the sequential demand of subsystem, or change the signal content that data register 24 is stored, just can change the puzzlement of design with the saving deviser so that the subsystem collocation cooperation after system 20 and the conversion.
For instance, the system 20 with present embodiment is applied in the ink-jet printer 10 of Fig. 1.Subsystems such as the direct supply conversion of ink-jet printer 10 and motor driven ASIC or ink gun driving ASIC all utilize the transmission mode of serial signal to finish control data, the purpose that view data is transmitted.But the sequential that they use definition may be also inconsistent.So as long as system 20 is disposed among the main control ASIC, just applicable to the application of direct supply conversion and motor driven ASIC or different ink gun driving ASIC.Even when replacing other direct supply conversion and motor driven ASIC or ink gun driving ASIC, also only need be with the prearranged multiple m of the basic cycle width in the sequential register 22 1, m 2And default triggering times n 1, n 2Setting adjust meeting the sequential demand of new ASIC, or change the signal content that data register 24 is stored, just can so that the ASIC collocation after system 20 and the conversion cooperate.
See also Fig. 6, Fig. 6 is the functional block diagram of the system 150 of another embodiment of the present invention.System 150 comprises a sequential register 22, a sequential state machine 26 and a logical circuit 154.Be similar to the system 20 of Fig. 2, sequential register 22 is used for storing a prearranged multiple m of a basic cycle width, and a default triggering times n.And sequential state machine 26 opens the beginning during signal receiving one, can begin to export continuously the status signal that has periodic width m*T for n time.But this moment, status signal can be sent to a logical circuit 154.Logical circuit 154 comprises a counter 152 and a combinational logic 156.Why counter 152 can decide count value according to default triggering times n.In other words, count value can meet default triggering times n.Combinational logic 156 can decide the control signal of output according to the periodic width m*T of count value n and sequential state machine 26 outputs.
See also Fig. 7 and Fig. 8.Fig. 7 is the synoptic diagram of ink gun 70.Fig. 8 is the sequential chart of first and second control signal of control ink gun 70.Ink gun 70 includes an ink container 72, a plurality of pipeline 74 and a plurality of inkjet ink chamber 76, ink container 72 is connected with a plurality of inkjet ink chamber 76 via a plurality of pipelines 74, ink in the ink container 72 can be flow in the inkjet ink chamber 76 via pipeline 74 deposit, each inkjet ink chamber 76 is other and be provided with a heating element 78 and be used for the ink in the inkjet ink chamber 76 is heated.The energy that is provided when heating element 78 is during greater than a predetermined energy threshold, then can make ink produce bubble 80 and from jet orifice 82 ejections and print, yet what of ink ejection are also relevant with the energy size that heating element 78 is provided, the amount of ink ejection is relatively also more when energy is big, therefore ink dot is bigger, relatively also less when the amount of energy hour ink ejection, so ink dot is less.If the inconsistent meeting of sizes of ink dots of ejection makes print quality poor, so the energy that heating element 78 is provided in the ink gun 70 preferably also can remain on a fixed value except being greater than this energy threshold, make the size of ejection ink dot to be consistent, to keep preferable print quality.When ink gun 70 receives as shown in Figure 8 the first control signal Wa, will heat ink gun 70 interior heating elements 78 are positioned at inkjet ink chamber 76 with heating ink, when the temperature of the ink in the inkjet ink chamber 76 surpassed a predetermined value, ink gun 70 will be from jet orifice 82 ejection inks.And the quality of data in order to want balance to print, after the ink gun 70 that will not spray ink can be received as shown in Figure 8 the second control signal Wb, because the heat time heating time of 78 pairs of inks of heating element is shorter, so ink gun 70 can not spray ink.This be in order to ensure a certain ink gun 70 in the process of print data, even without will spraying ink, but in this ink gun 70 temperature of inks and other ink gun 70 interior ink temperatures not want gap too big.So concerning ink gun 70, first or second control signal that receive only is to control the time length of ink heating in the ink gun 70 in fact.
See also Fig. 9 and Figure 10, Fig. 9 is the layout of logic gates of the combinational logic 156 of Fig. 6.Figure 10 is the Karnaugh map of combinational logic 156.Aforementioned mentioning, sequential state machine 26 outputs have the status signal and the default triggering times n in m*T cycle to be given after the counter 152, and counter 152 can decide count value n according to default triggering times n, and begins counting every the m*T time interval.Suppose that count value n is 16, then counter 152 can be from digital value " 0000 " every the m*T time interval counter to " 1111 ", and from the Karnaugh map of the combinational logic 156 of Figure 10, notice, the first control signal Wa=N3N2N1+N3N2, and the second control signal Wb=N3N2, so, ink gun 70 needed control signals just can] produce apace, and no longer need the system 20 of image pattern 2 the same, need elder generation that the signal content of first control signal and second control signal is stored to data register 24.Also therefore significantly reduce the usage space of register 24.
Though the present invention is with printer embodiment as an illustration, but the serial transmission system that every utilization spirit of the present invention is implemented all should belong to category of the present invention.
Compared to routine techniques, but system multiplex (MUX) of the present invention controls the running of other subsystem of different sequential demands.If the work schedule of subsystem is adjusted to some extent, only need be with the prearranged multiple m of the basic cycle width in the sequential register 1, m 2And default triggering times n 1, n 2Setting adjust meeting the sequential demand of subsystem, or change the signal content that data register is stored, just can change the puzzlement of design with the saving deviser so that the collocation of the subsystem after system and the conversion is cooperated.So, once the specification change is arranged on the design requirement and need to change peripheral IC, and these peripheral IC only need the redesign pcb board and reset relevant control register to get final product when also being the interface of communication with the serial transmission on the hardware.In such event, utilize project organization of the present invention, main control AS IC need not redesign on the one hand, the benefit that the hardware that one side is implemented by this structure has high resiliency and saves the unnecessary micro controller wasting of resources.But event has advantages such as using use of elasticity time division multiplexing and saving micro controller resource concurrently when of the present invention.
The above only is preferred embodiment of the present invention, and all equivalences of carrying out according to claim of the present invention change and revise, and all should belong to covering scope of the present invention.

Claims (27)

  1. One kind can be according to the serial transmission control system of status signal access data, it comprises:
    One sequential register is used for storing a prearranged multiple of a basic cycle width, and a default triggering times;
    One data register is used for storing data;
    One sequential state machine, be used for opening the beginning during signal in receiving one, repeat to export the status signal of this prearranged multiple that meets this basic cycle width of this default triggering times, after receiving a termination signal, when finishing the status signal of this default triggering times of exporting, stop output status signal; And
    One change-over circuit is used for the data of this data register of status signal access of producing according to this sequential state machine.
  2. 2. the system as claimed in claim 1, wherein this change-over circuit comprises a parallel serial circuit that changes, and is used for the data of this data register being stored according to the status signal of this sequential state machine to export an output port in the mode of serial.
  3. 3. the system as claimed in claim 1, wherein this change-over circuit comprises a serial changes parallel circuit, is used for according to the status signal of this sequential state machine the data of one input port being stored to this data register in the mode of serial.
  4. 4. the system as claimed in claim 1, wherein this data register is a first-in first-out register array, is used for storing data in parallel mode.
  5. 5. the system as claimed in claim 1, it also comprises a multiplexer, it is used for selecting data that this data register is stored to export this output port in the mode of serial according to the control signal of this sequential state machine output, maybe the data of this input port is stored to this data register in the mode of serial.
  6. 6.: the system as claimed in claim 1, it also comprises a three-state buffer, it is used for selecting data that this data register is stored to export this output port in the mode of serial according to the control signal of this sequential state machine output, maybe the data of this input port is stored to this data register in the mode of serial.
  7. 7. the system as claimed in claim 1, it is applied to a printer.
  8. 8. the method for a serial transmission that is used for the system that controls, this system comprises a data register mode area, and it is used for storing data, and this method comprises the following step:
    (a) open the beginning during signal in receiving one, repeat to export the status signal of this prearranged multiple that meets this basic cycle width of a default triggering times, after receiving a termination signal, when finishing the status signal of this default triggering times of exporting, stop output status signal; And
    (b) according to the data of this data register of status signal access.
  9. 9. method as claimed in claim 8, it also comprises according to the control signal decision exports the data of this data register mode area or deposits data in this data register.
  10. 10. method as claimed in claim 8, wherein step (b) data of this data register being stored according to status signal export an output port in the mode of serial.
  11. 11. method as claimed in claim 8, wherein step (b) is stored to this data register with the data of an input port in the mode of serial according to status signal.
  12. 12. a printer, it comprises:
    One sequential register is used for storing a prearranged multiple of a basic cycle width, and a default triggering times;
    One sequential state machine, be used for opening the beginning during signal in receiving one, repeat to export the status signal of this prearranged multiple that meets this basic cycle width of this default triggering times, after receiving a termination signal, when finishing the status signal of this default triggering times of exporting, stop output status signal;
    One logical circuit is used for producing one first control signal and one second control signal according to the status signal that this sequential state machine produces;
    One control signal selector switch is connected to this logical circuit, is used for controlling this logical circuit and exports this first control signal or this second control signal; And
    One ink gun is connected to this logical circuit, is used for according to this first control signal of this logical circuit output or the time of this second control signal control heating ink.
  13. 13. printer as claimed in claim 12, wherein this logical circuit comprises a counter and a combinational logic, this counter was according to presetting triggering times and determining this first control signal or the sequential length of this second control signal, and this combinational logic is used for producing first control signal and this second control signal.
  14. 14. printer as claimed in claim 12, wherein this ink gun comprises an inkjet ink chamber, be used for holding ink, an and heating element, be used for when receiving this first control signal, one first schedule time of ink that adds this heating element of thermal proximity to be spraying ink corresponding ink port, and when receiving this second control signal, the ink that adds this heating element of thermal proximity less than one second schedule time of this first schedule time to avoid that ink is sprayed this ink port.
  15. 15. a method that is used for controlling a printer, this method comprises:
    (a) open the beginning during signal in receiving one, repeat to export the status signal of this prearranged multiple that meets this basic cycle width of a default triggering times, after receiving a termination signal, when finishing the status signal of this default triggering times of exporting, stop output status signal;
    (b) status signal according to output produces one first control signal and one second control signal;
    (c) select this first control signal of output or this second control signal; And
    (d) control signal according to output is the time of this first control signal or this second control signal control heating ink.
  16. 16. method as claimed in claim 15, it is in step (d), if the control signal of output is this first control signal, the heating element of then controlling this printer adds one first schedule time of ink of this heating element of thermal proximity, if the control signal of output is this second control signal, then control one second schedule time of this heating element heating ink less than this first schedule time.
  17. 17. but a multiplex (MUX) controls the system that different sequential are exported, it comprises:
    N subsystem, it operates in different sequential respectively; And
    One main system is used for producing the signal that distributes different sequential, and this main system comprises:
    One clock controller is used for storing n basic cycle width and n corresponding default triggering times, and wherein each basic cycle width is corresponding to a default triggering times;
    One data register is used for storing data;
    One sequential state machine, be used for opening the beginning during signal from wherein a subsystem in receiving, repeat to export the status signal of this prearranged multiple that meets this basic cycle width of this default triggering times, after receiving a termination signal, when finishing the status signal of this default triggering times of exporting, stop output status signal;
    One change-over circuit is used for the data of this data register of status signal access of producing according to this sequential state machine; And
    One input/output end port, the data that are used for exporting this data register be to this subsystem, or the data of this system are imported this data register.
  18. 18. system as claimed in claim 17, wherein this change-over circuit comprises a parallel serial circuit that changes, and is used for exporting via this I/O port in the mode of serial according to the data that the state of this sequential state machine is stored this data register.
  19. 19. system as claimed in claim 17, wherein this change-over circuit comprises a serial changes parallel circuit, is used for being stored to this data register via the data of this I/O port in the mode of serial according to the state of this sequential state machine.
  20. 20. system as claimed in claim 17, wherein this data register is a first-in first-out register array, is used for storing data in parallel mode.
  21. 21. system as claimed in claim 17, it also comprises a multiplexer, and it is used for selecting the data that this data register is stored are exported in the mode of serial according to this status signal, or data are stored to this data register in the mode of serial.
  22. 22. system as claimed in claim 17, it also comprises a three-state buffer, and it is used for selecting the data that this data register is stored are exported in the mode of serial according to this status signal, maybe these data is stored to this data register in the mode of serial.
  23. 23. system as claimed in claim 17, it is applied to a printer.
  24. 24. the method for a transmission that is used for the system that controls, this system comprises a data register mode area, and it is used for storing data, and this method comprises:
    (a) set n basic cycle width and n corresponding default triggering times, wherein each basic cycle width is corresponding to a default triggering times;
    (b) open the beginning during signal in receiving from wherein a subsystem, repeat to export the status signal of this prearranged multiple that meets this basic cycle width of this default triggering times, after receiving a termination signal, when finishing the status signal of this default triggering times of exporting, stop output status signal; And
    (c) data of this data register of status signal access of foundation generation.
  25. 25. method as claimed in claim 24, it also comprises step (d) and deposits this data register in according to the data of this material register mode area of control signal decision output or with data.
  26. 26. method as claimed in claim 24, wherein step (c) data of this data register being stored according to status signal export an output port in the mode of serial.
  27. 27. method as claimed in claim 24, wherein step (c) is stored to this data register with the data of an input port in the mode of serial according to status signal.
CNB2004100922015A 2004-11-03 2004-11-03 Universal serial transmission system Expired - Fee Related CN100395740C (en)

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US6032261A (en) * 1997-12-30 2000-02-29 Philips Electronics North America Corp. Bus bridge with distribution of a common cycle clock to all bridge portals to provide synchronization of local buses, and method of operation thereof
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