CN1819238B - Image sensor pixel having a transfer gate formed from Pp+ or N+ doped polysilicon - Google Patents
Image sensor pixel having a transfer gate formed from Pp+ or N+ doped polysilicon Download PDFInfo
- Publication number
- CN1819238B CN1819238B CN2005101358861A CN200510135886A CN1819238B CN 1819238 B CN1819238 B CN 1819238B CN 2005101358861 A CN2005101358861 A CN 2005101358861A CN 200510135886 A CN200510135886 A CN 200510135886A CN 1819238 B CN1819238 B CN 1819238B
- Authority
- CN
- China
- Prior art keywords
- gate circuit
- transmission gate
- pixel
- floating node
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title abstract description 11
- 229920005591 polysilicon Polymers 0.000 title abstract description 8
- 238000007667 floating Methods 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000005540 biological transmission Effects 0.000 claims description 72
- 238000000034 method Methods 0.000 claims description 28
- 229910045601 alloy Inorganic materials 0.000 claims description 15
- 239000000956 alloy Substances 0.000 claims description 15
- 238000002513 implantation Methods 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 6
- 239000007943 implant Substances 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005036 potential barrier Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
Abstract
An active pixel using a transfer gate that has a polysilicon gate doped with P+ is disclosed. The pixel includes a photosensitive element formed in a semiconductor substrate and an n-type floating node formed in the semiconductor substrate. An n-channel transfer transistor having a transfer gate is formed between the floating node and the photosensitive element. The transfer gate is doped with a p-type dopant.
Description
Technical field
The present invention relates to imageing sensor, more particularly, the present invention relates to a kind of imageing sensor, the transmission gate circuit of the used pixel of this imageing sensor is formed by P+ or N+ doped polycrystalline silicon.
Background technology
It is ubiquitous that imageing sensor has become, and they are widely used in digital camera, portable phone, secret camera, medicine equipment, automobile and other application scenario.The technology of shop drawings image-position sensor, particularly CMOS (Cmos) imageing sensor is fast-developing constantly.For example, the requirement of high-resolution and low energy consumption has promoted the further miniaturization of imageing sensor and integrated.
Each pixel of imageing sensor generally comprises a photo-sensitive cell, as photodiode, and one or more transistor that is used for reading from photo-sensitive cell signal.Along with higher integrated, transistor is made lessly usually.For example, transmission transistor is usually used in adopting in the pixel of four transistor design.Transmission transistor has a transmission gate circuit that is formed between photo-sensitive cell and the floating node.Transmission gate circuit is the critical elements in the pixel; For better integrated and improve the fill factor (fill factor) of pixel, people wish to adjust transmission gate circuit, so that it has short gate circuit length (gate length).
But short gate circuit length may cause the leakage current from the photo-sensitive cell to the floating node.A kind of method that overcomes this leakage current is that (enhancement implant) implanted in the enhancing that increases the transmission gate circuit below.To strengthen transmission gate circuit and photodiode potential barrier/trap electromotive force at the interface like this; And the increasing of potential barrier/trap electromotive force will increase the weight of picture lag, thereby reduce image sensor performance.
Summary of the invention
The purpose of this invention is to provide and a kind ofly can improve integrated characteristic and fill factor, can guarantee the image sensor pixel of its performance again.
In order to solve the above problems, the invention provides a kind of pixel, this pixel comprises:
One is located at the photo-sensitive cell in the semiconductor substrate;
One is located at the n-type floating node in the semiconductor substrate; And
One is provided with the n-channel pass transistor (n-channel transfer transistor) of transmission gate circuit between floating node and photo-sensitive cell, wherein, this transmission gate circuit is mixed by p-type alloy.
In above-mentioned pixel of the present invention, photo-sensitive cell can be photodiode, part PIN type photodiode, PIN type photodiode, photogate or photocapacitance; Transmission gate circuit can be that P+ mixes, and the dosage of doping can be at 5e
14Ion/every square centimeter is to 5e
16Between the ion/every square centimeter, the implantation energy of doping can be between 500 electronvolt to 20 kiloelectron-volt, and this doping can original place (insitu) be carried out in the transmission gate circuit forming process.
Above-mentioned pixel may further include an amplifier transistor of being controlled by floating node, can comprise further that also one returns to the reset transistor of a reference voltage with floating node.Certainly, pixel itself can be in 4T, 5T, 6T or the 7T structure any.
Similarly, pixel provided by the invention can comprise:
One is located at the photo-sensitive cell in the semiconductor substrate;
One is located at the p-type floating node in the semiconductor substrate; And
One is provided with the p-channel pass transistor of transmission gate circuit between floating node and photo-sensitive cell, this transmission gate circuit can be mixed by n-type alloy.Wherein, transmission gate circuit can be that N+ mixes, and the dosage of doping is at 5e
14Ion/every square centimeter is to 5e
16Between the ion/every square centimeter, the implantation energy of doping can be between 1 kiloelectron-volt to 200 kiloelectron-volts, and this doping can be carried out in the original place when transmission gate circuit forms.
On the other hand, the present invention also provides a kind of transistor, and this transistor comprises:
One is located at the source region in the first conduction type semiconductor substrate;
One is located at the drain region in this first conduction type semiconductor substrate; And
One is located at above the semiconductor substrate and the gate circuit between source region and drain region, and this gate circuit is mixed by second conduction type.
Again on the one hand, the invention provides a kind of method that forms pixel in semiconductor substrate, this method comprises:
In semiconductor substrate, form a photo-sensitive cell;
Form a floating node in semiconductor substrate, this floating node is first conduction type;
Form a transmission transistor, this transmission transistor is provided with transmission gate circuit between photo-sensitive cell and floating node; And
With second conduction type this transmission gate circuit is mixed.
In the method for the invention described above, may further include the step that forms an amplifier transistor of being controlled by floating node.Wherein, first conduction type can be the n-type, and second conduction type can be the p-type.In addition, the step of doping transmission gate circuit can be to carry out in the mask step in the p-of semiconductor substrate channel periphery zone formation P+ zone in same being used for.And the mask of transmission gate circuit can carry out in forming the floating node process.
In the said method, photo-sensitive cell can be photodiode, part PIN type photodiode, PIN type photodiode, photogate or photocapacitance.Mix if transmission gate circuit is P+, then the dosage of Can Zaing can be at 5e
14Ion/every square centimeter is to 5e
16Between the ion/every square centimeter.
The invention has the beneficial effects as follows: the leakage current of the pixel of method preparation of the present invention has obtained improving well, can allow the gate circuit length of transmission gate circuit is shortened, thereby can carry out more highly integrated.And transmission gate circuit of the present invention has higher threshold voltage, thereby makes the potential barrier/trap electromotive force at photodiode and transmission gate circuit interface place obtain further improvement.
Description of drawings
Fig. 1 is prior art four transistors (4T) pixel and the p-raceway groove of periphery and the cutaway view of n-channel transistor.
Fig. 2-Fig. 3 is the cutaway view that the present invention prepares the method for pixel.
Embodiment
In the following description, many specific detail are provided, so that embodiment of the present invention are carried out thorough understanding.But the those of skill in the art in affiliated field can recognize, still can implement the present invention under the one or more situation in not having these details, perhaps adopt under the situation of other method, element etc. and still can implement the present invention.In addition, in order clearly to describe various embodiments of the present invention, thereby well-known structure and operation do not illustrated or describe in detail.
In specification of the present invention, be meant when mentioning " embodiment " or " a certain embodiment " that the described special characteristic of this embodiment, structure or characteristic comprise in one embodiment of the invention at least.Thereby " in one embodiment " or " in a certain embodiment " that occur in each place of specification might not refer to and all belong to same embodiment; And specific feature, structure or characteristic may be attached in one or more specific embodiments with suitable manner.
Fig. 1 is imageing sensor of the prior art and the cutaway view that adopts four transistorized active pixels.Be the 4T active pixel in the art.But, should be appreciated that photodiode design of the present invention can be used for the pixel design of any kind, includes but not limited to 5T, 6T or other design.
As shown in Figure 1, it shows the part 101 of imageing sensor.This part 101 of imageing sensor comprises pixel 103, n-raceway groove (channel) outer peripheral areas 105 and p-channel periphery zone 107.N-channel periphery zone 105 and p-channel periphery zone 107 comprise those elements of pel array periphery in the imageing sensor.Certainly, the transistor shown in the zone 105 and 107 only is an example, and these zones can comprise a lot of transistors (PMOS and NMOS) usually.
Pixel 103 only is an example pixel in the pel array.This pixel comprises photo-sensitive cell 109, is PIN type photodiode in the present embodiment.Yet photo-sensitive cell also can be photogate (photogate), photocapacitance (photocapacitor), part PIN type photodiode or non-PIN type photodiode.
Photodiode 109 outputs are used to adjust the signal of amplifier transistor 115.Amplifier transistor 115 is also referred to as source electrode with even transistor.Transmission transistor with transmission gate circuit 111 transfers to the gate circuit place of floating node 117 (N+ mixes) and amplifier transistor 115 in order to the signal with photodiode 109 outputs.
During use, in integration period (be also referred to as exposure cycle or gather the cycle), photodiode 109 produces electric charge (induction incident ray), and these charge storage are at the N of photodiode 109
-In the layer.Behind the integration period, transmission gate circuit 111 is opened, and will be stored in N
-Charge transfer in the layer is to floating node 117.After signal had been transferred to floating node 117, transmission gate circuit 111 was closed once more, and waited for the beginning of integration period next time.Signal on the floating node 117 is used to adjust amplifier transistor 115 subsequently.Read after the signal, the reset transistor that is provided with reset gate circuit 113 resets to a reference voltage with floating node 117.In a kind of specific embodiments, this reference voltage is Vdd.
Yet, as previously described, reduce the size of transmission gate circuit 111 for the needs of integrated and fill factor, will strengthen from photodiode 109 to floating node the generation of 117 leakage current.The present invention can reduce the transmission gate circuit leakage current, and can not reduce the performance and the minimum degree ground increase processing/manufacturing complexity of imageing sensor.
For this reason, adopt mask and implantation treatment process to form the N+ zone that reaches as the connection of reset reference voltage Vdd as floating node 117.Same mask and implantation treatment process (generally adopting arsenic and/or phosphorus) also are used for forming in n-channel periphery zone 105 the N+ zone of nmos pass transistors.N+ implants technology also can be implanted into the N+ alloy to the polysilicon gate circuit and the reset gate circuit of the nmos pass transistor in n-channel periphery zone 105.It should be noted that high-end cmos image sensor generally comprises top layer p-raceway groove handling process, in this handling process, polysilicon gate circuit material is implanted.Usually, n-raceway groove gate circuit carries out the N+ alloy to be implanted, and p-raceway groove gate circuit carries out the implantation of P+ alloy.(threshold voltage is with V to obtain having low threshold voltage to select such implantation
tExpression) n-raceway groove and p-channel transistor.In addition, also comprise a buried regions p-raceway groove treatment process usually, in this technology, n-raceway groove and p-raceway groove polysilicon gate circuit all carry out same doping.Usually, this mixes for N+, and it can be by implanting or preferably adopt raw material original place (insitu) the deposition N+ doped polycrystalline silicon of phosphorous or arsenic.
As of the present invention shown in Figure 2, photoresist mask 201 is used for N+ to be implanted, and with protection transmission gate circuit 111, prevents that it is exposed to N+ and implants down.In the prior art, transmission gate circuit 111 also adopts the conventional N+ doping techniques that is applied to n-raceway groove nmos pass transistor to implant.
Please refer to Fig. 3, formed the second photoresist mask 301 in the present invention.Usually, the second photoresist mask 301 exposes the PMOS transistor in p-channel periphery zone 107 and transmission gate circuit 111.Therefore, as shown in Figure 3, when implanting the P+ alloy, the polysilicon of transmission gate circuit 111 has also been implanted the P+ alloy.This has formed the transmission gate circuit 111 with relative higher threshold voltage (Vt), because the work function (work function) of the transmission gate circuit 111 that P+ mixes changes.
For example, alloy can be boron or boron difluoride (BF2).In one embodiment, boron implant to adopt the energy of 500 electronvolt to 20 kiloelectron-volt, and preferred energy range then is 2 kiloelectron-volts to 10 kiloelectron-volts; The concentration range of alloy is 5e
14Ion/every square centimeter (ions/cm
2) to 5e
16Ion/every square centimeter is preferably 1e
15Ion/every square centimeter is to 1e
16Ion/every square centimeter.But, be appreciated that implantation energy and other doping content, the device characteristics that concrete implantation energy and doping content depend on concrete needs and other the design consideration that also can adopt other.
In addition, P+ mixes and can carry out in the doping treatment technology of original place, in this treatment process, the polysilicon layer that forms transmission gate circuit contain boron substance in the presence of form, for example at B
2H
6Or BCl
3Existence under.
What need stress is that said process does not comprise any other step, only comprises the style of adjusting the photoresist mask 301 that is used for the implantation of p-channel PMOS transistor.Therefore, realize that the present invention has only increased the complexity of a little; And, owing to allow transmission gate circuit 111 can adjust to short gate circuit length, leakage current (I
Off) improved greatly; Simultaneously, because transmission gate circuit 111 has higher threshold voltage, the enhancing in photodiode 109 and transmission transistor zone is implanted and can be reduced, thereby further improves photodiode 109 and transmission gate circuit 111 potential barrier/trap electromotive force at the interface.
Although context of the present invention describes in conjunction with the n-channel pass transistor, same notion also can be applied to the p-channel pass transistor.In this case, the transmission gate circuit of p-channel pass transistor can be implanted with N+ and mix, and for example alloy can be arsenic or phosphorus.In one embodiment, the implantation energy that arsenic or phosphorus are implanted is 1 kiloelectron-volt to 200 kiloelectron-volts, and preferred energy range then is 5 kiloelectron-volts to 50 kiloelectron-volts, and the scope of doping content is 5e
14Ion/every square centimeter is to 5e
16Ion/every square centimeter, preferred concentration range are 1e
15Ion/every square centimeter is to 1e
16Ion/every square centimeter.But, being appreciated that the implantation energy and the doping content that also can adopt other, the device characteristics that concrete implantation energy and doping content depend on concrete needs and other design are considered.
As selectable scheme, N+ mixes and can carry out in the doping treatment technology of original place, and in this treatment process, the polysilicon layer that forms transmission gate circuit is to form in the presence of n-type alloy, for example at P
2H
6, POCl
3Or arsine (or being arsine).
In addition, though the present invention discusses by the imageing sensor transmission transistor, the present invention also can be applicable to any CMOS transistor that has leakage problem.
Foregoing is interpreted as: specific embodiments of the present invention described here is just in order to describe the present invention, but can make various conversion scheme under the situation that does not depart from aim of the present invention and scope.Therefore, except that right required, the present invention was not subjected to any restriction.
Claims (22)
1. pixel, it comprises:
One is located at the photo-sensitive cell in the semiconductor substrate;
One is located at the n-type floating node in the described semiconductor substrate; And
One is provided with the n-channel pass transistor of transmission gate circuit between described floating node and described photo-sensitive cell, wherein, described transmission gate circuit is mixed by p-type alloy, and the length of this transmission gate circuit is less than the length of the back gained transmission gate circuit that mixed by n-type alloy.
2. pixel as claimed in claim 1, wherein, described photo-sensitive cell is photodiode, part PIN type photodiode, PIN type photodiode, photogate or photocapacitance.
3. pixel as claimed in claim 1, wherein, described transmission gate circuit is that P+ mixes, the dosage of described doping is at 5e
14Ion/every square centimeter is to 5e
16Between the ion/every square centimeter.
4. pixel as claimed in claim 1, it further comprises the amplifier transistor of being controlled by described floating node.
5. pixel as claimed in claim 1, it further comprises the reset transistor that described floating node is returned to a reference voltage.
6. pixel as claimed in claim 1, wherein, described pixel is a kind of in 4T, 5T, 6T or the 7T structure.
7. pixel as claimed in claim 1, wherein, described transmission gate circuit is that P+ mixes, the implantation energy of described doping is between 500 electronvolt to 20 kiloelectron-volt.
8. pixel as claimed in claim 1, wherein, described transmission gate circuit is that P+ mixes, carry out in described doping original place in the transmission gate circuit forming process.
9. pixel, it comprises:
One is located at the photo-sensitive cell in the semiconductor substrate;
One is located at the p-type floating node in the described semiconductor substrate; And
Be provided with the p-channel pass transistor of transmission gate circuit between one described floating node and the described photo-sensitive cell, wherein, described transmission gate circuit is mixed by n-type alloy, and the length of this transmission gate circuit is less than by the length of p-type alloy doping gained transmission gate circuit.
10. pixel as claimed in claim 9, wherein, described photo-sensitive cell is photodiode, part PIN type photodiode, PIN type photodiode, photogate or photocapacitance.
11. pixel as claimed in claim 9, wherein, described transmission gate circuit is that N+ mixes, and the dosage of described doping is at 5e
14Ion/every square centimeter is to 5e
16Between the ion/every square centimeter.
12. pixel as claimed in claim 9, it further comprises the amplifier transistor of being controlled by described floating node.
13. pixel as claimed in claim 9, wherein, described transmission gate circuit is that N+ mixes, and the implantation energy of described doping is between 1 kiloelectron-volt to 200 kiloelectron-volts.
14. pixel as claimed in claim 9, wherein, described transmission gate circuit is that N+ mixes, and carry out in described doping original place in the transmission gate circuit forming process.
15. pixel as claimed in claim 9, it further comprises the reset transistor that described floating node is returned to a reference voltage.
16. pixel as claimed in claim 10, wherein, described pixel is a kind of in 4T, 5T, 6T or the 7T structure.
17. a method that forms pixel in semiconductor substrate, it comprises:
In described semiconductor substrate, form a photo-sensitive cell;
Form a floating node in described semiconductor substrate, described floating node is first conduction type;
Form a transmission transistor, this transmission transistor is provided with transmission gate circuit between described photo-sensitive cell and described floating node; And
With second conduction type described transmission gate circuit is mixed, wherein, the length of this transmission gate circuit is less than the length of the gained transmission gate circuit that mixes with first conduction type;
Wherein, the step of the described transmission gate circuit of described doping is carried out in same mask step, and this mask step also is used for forming the P+ zone in the p-of described semiconductor substrate channel periphery zone.
18. method as claimed in claim 17, wherein, described photo-sensitive cell is photodiode, part PIN type photodiode, PIN type photodiode, photogate or photocapacitance.
19. method as claimed in claim 17, wherein, described transmission gate circuit is that P+ mixes, and the dosage of described doping is at 5e
14Ion/every square centimeter is to 5e
16Between the ion/every square centimeter.
20. method as claimed in claim 17, it further comprises the amplifier transistor that formation is controlled by described floating node.
21. method as claimed in claim 17, wherein, described first conduction type is the n-type, and described second conduction type is the p-type.
22. method as claimed in claim 17, wherein, described transmission gate circuit is by mask in forming the process of described floating node.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/021,134 US7675094B2 (en) | 2004-12-22 | 2004-12-22 | Image sensor pixel having a transfer gate formed from P+ or N+ doped polysilicon |
| US11/021,134 | 2004-12-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1819238A CN1819238A (en) | 2006-08-16 |
| CN1819238B true CN1819238B (en) | 2011-02-02 |
Family
ID=36128438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2005101358861A Active CN1819238B (en) | 2004-12-22 | 2005-12-22 | Image sensor pixel having a transfer gate formed from Pp+ or N+ doped polysilicon |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7675094B2 (en) |
| EP (1) | EP1675182B1 (en) |
| CN (1) | CN1819238B (en) |
| TW (1) | TWI299210B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090261393A1 (en) * | 2008-04-18 | 2009-10-22 | United Microelectronics Corp. | Composite transfer gate and fabrication thereof |
| US9000500B2 (en) | 2009-12-30 | 2015-04-07 | Omnivision Technologies, Inc. | Image sensor with doped transfer gate |
| CN113206119B (en) * | 2021-04-29 | 2023-04-18 | 武汉新芯集成电路制造有限公司 | Active pixel circuit, image sensor, and electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310366B1 (en) * | 1999-06-16 | 2001-10-30 | Micron Technology, Inc. | Retrograde well structure for a CMOS imager |
| CN1839476A (en) * | 2003-06-25 | 2006-09-27 | 微米技术有限公司 | Tailoring gate work-function in image sensors |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4027380A (en) * | 1974-06-03 | 1977-06-07 | Fairchild Camera And Instrument Corporation | Complementary insulated gate field effect transistor structure and process for fabricating the structure |
| JPH0528053Y2 (en) | 1987-08-11 | 1993-07-19 | ||
| US5396096A (en) | 1992-10-07 | 1995-03-07 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US6027978A (en) | 1997-01-28 | 2000-02-22 | Advanced Micro Devices, Inc. | Method of making an IGFET with a non-uniform lateral doping profile in the channel region |
| US6218691B1 (en) * | 1998-06-30 | 2001-04-17 | Hyundai Electronics Industries Co., Ltd. | Image sensor with improved dynamic range by applying negative voltage to unit pixel |
| US6165902A (en) * | 1998-11-06 | 2000-12-26 | Advanced Micro Devices, Inc. | Low resistance metal contact technology |
| US6166846A (en) * | 1998-12-30 | 2000-12-26 | Intel Corporaqtion | Through silicon modulator and method |
| US6657665B1 (en) | 1998-12-31 | 2003-12-02 | Eastman Kodak Company | Active Pixel Sensor with wired floating diffusions and shared amplifier |
| US6501131B1 (en) | 1999-07-22 | 2002-12-31 | International Business Machines Corporation | Transistors having independently adjustable parameters |
| JP2001196572A (en) * | 2000-01-13 | 2001-07-19 | Canon Inc | Photoelectric conversion device |
| JP3782297B2 (en) * | 2000-03-28 | 2006-06-07 | 株式会社東芝 | Solid-state imaging device and manufacturing method thereof |
| US6750106B2 (en) | 2001-11-16 | 2004-06-15 | Altera Corporation | Polysilicon gate doping level variation for reduced leakage current |
| KR100749888B1 (en) | 2002-11-12 | 2007-08-21 | 마이크론 테크놀로지, 인크 | Isolation techniques for reducing dark current in cmos image sensors |
| KR100955735B1 (en) * | 2003-04-30 | 2010-04-30 | 크로스텍 캐피탈, 엘엘씨 | Unit pixel for cmos image sensor |
-
2004
- 2004-12-22 US US11/021,134 patent/US7675094B2/en active Active
-
2005
- 2005-11-08 TW TW094139191A patent/TWI299210B/en active
- 2005-11-17 EP EP05257094A patent/EP1675182B1/en active Active
- 2005-12-22 CN CN2005101358861A patent/CN1819238B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310366B1 (en) * | 1999-06-16 | 2001-10-30 | Micron Technology, Inc. | Retrograde well structure for a CMOS imager |
| CN1839476A (en) * | 2003-06-25 | 2006-09-27 | 微米技术有限公司 | Tailoring gate work-function in image sensors |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1675182B1 (en) | 2013-02-27 |
| EP1675182A2 (en) | 2006-06-28 |
| US20060131592A1 (en) | 2006-06-22 |
| EP1675182A3 (en) | 2009-02-11 |
| TW200625614A (en) | 2006-07-16 |
| CN1819238A (en) | 2006-08-16 |
| TWI299210B (en) | 2008-07-21 |
| US7675094B2 (en) | 2010-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7829921B2 (en) | Optimized transistor for imager device | |
| CN101694848B (en) | Image sensor and pixel having an optimized floating diffusion | |
| US5904493A (en) | Active pixel sensor integrated with a pinned photodiode | |
| US7541210B2 (en) | Method for fabricating CMOS image sensor | |
| CN100546039C (en) | Has image sensor pixel of the horizontal doping gradient that indium mix to form and preparation method thereof | |
| US7595210B2 (en) | Method of manufacturing complementary metal oxide semiconductor image sensor | |
| KR20080057356A (en) | Imaging with gate controlled charge storage | |
| EP1667232B1 (en) | Image sensor pixel having a photodiode with an indium-boron pinning layer and method of its manufacturing | |
| CN1941423B (en) | Pixel sensor with raised silicon photodiode | |
| US6218210B1 (en) | Method for fabricating image sensor with extended pinned photodiode | |
| CN1819238B (en) | Image sensor pixel having a transfer gate formed from Pp+ or N+ doped polysilicon | |
| US11901383B2 (en) | Transistor having increased effective channel width | |
| JP2001308311A (en) | Photoelectric conversion element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: American California Patentee after: OmniVision Technologies, Inc. Address before: American California Patentee before: Haowei Tech Co., Ltd. |
|
| CP01 | Change in the name or title of a patent holder |