CN1822233A - 一种擦除一个或多个非易失存储器单元的方法、电路和系统 - Google Patents

一种擦除一个或多个非易失存储器单元的方法、电路和系统 Download PDF

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CN1822233A
CN1822233A CNA2006100054168A CN200610005416A CN1822233A CN 1822233 A CN1822233 A CN 1822233A CN A2006100054168 A CNA2006100054168 A CN A2006100054168A CN 200610005416 A CN200610005416 A CN 200610005416A CN 1822233 A CN1822233 A CN 1822233A
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erase
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阿萨夫·沙比尔
夏伊·艾森
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Spansion Israel Ltd
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    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/18—Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

本发明是一种擦除非易失存储器(“NVM”)阵列或阵列段上的NVM单元的方法、电路或系统。按照本发明的一个例子，一个或多个擦除脉冲参数可与NVM阵列内的每个阵列段相关联。无论何处，个别的擦除脉冲参数可与NVM阵列内一个以至所有阵列段相关联。按本发明的某些例子，施加到阵列段内一个或多个NVM单元上的擦除脉冲的特性(如脉冲振幅、脉冲持续时间等)可至少部分基于一个或多个与给定阵列段相关联的擦除脉冲参数。

Description

一种擦除一个或多个非易失存储器单元的方法、电路和系统
技术领域
本发明涉及非易失存储器(NVM)单元，尤其涉及一种使用一个或多个存储的擦除参数来擦除一个或多个非易失存储器单元的方法、电路和系统。
背景技术
非易失存储器(NVM)单元装配于多种结构内，包括但不限于多晶硅浮栅—如图2A所示，氮化物只读存储器(NROM)—如图2B所示。如图2A所示，浮栅设备一般包括一层引导电荷诱捕层(比如由多晶硅构成)，因而只可提供一个电荷存储区。而另一方面，如图2B所示，NROM设备可能包括非传导性的电荷存储层(比如由硅氧化物构成)，因而可支持多电荷存储区。NVM的每个电荷存储区均可被视为独立的NVM单元或单位。
为生产大容量数据存储设备(比如闪存卡/棒、多媒体卡等)，NVM单元经常用做于阵列相关的单元的大矩阵的一部分，依据己知数种中的一种阵列结构和使用的操作方法，阵列中的每个单元可单独或作为组或批的部分来被设定地址、编程、读及/或擦除。多数单元阵列结构，包括业界熟知的假接地阵列，具有重复形成行列的段的多样性特征。依照某些典型的阵列结构，比如假接地阵列，每个阵列段可包括一个单元区域，该单元区域由四条分段的单元比特线、偶选区域和奇选区域构成。该偶选区域位于该单元区域的一端并包括一条分段的偶接触器比特线和两个选型晶体管用于连接该偶接触器比特线和该段的偶单元比特线。该奇选区域位于该单元区域的相对一端并包括一条分段的奇接触器比特线和两个选型晶体管用于连接该奇接触器比特线和该段的奇单元比特线。一个NVM阵列可能还另外分别包括一偶接触器连接两个相邻偶选区的偶接触器比特线，一个奇接触器连接两个相邻奇选区的奇接触器比特线。
众所周知，一个NVM单元的逻辑状态可决定和受限于其阈电压(“Vt”)，即栅极到源/漏极电压，在此电压时，单元开始明显导通电流。每个单元，或多电荷存储区域NVM设备的电荷存储区域，均可具有不同的阈电压，因而可存储其独特的逻辑值。每个单元或每个电荷存储区可从其各自的设备中的独立终端或一套终端进行操作(如被编程、擦除或读取)操作多电荷存储区NVM设备的方法为业内所熟知。前面所述或正在进行的讨论有关NVM单元操作的内容，同时可应用于单电荷存储区设备的单电荷存储区操作和多电荷存储区设备的每个电荷存储区操作。
对每个NVM单元，不同阈电压值具有不同的逻辑状态，且NVM单元阈电压水平可为存于单元电荷存储区电荷量(如电子和空穴)的函数。图1A为电压分布图，描述了二进位非易失性存储器单元可能的阈电压分布，其中竖轴方向为边界单元阈电压Vt值及每个单元可能的逻辑状态。例如，Vt值低于EV水平的单元被视为已校验擦除，Vt值低于PV水平的单元被视为已校验编程。这两个限制定义了完成编程和擦除顺序的逻辑状态，这可在单元上执行。一个编程脉冲的程序顺序可用来促使单元的Vt超过PV，而一个擦除顺序可能用于促使单元的Vt低于EV。同样在图1A中，一条竖轴线指明了在读取操作中常用的读取校验(RV)电平。另外，如果读取时单元的Vt超过RV水平，则被单元视为已被编程；如果单元的Vt低于RV，单元被视为已被编程
图1B为电压分布图，描述了多级非易失性存储器单元(MLC)电荷存储区可能的阈电压分布，其中一组竖轴描述了与每个单元可能的编程校验单元阈电压(如PV00、PV01)相关边界值，而另一组竖轴描述了与每个单元可能的程序状态(如RV00、RV01)下读取校验电平的相关边界值。
对NVM阵列的单独单元不同的编程方法(如注入电荷到电荷存储区)和/或擦除(如从电荷存储区移除电荷)是已知的。多数情形下，当一个或更多编程脉冲作用于单元时，存储于NVM单元存储区的电荷量会增加；与之相反，当一个或更多擦除脉冲作用于NVM单元栅极终端时，存储于NVM单元存储区的电荷量会减少，由此迫使释放从单元捕获区或单元捕获界面捕获的电荷。擦除过程也可选择注入反极性的电荷而不是物理移除电荷。例如，如果编程过程包括注入电子到单元电荷阱，相应的擦除过程就可包括注入空穴到电荷阱。反极性电荷会湮灭或消除彼此的效果。
另外，当讨论擦除一个或更多NROM假接地阵列中NVM单元的程序时，擦除步骤可包括在一个或更多单元栅极上施加强负压脉冲(如-7V)，在漏极上施加强正压(如+3V to +7V)，并允许单元源极浮动。在单元被擦除时，存储于各自电荷阱区邻近漏结的电荷，少许通过沟道，可被沉于正被擦除单元的漏极(或与注入空穴中和)。
NVM阵列的单元组或群可同时被编程和/或擦除。NVM阵列的单元组或群可由正被编程(或被擦除)成同样逻辑状态单元的组成，或由正被编程(或被擦除)成几种可能状态之一单元的组成，比如MLC阵列的单元中的情形。由于并非所有单元在被编程和/或被擦除时具有同一的磁化系数，单元组里的正接受编程或擦除脉冲的单元不会以同样的速度编程或擦除。在同组其他在同时接收编程或擦除脉冲的单元前，有些单元会达到目标编程状态或擦除状态。
操作NVM单元的方法(如编程、读取和擦除)使用一个或多个参考结构，如参考单元以提供参考电平(如PVs，EVs)每一或多个参考结构可与正在被操作的存储器单元比较，以决定正被操作的存储器单元的条件或状态。一般而言，为决定NVM单元是否处于一特定状态，如被擦除、编程或在多级单元(“MLC”)内的多重可编程状态下的一种编程。单元的阈电平与参考结构比较，而参考结构的阈电平是预设且公知的，并被设在一电压水平，该电压水平与待测试的特定状态相关。NVM单元与参考单元的阈电压之间的比较，常常使用读出放大器完成。为决定NVM单元的状态，而比较NVM单元与一个或多个参考单元的阈电压的各种技术都是公知的。
在将NVM单元编程至所需要的状态时，带有设置阈电压于特定状态下程序校验电平的参考单元可与被编程的单元阈电压比较，以决定电荷存储区域是否已被充分充电而可被视为被编程至需要状态。如在编程脉冲作用于单元后，由于单元阈电压是或高于“编程校验”电平(即相关参考单元的阈电压)，单元被确认未被充分充电，即未达目标编程状态，单元会被另一编程脉冲作用以在其电荷存储区充入更多电荷。一旦单元阈值达到或超过“编程校验”电平即已被编程，就不需要更多编程脉冲作用于单元。除将编程脉冲改为擦除脉冲，同样操作原则适用于擦除一个或多个单元时。
刚处理之后，特别是多编程/擦除周期之后，每个NVM单元的编程和擦除磁化系数与任何其他NVM单元的磁化系数都是不一样的，且其在单元的整个生命周期中不断变化。图3表示擦除脉冲电压的示例性分布，该擦除脉冲电压应能使多个阵列段中的每一个上的一组NVM单元中的每个单元达到擦除状态，该多个阵列段是图4所示的阵列一类的NVM阵列。
因此，在本领域内，需要一种NVM产品以提高擦除一个或多个NVM单元的方法、电路和系统。
发明内容
本发明是一种用于擦除非易失存储器(NVM)阵列或阵列段中的一个或多个单元的方法、电路和系统。根据本发明的某些实施例，一个或多个擦除脉冲参数可与NVM阵列中的一定数量的阵列段中的每个阵列段相关。单独的擦除脉冲参数可与NVM阵列中的从一个到全部的阵列段都相关。
根据本发明的某些实施例，对应用到阵列段中一个或多个NVM单元上的擦除脉冲而言，其至少一个特征(如脉冲幅值、脉冲持续时间等)可至少部分地基于一个或多个与给定阵列段相关的擦除脉冲参数。根据本发明另外的一些实施例，该一个或多个与给定阵列段相关的擦除脉冲参数可在NVM阵列的排序过程中被存储。根据本发明其他的一些实施例，该一个或多个与给定阵列段相关的擦除脉冲参数可在一个擦除操作已作用于阵列段中的一个或多个NVM单元后被更新。
所述一个或多个与给定阵列段相关的擦除脉冲参数可与最高擦除脉冲电压相关，该最高擦除脉冲电压用于使阵列段中的一个或多个单元达到阈电压。根据本发明的某些实施例，该一个或多个与给定阵列段相关的擦除脉冲参数实际是指一擦除脉冲电压，在该擦除脉冲电压，阵列段中的一个最慢的擦除NVM单元被促使达到与前述擦除操作或循环过程中的擦除状态相关的阈电压。根据某些其他实施例，该一个或多个擦除脉冲参数可以是一擦除脉冲电压，该擦除脉冲电压由一电压偏移而来并低于该电压，该电压可促使阵列段中的擦除最慢的NVM单元达到与一在先的擦除操作/循环期间的擦除状态相关的阈电压。又根据本发明的其他一些实施例，该一个或多个与给定阵列段相关的擦除脉冲参数可与擦除脉冲电压相关，该擦除脉冲电压可使阵列段中除擦除最慢的单元外的NVM单元达到擦除状态。根据本发明的其他一些实施例，一个或多个与给定阵列段相关的擦除脉冲参数可与擦除脉冲的持续时间相关，该擦除脉冲持续时间可使阵列段中的一个相对较慢的擦除单元达到一在先的擦除操作/循环过程中的擦除状态。对于本领域的普通技术人员而言，显而易见的是：擦除脉冲参数可以是擦除脉冲的任何特性(如振幅、持续时间、斜率、波形等)，这些擦除脉冲特征可影响擦除脉冲的使一NVM单元达到与擦除状态相关的阈电压的有效性。
根据本发明的一些实施例，该一个或多个与各个阵列段相关的擦除脉冲参数可被存储到一个或多个与该脉冲参数有关的给定阵列段中的NVM单元中，或存储到一个或多个其它功能上与给定阵列段相关的NVM单元中。该一个或多个与阵列段相关的擦除参数可在排序过程中首先存储在相关的NVM单元中。该一个或多个与给定阵列段相关的擦除参数可随后被更新，更新时间也可在阵列段中的一个或多个单元的每个擦除操作/循环之后，或者间歇地在给定阵列段的某个数量的擦除操作/循环之后。对于本领域的普通技术人员而言，显而易见的是：擦除脉冲参数可存储在任何功能上与阵列段相关的NVM单元中。
根据本发明的一些实施例，存在一个或多个NVM单元，其与NVM阵列段相关，并且可用于存储一个或多个也与NVM阵列段相关擦除脉冲参数。根据本发明的其他一些实施例，存在一个擦除脉冲源(如，电荷泵、控制器等)，可用于产生擦除脉冲，其特征是至少部分地基于一个或多个存储在与给定阵列段相关的NVM单元中的擦除脉冲参数。
根据本发明的一些实施例，存在一个控制器，可用于读一个或多个与给定阵列段相关的擦除脉冲参数，且发出擦除脉冲源信号以产生一个或多个至少部分基于所述读擦除脉冲参数的擦除脉冲。根据本发明其他的一些实施例，控制器可用于记录擦除脉冲的与脉冲特性(如，幅值、持续时间等)相关的擦除脉冲参数，该擦除脉冲使NVM单元达到一阈电压，该阈电压与擦除操作/循环过程中的擦除状态相关。该控制器可将擦除脉冲参数存储到NVM单元中，该NVM单元在功能上将阵列段与给定的擦除脉冲参数关联。
附图说明
前已特别指出，并在说明书的结尾部分也明确地提出了本发明的主题。然而仍可参考下面的详细描述并结合附图，以期更好理解本发明，及结合对象、特征和有益效果的操作结构和方法，但均不限于此：
图1A所示是一电压分布图，表示可能的阈电压在二进制非易失存储器单元的电荷存储区域中的分布，其中竖轴表示边界值或者阈电压值，其与单元的各个可能的编程状态的编程校验、读校验和中间编程校验电平相关联；
图1B所示是一电压分布图，表示可能的阈电压在一多电平的非易失存储器单元(“MLC”)的电荷存储区域中的分布，其中竖轴表示边界值或阈电压，其与单元的各个可能状态的编程校验、读校验和中间编程校验电平相关联；
图2A所示是浮栅存储单元的侧截面简图；
图2B所示是具有独特的编程电荷存储区域的氮化物只读存储器(NROM)单元的侧截面简图；
图3所示是擦除脉冲电压值的示例性分布图，该擦除脉冲电压应能使多个阵列段中的每一个上的一组NVM单元中的每个单元达到擦除状态，该多个阵列段是图4所示的阵列一类的NVM阵列；
图4是根据本发明的一些实施例的一个示例性NVM电路和阵列的方块图，其中，通过一个擦除脉冲源进行擦除脉冲初始化，控制器可从初始化之前的表到给定阵列段，来访问与给定阵列段相关的擦除脉冲参数；
图5是包括根据本发明的示例性方法的步骤的流程图，其中该示例性方法的步骤用于与现有技术中的工艺步骤相对照。
以上图形都是非限制性的，为简单和清晰起见，其中所示的元件不一定均按比例绘制，例如，为了某些元件的清晰，其尺度可比其他元件相对大一些。而且，参考数字在插图中可能适当地被重复使用以指示相关的或相似的部分。
具体实施方式
在下面的详细说明中，将提出一些具体细节以便透彻理解本发明。但可以理解的是，对本领域内的普通技术人员来说，没有这些细节，也能够实施本发明。另外，为明晰起见，本文件对一些众所周知的方法和程序将不予详细描述。
除非特别说明，下文讨论中所贯穿使用于本说明书的一些术语如“处理”、“计算”、“计划”、“决定”之类，均表示计算机或计算系统或类似的电子计算设备的动作和/或过程，该动作和/或过程对计算系统的寄存器和/或存储器上的物理(例如电子的)量进行操作和/或转换，使其变为其他数据，类似地，这些数据意指在计算系统的寄存器、存储器或其他类似的可存储、转换或显示信息的设备上的物理量。
本发明的实施例可包括用以执行文中所述操作的设备。该设备可依用途而特制，或可包括一个具有普通用途的计算机，该计算机可通过内置的计算机程序进行选择性激活或重构。
本发明是一种用于擦除非易失存储器阵列或阵列段上的一个或多个非易失存储器(“NVM”)单元的方法、电路和系统。按本发明的某些实施例，一个或多个擦除脉冲参数可与一定数量的NVM阵列内的每个阵列段相关联。单独的擦除脉冲参数可与NVM阵列内的一个至所有中任何数量的阵列段相关联。
按本发明的某些实施例，对施加到阵列段内部的一个或多个NVM单元上的擦除脉冲来说，其至少有一种特性(如，脉冲振幅、脉冲持续时间等)可至少部分基于一个或多个与给定阵列段相关联的擦除脉冲参数而设定。按照本发明的另一些实施例，该一个或多个与给定阵列段相关联的擦除脉冲参数可在该NVM阵列排序期间进行存储，而按照本发明的另外一些实施例，该一个或多个与给定阵列段相关联的擦除脉冲参数可在阵列段的一个或多个NVM单元上执行完擦除操作后予以更新。
该与给定阵列段相关联的一个或多个擦除脉冲参数可与最高擦除脉冲电压相关联，该最高擦除脉冲电压应可促使阵列段上的一个或多个单元达到擦除阈电压。按本发明的某些实施例，该一个或多个与给定阵列段相关联的擦除脉冲参数实际上可以是该擦除脉冲电压，在该电压时，该阵列段上擦除得最慢的NVM单元也可达到阈电压，该阈电压与一在先的擦除操作或循环中的擦除状态相关。按本发明的某些实施例，一个或多个擦除脉冲参数可以是一个擦除脉冲电压，该脉冲电压由偏移且低于另一电压，在该另一电压时，阵列段上擦除得最慢的NVM单元也可达到阈电压，该阈电压与一在先的擦除操作/循环中的擦除状态相关。按本发明的另一些实施例，一个或多个与给定阵列段相关联的擦除脉冲参数可与擦除脉冲电压相关，该擦除脉冲电压可使该阵列段内除擦除得最慢的单元外的NVM单元达到擦除状态。按本发明的某些实施例，一个或多个与给定的阵列段相关联的擦除脉冲参数可与一个擦除脉冲特性相关联(如，电压)，该擦除脉冲特性使在一在先的擦除操作/周期中擦除得最快的阵列段内的一个NVM单元达到擦除状态。
按本发明的某些实施例，一个或多个与给定阵列段相关联的擦除脉冲参数可与擦除脉冲的持续时间相关联，该擦除脉冲的持续时间可使该阵列段上擦除速度相对较慢的单元在一在先的擦除操作/循环中达到擦除状态。对本领域内的普通技术人员来说，很明显，一个擦除脉冲参数可以是擦除脉冲的任何特性(如，振幅、持续时间、斜率、波形等)，擦除脉冲可促使NVM单元达到与擦除状态相关的阈电压受到该特性影响。
按本发明的某些实施例，该一个或多个与每个阵列段相关联的擦除脉冲参数可存储在给定阵列段内的一个或多个NVM单元上，该给定阵列段与擦除脉冲参数相关，或者，一个或多个NVM单元在功能上以另外的方式与给定阵列段相关联。该一个或多个与阵列段相关的擦除参数可在排序期间首先存储在相关的NVM单元上。该一个或多个与给定阵列段相关联的擦除参数可稍晚，或在该一个或多个阵列内的单元完成所有擦除操作/循环后，或者间歇性地在给定阵列段的某些擦除操作/循环之后，予以更新。对本领域的普通技术人员来说，很明显擦除脉冲参数可存储在任何NVM单元上，该NVM单元在功能上与阵列段相关。
按本发明的某些实施例，存在一个或多个NVM单元，其与NVM阵列段相关，且可用以存储一个或多个也与NVM阵列段相关的脉冲参数。按本发明的另外一些实施例，存在一个脉冲源(如，电荷泵，控制器等)，可用以产生一个擦除脉冲，该擦除脉冲的特性至少可部分基于一个或多个擦除脉冲参数设定，当该脉冲源针对该给定阵列段内的单元产生一个擦除脉冲时，该脉冲参数存储在与给定阵列段相关联的NVM单元中。
按照本发明的某些实施例，可采用控制器以读取一个或多个与给定阵列段相关联的擦除脉冲参数，并向擦除脉冲源发出信号以产生一个或多个擦除脉冲，该擦除脉冲至少可部分基于该读擦除脉冲参数。按照本发明的另外一些实施例，可采用控制器以记录与擦除脉冲的脉冲特性(如，振幅、持续时间等)相关联的擦除脉冲参数，该擦除脉冲可促使NVM单元达到阈电压，该阈电压与一个擦除操作/循环中的擦除状态相关联。该控制器可将擦除脉冲参数存储在一个NVM单元内，该NVM单元在功能上与该阵列段相关联，该阵列段与给定的擦除脉冲参数相关。
参看图4，该图表示一个示例性的电路和阵列100，见于本发明某些实施例，其中，通过擦除脉冲源300可进行脉冲初始化，控制器200可从初始化之前的表100到该给定阵列段，读取一个与一给定阵列段(如，2A)相关联的擦除脉冲参数。不论在擦除操作初始化时，或在给定阵列段内的一个或多个单元循环时，不论是基于通过外部界面接受到的信号，还是基于其自身协议，该控制器200均可在阵列段擦除脉冲参数表10中查寻一个或多个与给定阵列段相关联的擦除脉冲参数。
在排列阵列10期间，与每个阵列段相关的一个或多个擦除脉冲参数可初始编入表110，并在给定阵列段进行一在先的擦除操作/循环后更新。与每个阵列段相关的存储擦除参数可以是擦除脉冲的至少一个特性(如，电压和/或持续时间)，该擦除脉冲在一在先的擦除操作/循环期间促使特定阵列段的NVM单元达到擦除状态。
控制器200使用与给定阵列段相关的擦除脉冲参数来促使擦除脉冲源300产生一个或一组擦除脉冲，擦除脉冲至少部分基于该一个或多个擦除参数。所产生的擦除脉冲通过X/Y MUX电路400作用于阵列100，这在本领域内是公知的。该擦除可作用于给定阵列中的所有或部分NVM单元
一旦控制器200通过读出放大器读取出接受擦除脉冲的特定阵列段里至少有部分单元已达到了擦除校验电平(不管是第一个单元，最后一个单元，或其中的某些单元)，控制器200就通过一个或多个新擦除脉冲参数更新与特定阵列段相关的参数表110的记录，该新擦除脉冲参数与一个擦除脉冲的某些特性相关联，该擦除脉冲使该阵列段中的一个NVM单元在现擦除擦作/周期中达到擦除校验状态。
参看图5，该图是一个流程图，包括本发明一个示例性方法的步骤，其用以与现有技术中的方法相对照。按照图5所示的示例性算法，应初始化设置(如，在排序期间)栅极(Vcvp)和漏极(Vppd)电压，该栅极和漏极电压与一个被施加在阵列段上的擦除脉冲相关联。在一个擦除脉冲被施加到该阵列段(如，单元集合)的一个或多个单元之后，就在这些单元上执行校验操作。如果没有任何子群(标以DQ)完全通过擦除校验，就向漏极电压加一个“强”增量，否则就加一个“弱”增量。该循环一直继续，直到所有单元均通过校验。为可靠起见，每个子群均可收到一个额外的擦除脉冲(其比使单元达到完全擦除的电压高一阶)。作为本发明示例性实施例的一部分，应用在该在先的擦除操作中的最高漏极电压(Vppd)可作为下一擦除操作(对同一单元集合)的初始漏极电压来存储并使用。
在一在先的擦除操作中使用的擦除电压需要存储在专门的单元中，这样后续擦除操作时可从该单元重新取出该电压。
在此虽然叙述了本发明的某些特征，但本领域的技术人员仍可对其做出修改、替代、变化和等效。可以理解的是，本发明的权利要求试图涵盖所有这类修改和变化，其应均属本发明之精神。

Claims (10)

1、一种擦除NVM阵列段上的一个或多个非易失存储器单元的方法，所述方法包括：向NVM单元施加一个擦除脉冲，该擦除脉冲的特性至少部分基于与给定阵列段相关联的可更新的擦除脉冲参数。
2、根据权利要求1所述的方法，其中，该可更新的擦除脉冲参数与一擦除脉冲电压相关联。
3、根据权利要求2所述的方法，其中，该可更新的擦除脉冲参数实际上与一个擦除脉冲电压相关联，该擦除脉冲电压电压可使该阵列段上一个NVM单元达到阈电压，该阈电压与一在先的擦除操作中的擦除状态相关。
4、根据权利要求3所述的方法，其中，该可更新的擦除脉冲参数实际上与一个擦除脉冲电压相关联，该擦除脉冲电压可使该阵列段上擦除相对慢的NVM单元达到阈电压，该阈电压与一在先的擦除操作中的擦除状态相关。
5、根据权利要求3所述的方法，其中，该可更新的擦除脉冲参数由擦除脉冲电压偏移而来且比该电压低，该擦除脉冲电压可使该阵列段上擦除相对慢的NVM单元达到阈电压，该阈电压与一在先的擦除操作中的擦除状态相关。
6、一种擦除非易失存储器单元的电路，包括，一个擦除脉冲源，其产生一个擦除脉冲，该擦除脉冲的特性基于一个可更新的擦除参数，该擦除参数与该给定阵列段相关联。
7、根据权利要求6所述的电路，其中，该可更新擦除脉冲参数与一擦除脉冲电压相关联。
8、根据权利要求7所述的电路，其中，该可更新擦除脉冲参数实际上与一擦除脉冲电压相关联，该擦除脉冲电压可使该阵列段上一个NVM单元达到一阈电压，该阈电压与一在先的擦除操作中的擦除状态相关联。
9、根据权利要求8所述的电路，其中该可更新擦除脉冲参数实际上与一擦除脉冲电压相关联，该擦除脉冲电压可使该阵列段上擦除相对慢的NVM单元达到阈电压，该阈电压与一在先的擦除操作中的擦除状态相关。
10、根据权利要求8所述的方法，其中，该可更新的擦除脉冲参数实际上与一电压相关联，该电压由擦除脉冲电压偏移而来且比擦除脉冲电压低，该擦除脉冲电压可使该阵列段上擦除相对慢的NVM单元达到阈电压，该阈电压与一在先的擦除操作中的擦除状态相关。
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