CN1832165A - 双列存储器模块的堆叠式dram存储器芯片 - Google Patents

双列存储器模块的堆叠式dram存储器芯片 Download PDF

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CN1832165A
CN1832165A CNA2005101370596A CN200510137059A CN1832165A CN 1832165 A CN1832165 A CN 1832165A CN A2005101370596 A CNA2005101370596 A CN A2005101370596A CN 200510137059 A CN200510137059 A CN 200510137059A CN 1832165 A CN1832165 A CN 1832165A
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S·拉古拉姆
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Abstract

双列存储器模块(DIMM)的DRAM存储器芯片具有：(a)预定数目(M)的堆叠式DRAM存储器管芯；(b)每个DRAM存储器管芯可通过相应的存储器队列信号(r)选择；(c)每个DRAM存储器管芯包括存储单元阵列；(d)由地址线构成的公用内部地址总线是为寻址存储单元设置的并连接到全部M个堆叠式DRAM存储器管芯；(e)由内部数据线构成的M个内部数据总线是为把数据写入堆叠式存储器管芯的存储单元和从其中读出数据而设置的；(f)设置集成再驱动装置，它包括：(f1)为驱动施加在DRAM存储器芯片的地址焊盘的外部地址信号而设置的用于所有内部地址线的缓冲区；和(f2)多路器/多路分离器，它把选定的DRAM存储器管芯的内部数据线切换到DRAM存储器芯片的数据焊盘。

Description

双列存储器模块的堆叠式DRAM存储器芯片
技术领域
本发明一般地涉及双列存储器模块(DIMM)的DRAM芯片，具体地说，涉及带寄存器的双列存储器模块(DIMM)的DRAM存储器芯片。
背景技术
设置存储器模块是为了增大计算机系统的存储能力。原来单列存储器模块(SIMM)用于个人计算机来增大存储器的大小。单列存储器模块只在它的印刷电路板(PCB)的一侧包括DRAM芯片。在所述模块的两侧用于连接单列存储器模块(SIMM)的印刷电路板的触点是冗余的。SIMM的第一变型具有30个引脚并提供8位数据(在奇偶位版本上9位)。SIMM的第二变型称为PS/2，包括72个引脚，并提供32位数据(在奇偶位版本上36位)。
由于所述存储器模块在某些处理器上数据总线的不同宽度，有时为了填充存储体要成对地安装几个SIMM模块。例如，在具有32位数据总线宽度的80386或80486系统上，存储体或者需要四个30引脚SIMM或者需要一个72引脚SIMM。对于具有64位数据总线宽度的pentium系统，需要两个72引脚SIMM。为了安装单列存储器模块(SIMM)，将所述模块放入插口中。单列存储器模块使用的RAM技术包括EDO和FPM。
当Intel公司的pentium处理器在市场上变得广为流行时，双列存储器模块(DIMM)便作为占主导地位的存储器模块类型开始代替单列存储器模块(SIMM)。
单列存储器模块(SIMM)仅在它们的印刷电路板(PCB)的一侧安装几个存储部件或DRAM芯片，而双列存储器模块(DIMMS)在模块印刷电路板的两侧都安装存储部件。
有不同类型的双列存储器模块(DIMM)。无缓冲的双列存储器模块不包含缓冲区或位于该模块的寄存器。这些无缓冲的双列存储器模块一般用于台式PC系统和工作站。在单数据速率(SDR)存储器模块中，引脚的数量一般是168，在双数据速率模块和在DDR-2模块中引脚数为184。DDR-2-DRAM是现有的DDR-DRAM的自然延伸。已经引入200MHz工作频率的DDR2，并且对于主存储器正在将其扩展至266MHz(DDR-2 533)、333MHz(DDR-2 667)，而对于特殊用途，甚至正在将其扩展至400MHz(DDR-2 800)。DDR-SDRAM(同步DRAM)通过在时钟脉冲的上升沿和下降沿都读取数据来提高速度，在不增大时钟信号的时钟频率的情况下基本上使数据的频带宽度加倍。
另一种类型的双列存储器模块(DIMM)是带寄存器的双列存储器模块。带寄存器的双列存储器模块在模块上包括几个附加的电路，具体地说，一种类似于寄存器的再驱动缓冲部件，用来再驱动命令地址信号。还设置锁相环(PLL)，用于再驱动时钟信号的定时对准。带寄存器的双列存储器模块一般用于高端服务器和高端工作站。
ECC双列存储器模块包括误差校正位或ECC位。所述类型的双列存储器模块总共具有64个数据位加上8个ECC位，主要用于服务器计算机。带寄存器的双列存储器模块或者带有ECC或者不带ECC，用于SDR、DDR和DDR 2。
另一种类型的双列存储器模块是所谓小外形DIMM(SO-DIMM)。它们是一种增强版本的标准双列存储器模块，用于膝上计算机和某些特殊服务器。
双列存储器模块在其印刷电路板上包括预定数目N的存储器芯片(DRAM)。每一个存储器的数据宽度一般为4位、8位或16位。若选定DIMM作为主存储器，则当今个人计算机主要使用无缓冲的双列存储器模块。但对于主存储容量要求较高的计算机系统，具体地说服务器，带寄存器的双列存储器模块是流行的选择。
因为在计算机系统中存储器要求与日俱增，亦即，在存储器大小和存储器速度两个方面都要求在每一个存储器模块(DIMM)上设置最大数目的存储器芯片(DRAM)。
图1表示按照先有技术的双列存储器模块。所述双列存储器模块包括N个DRAM芯片，安装在印刷电路板(PCB)的上侧。图1所示的带寄存器的双列存储器模块包括命令和地址缓冲区，后者通过主母板对施加在双列存储器模块的命令和地址信号进行缓冲而且通过命令和地址总线(CA)向安装在印刷电路板上的DRAM芯片输出这些信号。还通过命令和地址缓冲器缓冲芯片选择信号S并且所述芯片选择信号S是为选择安装在DIMM电路板上的所需的DRAM芯片而设置的。所有DRAM芯片都由时钟信号CLK提供时钟，它通过也安装在所述双列存储器模块(DIMM)上的时钟信号缓冲区进行缓冲。每一个DRAM芯片都通过具有q条数据线的单独的数据总线(DQ)连接到母板。每一个DRAM芯片的数据总线一般都包括4至16位。
图2表示如图1所示的双列存储器模块(DIMM)沿着直线A-A’截取的截面图。为了增大存储能力，DIMM具有安装在印刷电路板(PCB)两侧的DRAM芯片。在DIMM模块的顶侧有DRAM芯片、而在DIMM模块的底侧也有DRAM芯片。因此，图2所示的DRAM双列存储器模块包括两个存储器队列或存储器层次，亦即，存储器队列0和存储器队列1。
为了增大双列存储器模块(DIMM)的存储能力还已经研制了堆叠式DRAM芯片。
图3表示堆叠式DRAM芯片，具有存储器上管芯和存储器下管芯，从而在堆叠式DRAM芯片内提供两个存储器队列。两个存储器管芯封装在基片上的一个芯片内。堆叠式DRAM芯片通过焊球等焊盘连接到印刷电路板。具有图3所示的堆叠式DRAM芯片的双列存储器模块在印刷电路板的两侧具有四个存储器队列，亦即，在顶侧两个存储器队列和在底侧两个存储器队列。
在当前计算机中，具有两个存储器队列的双列存储器模块是允许的。当存储器系统内存储器队列的数量递增到四个存储器队列或甚至八个存储器队列时，如图1所示，DQ总线和CA总线上负载增大。对于CA总线，负载的增大并不激烈，因为与数据总线对比，命令和地址总线(CA)运行在半速下，而命令和地址缓冲区再驱动由母板上的处理器施加在双列存储器模块上的地址和命令信号。但是，大双列存储器模块上的存储器队列会引起由母板上的控制器驱动的DQ数据总线的负载增大。DQ总线上的数据速率非常高，特别是当运行在DDR2数据速率下时。因而，连接到每一个DQ数据总线上的负载的增大会恶化数据信号，还使得数据差错无法排除。因此，在连接到芯片的DQ总线DRAM芯片内，存储器队列的数目M有一个限度。由于限制在DRAM芯片内允许的存储器队列数量，双列存储器的存储能力也受到限制。
发明内容
因此，本发明的目的是提供一种用于双列存储器模块的堆叠式DRAM存储器芯片，对于预定的工作频率，它允许增大双列存储器模块上的存储器队列数目。
所述目的是通过本发明的堆叠式DRAM存储器芯片达到的。
本发明提供一种用于双列存储器模块(DIMM)的堆叠式DRAM存储器芯片，它具有：
(a)预定数目(M)的堆叠式DRAM存储器管芯；
(b)其中每一个DRAM存储器管芯都可以通过相应的存储器队列信号(r)选择；
(c)其中每一个DRAM存储器管芯都包括存储单元阵列；
(d)其中由地址线构成的公用的内部地址总线是为寻址存储单元而设置的并连接到所有M个堆叠式DRAM存储器管芯；
(e)其中由内部数据线构成的M个内部数据总线是为把数据写入所述堆叠式DRAM存储器管芯的存储单元和从所述存储单元读出数据而设置的；
其中
(f)设置集成再驱动装置，所述集成再驱动装置包括：
(f1)为驱动施加在所述DRAM存储器芯片的地址焊盘上的外部地址信号而设置的用于所有内部地址线的缓冲区；和
(f2)多路器/多路分离器，它把选定的DRAM存储器管芯的内部数据线切换到所述DRAM存储器芯片的数据焊盘。
在推荐的存储器芯片上，所述再驱动装置还包括存储器队列解码器，所述存储器队列解码器用于响应施加在DRAM存储器芯片的控制焊盘上的外部选择信号而产生内部存储器队列信号。
其优点是，通过把存储器队列解码器集成在DRAM存储器芯片内，使必须通过命令和地址缓冲区向每一个DRAM芯片提供的选择信号的数量减少。因而，在双列存储器模块上选择信号线的数量减少，使得印刷电路板的尺寸减小，线路的路径选择复杂性降低。
在另一个实施例中，所述存储器队列解码器控制所述多路器/多路分离器。
在另一个实施例中，所述多路器/多路分离器包括用于缓冲通过所述切换的数据线发送的数据信号的缓冲区。
在按照本发明的堆叠式DRAM存储器芯片的推荐的实施例中，通过公用的内部时钟信号来为全部DRAM存储器管芯计时。
在按照本发明的堆叠式DRAM芯片的推荐的实施例中，所述再驱动装置还包括缓冲区，所述缓冲区用于驱动施加在DRAM存储器芯片的时钟焊盘上以便产生内部时钟信号的外部时钟信号。
在按照本发明的堆叠式DRAM存储器芯片的推荐的实施例中，DRAM管芯的堆叠和所述再驱动装置集成在所述DRAM存储器芯片上。
在按照本发明的DRAM存储器芯片的推荐的实施例中，所述再驱动装置通过所述DRAM存储器芯片的电源焊盘提供电源。
本发明还提供一种双列存储器模块，它包括多个堆叠式DRAM存储器芯片，其中每一个堆叠式DRAM存储器芯片具有：
(a)预定数目(M)的堆叠式DRAM存储器管芯；
(b)其中每一个DRAM存储器管芯都可以通过相应的存储器队列信号(r)选择；
(c)其中每一个DRAM存储器管芯都包括存储单元阵列；
(d)其中由地址线构成的公用的内部地址总线是为寻址存储单元而设置的并连接到所有M个堆叠式DRAM存储器管芯；
(e)其中由内部数据线构成的M个内部数据总线是为把数据写入所述堆叠式DRAM存储器管芯的存储单元和从所述存储单元读出数据而设置的；
(f)其中在堆叠式DRAM存储器管芯的下面设置再驱动装置，其中所述再驱动装置包括：
(f1)为驱动施加在所述DRAM存储器芯片的地址焊盘上的外部地址信号而设置的用于所有内部地址线的缓冲区；和
(f2)多路器/多路分离器，它把选定的DRAM存储器管芯的内部数据线切换到所述DRAM存储器芯片的数据焊盘。
在推荐的实施例中，双列存储器模块包括命令和地址缓冲区芯片，用于缓冲从主印刷电路板接收的命令和地址信号。
在按照本发明的双列存储器模块的推荐的实施例中，所述命令和地址缓冲区通过命令和地址总线连接到安装在所述双列存储器模块的印刷电路板上的全部堆叠式DRAM存储器芯片上。
附图说明
图1表示按照上述先有技术的双列存储器模块(DIMM)。
图2是如图1所示的按照先有技术的所述双列存储器模块的截面图。
图3表示按照先有技术的堆叠式DRAM芯片的截面。
图4表示按照本发明的堆叠式DRAM芯片的推荐实施例的截面图。
图5表示按照本发明的包括堆叠式DRAM芯片的双列存储器模块的顶视图。
具体实施方式
参见图4，它表示安装在双列存储器模块3的印刷电路板(PCB)2上的堆叠式DRAM存储器芯片1的截面。在所示实施例中，图4所示的堆叠式DRAM芯片1包括四个堆叠式DRAM存储器管芯4-0、4-1、4-2、4-3。每一个存储器管芯4-i都可以通过相应的存储器队列信号r-i选择。DRAM存储器管芯4-i包括存储单元阵列，可以通过地址线对所述存储单元阵列选址。公用内部地址总线5包括预定数目的内部地址线5-i，用于寻址存储器管芯4-i的存储器单元。作为例子，图4示出通过地址线5-i连接到所有存储器管芯4-i的地址焊盘A0。内部地址总线的所有地址线都并联到堆叠式DRAM芯片1的所有4个DRAM存储器管芯。如图4所示，存储器管芯4-i由通过内部时钟线6施加在全部存储器管芯的时钟信号CLK计时。每一个存储器管芯4-i都通过相应的内部数据总线7-i连接到DQ多路器/多路分离器8A。每一个内部数据总线7-i都包括预定数目的数据线，用于把相应的存储器管芯4-i连接到DQ多路器/多路分离器8A。每一个DQ数据总线7-i包括4至16条位线。所述内部数据总线DQ总线7-i是为了把数据写入堆叠式DRAM存储器管芯4-i的存储单元和从存储单元读出数据而设置的。
图4中所示的按照本发明的堆叠式DRAM芯片1包括在堆叠式DRAM存储器管芯4-i下面的再驱动装置8。再驱动装置8包括DQ多路器/多路分离器装置8A和缓冲区8B，用于为驱动施加在DRAM存储器芯片1的地址焊盘9-i的外部地址信号设置的全部内部地址线5-i。在所述推荐实施例中，如图4所示，再驱动装置8还包括缓冲区8C，用于驱动借助于时钟信号焊盘施加在DRAM芯片1上的时钟信号CLK。在全部实施例中，再驱动装置8都包括多路器/多路分离器8A，它把选定的DRAM存储器管芯的内部数据线或数据总线7-i切换到DRAM存储器芯片1的数据焊盘11。焊盘9、10、11是通过焊球或引脚形成的。在推荐的实施例中，每个DRAM芯片1的DQ线的数目q或者是4或者是8。
在推荐实施例中，如图4所示，再驱动装置8还包括存储器队列解码器8D，用于响应施加在DRAM存储器芯片1的控制焊盘12-0、12-1上的外部选择信号Si，产生内部存储器队列选择信号r-i。在所示的实施例中，存储器队列解码器8D接收两个外部选择信号S0、S1并对它们进行解码，以便产生四个存储器队列信号ri，它们通过控制线13-i施加在存储器管芯4-i上。
在图4的推荐实施例中，存储器队列解码器8D集成在堆叠式DRAM1的再驱动装置8内。在替代的实施例中，解码器8D集成在双列存储器模块3的中央命令和地址缓冲区。存储器队列解码器8D集成在再驱动装置8内的优点是，双列存储器模块3上的选择信号和选择线的数量可以减到最少。在图4的推荐实施例中，存储器队列解码器8D通过内部控制线14控制DQ多路器/多路分离器8A。在推荐的实施例中，多路器/多路分离器8A包括缓冲区，用于驱动通过切换数据线发送的数据信号。多路器/多路分离器8A响应写允许(WE)控制信号而从多路切换方式(读方式)切换到多路分离方式(写方式)。
DRAM存储器管芯4-i的堆叠和再驱动装置8集成在DRAM存储器芯片1内。为了增大每个双列存储器模块3的存储密度，所述各存储器管芯集成在FBGA(细间距网格焊球阵列)内。在堆叠式DRAM芯片1内设置再驱动装置8(它可以集成在FBGA封装中)允许增大存储器管芯4-i的数量，而不增大命令和地址缓冲区15的负载，而更重要的是不增大主板上的处理器的负载。这允许用于操作双列存储器模块3的高得多的工作频率。在推荐实施例中，如图所示，再驱动装置8设置在堆叠式DRAM芯片1的底侧所述存储器管芯堆叠的下面。
图5表示双列存储器模块3，它包括预定的数目N的如图4所示的堆叠式DRAM芯片1。DRAMs的数目N一般为9或18，取决于存储器队列的数目M。每一个堆叠式DRAM芯片1都包括M个堆叠式DRAM存储器管芯。堆叠式DRAM存储器管芯的数目M可以是1、2、4、8、16...个DRAM存储器管芯。双列存储器模块3还包括至少一个中央命令和地址缓冲区15，它位于双列存储器模块3的印刷电路板2的中间。命令和地址缓冲区15通过命令和地址总线16连接到双列存储器模块3上的全部DRAM存储器芯片1。命令和地址缓冲区15通过命令和地址线17从主印刷电路板接收命令和地址信号，并通过命令和地址总线16驱动器它们到全部DRAM芯片1。命令和地址缓冲区15还通过选择控制总线18接收选择信号，并通过选择信号总线19驱动器它们到全部DRAM芯片1。通过选择总线19施加在DRAM芯片1的选择信号，选择DRAM芯片和DRAM芯片1内的存储器管芯4-i。
若本机的存储器队列解码器8D集成在每一个堆叠式DRAM存储器芯片1的再驱动装置8内，则选择信号总线19的总线宽度S由下式给出：
          2s＝N+M
其中N是双列存储器模块3上DRAM芯片的数量，而
M是每一个DRAM芯片1内堆叠式存储器管芯或队列的数量。
在其中存储器队列解码器8D集成在命令和地址缓冲区15中而不在DRAM芯片1内的实施例中，选择控制总线19的总线宽度S由下式给出
           S＝1dN+M
在这两个实施例中，把用于通过选择线18将双列存储器模块3连接到母板的焊盘数量减到最少。
按照本发明的双列存储器模块3，如图5所示，还包括至少一个焊盘20，后者通过时钟线21连接到时钟信号缓冲区22。从母板接收的外部时钟信号是通过时钟信号缓冲区21缓冲的，并通过内部时钟线23施加在全部DRAM存储器芯片1。每一个DRAM芯片1都包括再驱动装置8，后者带有缓冲区8C，用于缓冲所接收的内部时钟信号。
采用按照本发明的堆叠式DRAM存储器芯片1，可以以非常高的存储密度达到多队列双列存储器模块3，而不增大母板上处理器的负载。因此，包括按照本发明的堆叠式DRAM存储器芯片1的双列存储器模块3允许较高的处理器工作频率。存储器管芯的堆叠提供单位板面积空前的存储密度，并同时提供所得双列存储器部件的优异的电气特性。按照本发明的双列存储器模块3与用于现有的双列存储器的插槽充分兼容。因为同样的互连技术用于堆叠式存储器管芯4-1上，所以这些管芯具有类似的电气参数。在推荐的实施例中，DRAM存储器芯片1按照芯片技术集成在BOC板的细间距网格焊球阵列封装(FPBC)。

Claims (12)

1.一种用于双列存储器模块(DIMM)的堆叠式DRAM存储器芯片，所述堆叠式DRAM存储器芯片具有：
(a)预定数目(M)的堆叠式DRAM存储器管芯；
(b)其中每一个DRAM存储器管芯都可以通过相应的存储器队列信号(r)选择；
(c)其中每一个DRAM存储器管芯都包括存储单元阵列；
(d)其中由地址线构成的公用的内部地址总线是为寻址存储单元而设置的并连接到所有M个堆叠式DRAM存储器管芯；
(e)其中由内部数据线构成的M个内部数据总线是为把数据写入所述堆叠式DRAM存储器管芯的存储单元和从所述存储单元读出数据而设置的；
其中
(f)设置集成再驱动装置，所述集成再驱动装置包括：
(f1)为驱动施加在所述DRAM存储器芯片的地址焊盘的外部地址信号而设置的用于所有内部地址线的缓冲区；以及
(f2)多路器/多路分离器，它把选定的DRAM存储器管芯的内部数据线切换到所述DRAM存储器芯片的数据焊盘。
2.如权利要求1所述的堆叠式DRAM存储器芯片，其中所述再驱动装置还包括存储器队列解码器，用于响应施加在所述DRAM存储器芯片的控制焊盘的外部选择信号而产生所述内部存储器队列信号。
3.如权利要求2所述的堆叠式DRAM存储器芯片，其中所述存储器队列解码器控制所述多路器/多路分离器。
4.如权利要求1所述的堆叠式DRAM存储器芯片，其中所述多路器/多路分离器响应写允许控制信号而在多路切换方式和多路分离方式之间切换。
5.如权利要求1所述的堆叠式DRAM存储器芯片，其中所述多路器/多路分离器包括缓冲区，用于驱动通过所述切换的数据线发送的数据信号。
6.如权利要求1所述的堆叠式DRAM存储器芯片，其中全部DRAM存储器管芯利用公用的内部时钟信号计时。
7.如权利要求6所述的堆叠式DRAM存储器芯片，其中所述再驱动装置还包括缓冲区，用于驱动施加在所述DRAM存储器芯片的时钟焊盘上的外部时钟信号，以便产生所述内部时钟信号。
8.如权利要求1所述的堆叠式DRAM存储器芯片，其中所述堆叠式DRAM存储器管芯和所述再驱动装置集成在DRAM存储器芯片内。
9.如权利要求1所述的堆叠式DRAM存储器芯片，其中通过所述DRAM存储器芯片的电源焊盘向所述再驱动装置供电。
10.一种包括多个堆叠式DRAM存储器芯片的双列存储器模块(DIMM)，其中每一个堆叠式DRAM存储器芯片具有：
(a)预定数目(M)的堆叠式DRAM存储器管芯；
(b)其中每一个DRAM存储器管芯都可以通过相应的存储器队列信号(r)选择；
(c)其中每一个DRAM存储器管芯都包括存储单元阵列；
(d)其中由地址线构成的公用的内部地址总线是为寻址存储单元而设置的并连接到所有M个堆叠式DRAM存储器管芯；
(e)其中由内部数据线构成的M个内部数据总线是为把数据写入所述堆叠式DRAM存储器管芯的存储单元和从所述存储单元读出数据而设置的；
(f)其中设置集成再驱动装置，所述集成再驱动装置包括：
(f1)为驱动施加在所述DRAM存储器芯片的地址焊盘的外部地址信号而设置的用于所有内部地址线的缓冲区；以及
(f2)多路器/多路分离器，它把选定的DRAM存储器管芯的内部数据线切换到所述DRAM存储器芯片的数据焊盘。
11.如权利要求10所述的双列存储器模块(DIMM)，其中所述双列存储器模块还包括命令和地址缓冲区芯片，用于缓冲从主印刷电路板接收的命令和地址信号。
12.如权利要求11所述的双列存储器模块，其中所述命令和地址缓冲区通过命令和地址总线连接到安装在所述双列存储器模块的印刷电路板上的全部堆叠式DRAM存储器芯片。
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