CN1838323A - 可预防固定模式编程的方法 - Google Patents

可预防固定模式编程的方法 Download PDF

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CN1838323A
CN1838323A CNA2006100059975A CN200610005997A CN1838323A CN 1838323 A CN1838323 A CN 1838323A CN A2006100059975 A CNA2006100059975 A CN A2006100059975A CN 200610005997 A CN200610005997 A CN 200610005997A CN 1838323 A CN1838323 A CN 1838323A
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阿萨夫·沙比尔
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Spansion Israel Ltd
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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/18—Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

一种可预防固定模式编程的方法，该方法包括将数据编程入存储器阵列中存储器单元的一种模式，并通过周期性扰动数据以预防固定程式编程，因此数据就被存储在存储器阵列中存储器单元的不同模式里。

Description

可预防固定模式编程的方法
技术领域
本发明涉及操作非易失存储器(NVM)阵列中的存储器单元，如编程和擦除，尤其涉及一种方法可预防在对单元历史记录编程和擦除时造成的巨大差动，如由于数据扰动引起的。
背景技术
现在的非易失存储器产品都具有对存储器单元进行电子编程和擦除功能。在多数情形下，如通常的编程操作中一样，擦除操作是对一子集单元进行，而非一个单元一个单元的进行。这就意味着直到最后(最慢)一个单元完成擦除，包括单元完成了预定水平的确认(擦除校验)，擦除条件才适用于该子集单元。
如图1所示，与氮化物只读存储器(NROM，nitride read-only memory)技术一样，由于在擦除时集成了隧道增强热孔注入，存储器产品要求晶体管结的高偏压通过带到带的隧道效应以产生注入孔。电荷注入必须得到控制以确保恰当的设备操作，因此步进和校验算法常被采用。在典型的算法中，在一定偏压的电荷注入后，是一校验操作以确认单元是否已达标。如仍未达标，就需要在更高的偏压下进行更强的电荷注入，反之亦然。
图2所示是现有技术中一个典型的擦除算法流程图，可用于NROM设备。
擦除脉冲可选择以擦除单元比特，包括选择(拨入)负栅压(Vg or Vcvpn-来自电荷泵的电压)及正漏压(Vppd)(步骤201)；擦除脉冲然后作用于单元集合上的比特(步骤202)；在擦除校验步骤(步骤203)中读取单元的阈电压以检查存储器单元的阈电压是否已降低至擦除校验(EV)电压水平。
如果没有单元通过擦除校验(EV)，就设定(拨入)一个新的正漏压Vppd，新漏压有强增加(如巨大)(步骤204)；如果有单元通过擦除校验(EV)，就设定一个新的正漏压Vppd，新的正漏压弱增强(如相对小)(步骤205)；在擦除脉冲作用于所有单元前，持续以上步骤。每个子群可接收额外脉冲以提高可靠性，额外脉冲比最终达到完全擦除的上一脉冲电平更高。附加脉冲的应用在不同的专利文献中有涉及，比如美国专利6,700,818及美国专利申请20050117395和20050058005，这些都已转让给本申请的现受让人，上述文献公开的内容在本申请中会引用。
为改善热孔注入的隧道效应，图2所示的步骤通常必须在存储器单元的两侧独立实施，其结果是更长的擦除时间和更低的执行效率。
由于存储在子集单元里的数据本质上更可能是随机的，在擦除操作前有些单元处于编程状态而有些处于擦除状态。因此，如果不采取特别措施，很可能先前的已编程单元(在上面已执行了擦除操作)会接近阈电压水平或达到擦除校验水平，而没有被编程的单元会由于阈电压显著低于擦除校验水平被过分擦除。这可在图3中看到，图中表明现有技术中在原始状态的、在未有任何操作前的及擦除后的(只有一个子群是预先编程的)子集单元的阈电压分布。被擦除的单元分布有两个峰值，高峰值出现在先前编程单元上的阈电压，而低峰值是出现在未编程单元，即被过分擦除的单元上的阈电压。
过分擦除的情况引发了一些问题。过分擦除的单元可能会变漏，即在未加偏压时会引导电流到“开”的状态(金属氧化物半导体场效应晶体管型的存储器单元的正栅压)；被过分擦除的单元可能会变的很难编程，即需要额外电压及时间使之进入编程状态(超过预先设定的水平，编程校验水平)。在操作环境(编程和擦除)中的实际误差可能会在被过分擦除的单元和未被过分擦除的单元间扩大。这些影响总和会最终导致存储器设备的故障，也就是失去数据的完整性。
参见图4，所示为现有技术中存储器阵列中的子群单元的阈电压分布，存储器阵列按固定模式的大循环(105循环)和检测板后续编程。由于缺少足够的预防过分擦除的措施，图中显示了已形成的散乱模式。
现有技术中预防单元过分擦除包括分隔擦除子群，该方法优点在于在较小的擦除子群时可保证更好的擦除一致性。然而其缺点是额外的时间开销(降低性能)和设计复杂。另一项涉及擦除前的编程的现有技术中的方法，可以确保单元在没被编程时不会经常地被擦除；然而这会带来实际操作中时间和能量的损失。
另一项涉及擦除前的编程的现有技术中的方法，可以确保单元在超出设定电平之上时不会被过分擦除；然而这同样会带来实际操作中时间和能量的损失。
发明内容
本发明是要提供一种可预防固定模式编程的方法，可预防在对存储器陈列中单元历史记录编程和擦除时造成的巨大差动，如下详述。本发明如下详述的部分涉及NVM阵列的存储器单元，特别涉及单比特、双比特、多比特和多电平NROM单元。但需强调，本发明不局限于NROM阵列。
按本发明一种可预防固定模式编程的方法的具体实施例所述，本发明方法包括将数据编程入存储器阵列中存储器单元的一种模式里，并通过周期性扰动数据以预防固定程式编程，因此数据被存储在存储器阵列中存储器单元的不同模式里。
可通过周期性的倒转数据实现数据扰动。另外可同时或者也可选择，通过周期性地对数据物理地址再排列以做到数据扰动。另外可同时或者也可选择，通过在编程中采用混和模式卷积数据并在读操作中展开卷积该数据以做到数据扰动。另外可同时或者也可选择，通过按编程和擦除循环计数器周期性地扰动数据以做到数据扰动。数据可以随机或伪随机地周期性扰动。
按本发明的一个实施例，数据扰动可由存储器阵列内部的存储参数的函数来实现，但不限于此。存储参数可以与数据一起被编程。
另外可同时或者也可选择，数据扰动可由数据的逻辑和/或物理地址函数来实现。
附图说明
下面结合附图对本发明作详细描述：
图1是现有技术中擦除NROM单元的简图，是通过隧道效应增强热孔注入；
图2是现有技术NROM设备中擦除算法的流程简图；
图3是现有技术中存储器阵列子群单元在原始状态、擦除后状态的阈电压分布图，该图中只有一个子集单元被预先编程；
图4是现有技术中存储器阵列子群单元的阈电压分布，存储器阵列按固定模式的大循环(105循环)和检测板后续编程；
图5是本发明一个具体实施例中用来预防固定模式编程的数据扰动编程流程的流程简图；
图6是本发明一个具体实施例中数据扰动应用时读取流程的流程简图。
具体实施方式
参见图5，如图是本发明的一个具体实施例，在一个非易失存储器阵列中用来预防固定模式编程的方法。需指出图5是在数据扰动应用中的编程流程的流程简图，下面进行阐释。
按本发明的一个实施例，在将数据编程入存储器阵列中存储器单元的一种模式里后，通过周期性扰动数据以预防固定程式编程，因此数据被存储在存储器阵列中存储器单元的不同模式里(步骤500)。在本发明的一个非限制性实施例中，实际的物理编程数据每个循环都被强迫改变(步骤501)。由此由于固定模式编程，系统误差可能扩大的比率会被大大减小。实际编程入单元阵列的数据可能是用户输入的操作的结果(步骤502)。这种操作可能会每个循环都不同(步骤503)，或者按计数器或预先设定的临界参数周期性改变(步骤504)。这种操作包括，但不限于，对输入的数据进行倒转、移位、转置(矩)阵，或者，混和比特、字、页面、输入数据或擦除子群的任何其他数据子集的内在地址，或者，通过变换混合模式来卷积输入数据。这种变化混和模式可以为每个循环或其他期间：固定的、变化的或随机的(步骤505)。
按本发明的一个未设限实施例，擦除扇区包括一组页面(每张单独编程)，输入页面数据根据计数器以及擦除扇区的页面位置而采取随机或伪随机模式进行卷积(步骤506)。由于计数器按每个循环变化，被编程到页面物理地址的实际数据也在变化(步骤507)。而且，即使输入数据对所有页面都是相同的，由于随机或伪随机模式也由擦除扇区的页面位置决定，被编程的实际数据在逐页变化(步骤508)。用于数据扰动和错误检测参数的计数器可在同一流程中被物理编程(步骤509)。如美国专利申请10/695,457(公布号US 20040136236)中所述，讨论了错误检测参数问题，相应的还有PCT申请WO 2005/041108“一种在非易失性存储器阵列中用于读取错误检测的回路和系统方法”，这两件专利都已转让给本发明的受让人。读取错误比率由多种错误比率样本和/或错误检测技术决定，比如奇偶比特、检查和、循环冗余校验及其他多种技术。任何错误检测译码和/或评估技术，无论现知的还是未来发展的，都可能应用于本发明。
参见图6，所示为图5中数据扰动应用时读取操作，是本发明一个具体实施例。数据可靠性不受扰动安排的影响。
在一个不受限具体实施例中，页面可被读取，包括错误检测参数(步骤601)。如果已使用了计数器，算法会评估计数器(步骤602)。然后对已使用的特别模式展开卷积(步骤603)，从而获得数据(步骤604)。
尽管本发明是按特别的实施例说明的，但很显然对本领域技术人员而言无需创造性即可有许多选择、变动和变化。因此，本申请包含所有这些选择、变动和变化。

Claims (11)

1、一种可预防固定模式编程的方法，该方法包括：将数据编程入存储器阵列中存储器单元的一种模式里，并通过周期性数据扰动以预防固定程式编程，该数据就被存储在存储器阵列中存储器单元的不同模式中。
2、根据权利要求1所述的方法，该周期性数据扰动包括周期性的倒转数据。
3、根据权利要求1所述的方法，该周期性数据扰动包括周期性地再排列所述数据物理地址。
4、根据权利要求1所述的方法，该周期性数据扰动包括在编程中采用混和模式卷积数据并在读取操作中展开卷积该被卷积数据。
5、根据权利要求1所述的方法，该周期性数据扰动包括按程序和擦除循环计数器周期性数据扰动。
6、根据权利要求1所述的方法，该数据被周期性地随机扰动。
7、根据权利要求1所述的方法，该数据被周期性地伪随机扰动。
8、根据权利要求1所述的方法，该周期性数据扰动包括，该扰动是存储器阵列内的存储参数的函数。
9、根据权利要求8所述的方法，所述存储参数与所述数据一起被编程。
10、根据权利要求1所述的方法，该周期性数据扰动包括，该扰动是所述数据的逻辑地址的函数。
11、根据权利要求1所述的方法，该周期性数据扰动包括，该扰动是所述数据的物理地址的函数。
CNA2006100059975A 2005-01-19 2006-01-18 可预防固定模式编程的方法 Pending CN1838323A (zh)

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