CN1848424A - 非凹槽式封装体 - Google Patents
非凹槽式封装体 Download PDFInfo
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- CN1848424A CN1848424A CNA2006100587726A CN200610058772A CN1848424A CN 1848424 A CN1848424 A CN 1848424A CN A2006100587726 A CNA2006100587726 A CN A2006100587726A CN 200610058772 A CN200610058772 A CN 200610058772A CN 1848424 A CN1848424 A CN 1848424A
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Abstract
本发明提供一种非凹槽式封装体。上述非凹槽式封装体包含:一非凹槽式基底具有相反的第一表面与第二表面,上述第一表面上具有一外部接点;第一晶片通过焊线与上述非凹槽式基底的上述第一表面连接;一封装胶体覆盖上述第一晶片;一导体凸块凸出于上述非凹槽式基底的第二表面,且与其电性连接;尺寸大于上述第一晶片的第二晶片,具有一主动表面电性连接于上述导电凸块;以及一底胶置于上述第二晶片与上述非凹槽式基底的第二表面之间,而将上述导体凸块封于其中。本发明所述的非凹槽式封装体,可提升制程良率,并减少使用本发明的非凹槽式封装体的终端产品的外观尺寸。
Description
技术领域
本发明是有关于半导体制程,特别是关于多晶片模组(multi-chip module;MCM)。
背景技术
图1是显示一现有的晶片堆叠封装体,其具有一基底100,具有第一表面101与第二表面102。而锡球150是置于第一表面101上。焊锡凸块112是电性连接基板100的第二表面102与大晶片110(例如为数字晶片)的主动表面。一小晶片120(例如为模拟晶片),则叠于大晶片110的背面。小晶片120是通过焊线131与132,与基底100连接。
然而,大晶片110与小晶片120之间的晶片面积的差异,会造成品质上的问题。如图1所示,较长的焊线132有可能会接触到大晶片110的边缘,而有可能在形成封装胶体140的封胶制程中,偏离既定位置并接触到邻近的其他焊线(未绘示),因而发生焊线短路(wire short;以下简称“线短”)的问题,而对制程良率造成不良影响。另外,晶片堆叠封装体的高度通常为1.4~1.6mm,且无法再缩减其尺寸。
为了解决上述线短的问题,通常从修改小晶片120的焊垫排列方面着手。改良后的小晶片120中,焊垫仅排列于其主动表面的两侧。将此改良后的小晶片粘于大晶片110背面的边缘附近时,就可以减少所需的焊线长度而减少上述线短的问题。然而,上述的修改方式却必须增加小晶片120的晶片面积,而会增加其制造的成本。
美国专利US 6,620,648揭露一种多晶片模组,包含第一晶片、第二晶片、与夹于二者之间的层积层。上述层积层包含一上侧、下侧、与中央沟道(central passage)。上述第一晶片是通过一粘着层,粘于上述层积层的下侧,并通过经过上述中央沟道的焊线,电性连接于上述层积层的上侧。上述第二晶片是使用一凸块,上述凸块是置于上述层积层的上侧中上述中央沟道以外的区域,而通过上述凸块介于上述第二晶片与上述层积层之间的状态,将两者电性连接。上述多晶片模组是具有较小的外观尺寸,但仍无法避免潜在的线短问题。其中,经由上述沟道连接至上述层积层上侧焊垫的焊线,仍有可能会接触到上述第二晶片,而与其发生短路。
美国专利US 6,506,633揭露一种多晶片模组,包含内嵌于一封装基底中的一晶片,可缩减多晶片模组的外观尺寸并减少线短的问题。其基底的制程实质上包含上述内嵌晶片的封装,当基底的制程中因坏片而必须报废时,往往会牺牲掉内嵌的可用晶片(good die),而有高制造成本的问题。
发明内容
有鉴于此,本发明的一目的是提供一种非凹槽式封装体及其制造方法,可缩减封装体的外观尺寸,并在不增加额外成本负担及不会衍生其他品质问题的情况下,避免线短问题的发生,因此可提升制程良率,并减少使用本发明的非凹槽式封装体的终端产品的外观尺寸。
为达成本发明的上述目的,本发明是提供一种非凹槽式封装体,包含:一非凹槽式基底具有相反的第一表面与第二表面;第一晶片通过焊线与上述非凹槽式基底的上述第一表面连接;一封装胶体覆盖上述第一晶片;以及尺寸大于上述第一晶片的第二晶片,电性连接于上述非凹槽式基底的上述第二表面。
本发明所述的非凹槽式封装体,其中该第二晶片与该第一晶片的面积比不小于2。
本发明所述的非凹槽式封装体,其中该第二晶片与该第一晶片的面积比为2至4。
本发明所述的非凹槽式封装体,其中该非凹槽式基底为阵列式的基底,包含多个封装单元。
本发明所述的非凹槽式封装体,其中该非凹槽式基底位于该第一晶片与该第二晶片之间,形成三明治结构。
本发明所述的非凹槽式封装体,其中该第一晶片具有矩形的主动表面、与多个焊线连接垫,该些焊线连接垫是沿着该主动表面的四边排列。
本发明是又提供一种非凹槽式封装体,包含:一非凹槽式基底具有相反的第一表面与第二表面,上述第一表面上具有一外部接点;第一晶片通过焊线与上述非凹槽式基底的上述第一表面连接;一封装胶体覆盖上述第一晶片;一导体凸块凸出于上述非凹槽式基底的第二表面,且与其电性连接;尺寸大于上述第一晶片的第二晶片,具有一主动表面电性连接于上述导电凸块;以及一底胶置于上述第二晶片与上述非凹槽式基底的第二表面之间,而将上述些导体凸块封于其中。
本发明所述的非凹槽式封装体,其中该第二晶片与该第一晶片的面积比不小于2。
本发明所述的非凹槽式封装体,其中该第二晶片与该第一晶片的面积比为2至4。
本发明所述的非凹槽式封装体,其中该非凹槽式基底为阵列式的基底,包含多个封装单元。
本发明所述的非凹槽式封装体,其中该非凹槽式基底位于该第一晶片与该第二晶片之间,形成三明治结构。
本发明所述的非凹槽式封装体,更包含一软焊料球状接合物于该外部接点上。
本发明所述的非凹槽式封装体,其中该封装胶体的厚度不大于该软焊料球状接合物。
本发明所述的非凹槽式封装体,其中该第一晶片具有矩形的主动表面、与多个焊线连接垫,该些焊线连接垫是沿着该主动表面的四边排列。
本发明所述的非凹槽式封装体,更包含一第二封装胶体覆盖该第二晶片与该底胶。
本发明是提供一种非凹槽式封装体,包含:一非凹槽式基底具有相反的第一表面与第二表面,上述第一表面上具有一外部接点;第一晶片通过焊线与上述非凹槽式基底的上述第一表面连接;第一封装胶体覆盖上述第一晶片;一导体凸块凸出于上述非凹槽式基底的第二表面,且与其电性连接;尺寸大于上述第一晶片的第二晶片,具有一主动表面电性连接于上述导电凸块;一底胶置于上述第二晶片与上述非凹槽式基底的第二表面之间,而将上述些导体凸块封于其中;以及第二封装胶体覆盖上述第二晶片与上述底胶。
本发明是提供一种非凹槽式封装体的制造方法,包含:提供一非凹槽式基底,具有相反的第一表面与第二表面,上述第一表面上具有一外部接点;通过焊线连接的方式,将第一晶片连接至上述非凹槽式基底的上述第一表面;形成一封装胶体覆盖上述第一晶片;以覆晶接合的方式,经由一导体凸块,将尺寸大于上述第一晶片的第二晶片,连接于上述非凹槽式基底的上述第二表面;以及一形成底胶于上述第二晶片与上述非凹槽式基底的第二表面之间,而将上述些导体凸块封于其中。
本发明是提供一种非凹槽式封装体的制造方法,包含:提供一非凹槽式基底,具有相反的第一表面与第二表面,上述第一表面上具有一外部接点;以覆晶接合的方式,经由一导体凸块,将尺寸大于上述第二晶片,电性连接于上述非凹槽式基底的上述第二表面;一形成底胶于上述第二晶片与上述非凹槽式基底的第二表面之间,而将上述些导体凸块封于其中;形成第二封装胶体覆盖上述第二晶片与上述底胶;通过焊线连接的方式,将小于上述第二晶片的第一晶片连接至上述非凹槽式基底的上述第一表面;以及形成第一封装胶体覆盖上述第一晶片。
本发明所述的非凹槽式封装体,可有效地缩减封装体的外观尺寸,并在不增加额外成本负担及不会衍生其他品质问题的情况下,避免线短问题的发生,因此可提升制程良率,并减少使用本发明的非凹槽式封装体的终端产品的外观尺寸。
附图说明
图1为一剖面图,是显示一传统的多晶片模组;
图2为一剖面图,是显示本发明第一实施例的非凹槽式封装体;
图3为一剖面图,是显示本发明第二实施例的非凹槽式封装体;
图4为一剖面图,是显示本发明第三实施例的非凹槽式封装体;
图5为一俯视图,是显示用于本发明上述实施例的半导体晶片。
具体实施方式
为了让本发明的上述和其他目的、特征和优点能更明显易懂,下文特举数个较佳实施例,并配合所附图示,作详细说明如下:
图2是显示本发明第一实施例的非凹槽式封装体。上述封装体包含一非凹槽式基底200、第一晶片210、一封装胶体240与第二晶片220。
非凹槽式基底200,其不具有凹槽,因此其可以是阵列式基底,可具有多个封装单元,可同时进行封装作业而可增加产出,而其中一个封装单元是绘示于图2中。非凹槽式基底200包含相反的第一表面201与第二表面202。第一表面201上具有一外部接点203,可电性连接至一外部元件例如一电子设备的印刷电路板。非凹槽式基底200可以是导线架、印刷电路板、或是其他已知的封装基底;在本实施例中,非凹槽式基底200为印刷电路板。在某些实施例中,非凹槽式基底200可具有二层或二层以上的线路。在某些实施例中,非凹槽式基底200的厚度最薄可达0.20mm;而在一较佳的实施例中,非凹槽式基底200的厚度为约0.26mm。
第一晶片210是粘着于非凹槽式基底200的第一表面201上,并通过焊线与其电性连接,其中一焊线212是将第一晶片210电性连接至非凹槽式基底200的第一表面201。第一晶片210的一实施例是绘示于图5中,在该实施例中,第一晶片210是具有一矩形的主动表面,位于其主动表面上的焊线连接垫211,是沿着其主动表面的四边排列,而可减少所需的晶片面积,而降低其制造成本。
封装胶体240,例如为热固性树脂与二氧化硅填充物的混合物,是覆盖第一晶片210与焊线212以保护其不受外在环境因素所造成的伤害。
第二晶片220,通常大于第一晶片210,是电性连接于非凹槽式基底200的第二表面202。另外,第二晶片220亦可以小于第一晶片210。在某些实施例中,第二晶片220与第一晶片210的面积比不小于2;而在某些特定的实施例中,第二晶片220与该第一晶片210的面积比为2~4。
第二晶片220较好为以倒装技术连接于非凹槽式基底200,以缩减封装体的尺寸。例如在图2中,一导体凸块222是凸出于非凹槽式基底200的第二表面202并与其电性连接;而第二晶片220则电性连接于导体凸块222。导体凸块222可以是软焊料、金、铜、具导电性的有机材料、或是其他的导体材料。在其他实施例中,亦可使用焊线接合、引带式自动接合(tape-automatic bonding;TAB)、或是其他可用以连接第二晶片220与非凹槽式基底200的封装技术。非凹槽式基底200较好为位于第二晶片220与第一晶片210之间而形成三明治结构,以减少封装体所占用的面积。
在某些实施例中,可使用被动元件、连接器或已封装的集成电路来取代第二晶片220。在某些实施例中,可将一散热器(未绘示)导热性地连接于第二晶片220以帮助其散热。
由于第一晶片210连接于第一表面201、而第二晶片220连接于第二表面202,本发明的非凹槽式封装体就不需要使用到长焊线,而两晶片的面积差异亦不会引发线短的问题。另外,本发明的非凹槽式封装体更不会增加额外成本负担、且不会衍生其他品质问题。
请参考图3,在本发明第二实施例中,一底胶260是置于第二晶片220与非凹槽式基底200的第二表面202之间。底胶260的热膨胀系数是介于第二晶片220与非凹槽式基底200之间,而作为热应力作用的缓冲层,上述热应力会因某些环境因素例如温度的循环所引发。底胶260更可将导体凸块222封于其内。
在某些实施例中,本发明的非凹槽式封装体可包含一软焊料球状接合物250于外部接点203上,其可含铅、而亦可以是无铅材质,视需求而定。封装胶体240的厚度较好为不大于软焊料球状接合物250的厚度。软焊料球状接合物250在一较佳实施例中,软焊料球状接合物250的厚度为约0.4mm,而封装胶体240的厚度则小于0.3mm。
在某些实施例中,本发明的非凹槽式封装体的厚度不大于1.0mm。在一较佳实施例中,第二晶片220的厚度约0.2mm、连接于第二晶片220与非凹槽式基底200之间的软焊料凸块222的厚度约0.07mm、非凹槽式基底200的厚度约0.26mm、而软焊料球状接合物250的厚度约0.4mm,因此其非凹槽式封装体的厚度约0.93mm。
关于本发明的非凹槽式封装体的其他元件的详细叙述,与第一实施例中所述等效的,在此便予以省略。
请参考图4,在本发明第三实施例中,是形成有一封装胶体207,而覆盖第二晶片220。封装胶体可对第二晶片220提供额外保护,避免因为环境因素例如碰撞所造成的伤害。封装胶体207的形成可能会略微增加本发明的非凹槽式封装体的厚度,在某些实施例中,其厚度可不大于1.1mm。
关于本发明的非凹槽式封装体的其他元件的详细叙述,与第一、二实施例中所述等效的,在此便予以省略。
如上所述,本发明的非凹槽式封装体,可有效地缩减封装体的外观尺寸,并在不增加额外成本负担及不会衍生其他品质问题的情况下,避免线短问题的发生,因此可提升制程良率,并减少使用本发明的非凹槽式封装体的终端产品的外观尺寸。
本发明另外提供一实施例,是关于例如图3所示的非凹槽式封装体的制造方法。首先,提供一非凹槽式基底200,其具有相反的第一表面201与第二表面202,第一表面201具有一外部接点203于其上。然后将第一晶片210粘着于非凹槽式基底200的第一表面201上并以焊线连接的方式与其连接。在某些实施例中,可将一导电性或绝缘性的热固性粘着剂(未绘示)置于第一表面201的预定粘着区上,再将第一晶片210粘着于上述粘着剂上,而后再使其硬化。在某些实施例中,一焊线212例如为金线或铝线,是用以将第一晶片210电性连接至非凹槽式基底200的第一表面201。
接下来,形成一封装胶体240覆盖第一晶片210。在某些实施例中,例如将具有热固性环氧树脂与二氧化硅填充物的液态胶体,以点胶的方式来形成封装胶体240而覆盖第一晶片210,接下来使上述液态胶体硬化而完成封装胶体240。焊线212通常为封装胶体240所覆盖。
接下来,将第二晶片220粘着于非凹槽式基底200的第二表面202上并以倒装法的技术,经由两者之间的导电凸块222,使第二晶片220与非凹槽式基底200的第二表面202电性连接。在某些实施例中,导电凸块222可预先形成于第二晶片220的一主动表面上,然后在第二晶片220以主动表面朝下的方式粘于非凹槽式基底200的第二表面202后,经由回流(reflow),而形成两者之间的电性连接。而在其他实施例中,导电凸块222亦可预先形成于非凹槽式基底200的第二表面202上的凸块连接垫上,然后在第二晶片的粘着后与其电性连接。
最后,将一底胶260置于第二晶片220与非凹槽式基底200的第二表面202之间,而作为缓冲层,以吸收因第二晶片220与非凹槽式基底200之间热膨胀系数的差异所造成的热应力。底胶260是将导电凸块222封于其中。如上所述,是完成了图3所示的非凹槽式封装体。
另外,可以更形成一封装胶体207以覆盖第二晶片220,而对其提供额外的保护。在某些实施例中,可以射出成型的方法来形成封装胶体207。如上所述,是完成了图4所示的非凹槽式封装体。
另外,上述本发明的非凹槽式封装体的制造方法的实施顺序亦可视需要加以变化。例如,可先将第二晶片220粘着于非凹槽式基底200的第二表面202上并以倒装法的技术,经由两者之间的导电凸块222,使第二晶片220与非凹槽式基底200的第二表面202电性连接。然后,将一底胶260置于第二晶片220与非凹槽式基底200的第二表面202之间。接下来亦可以更形成一封装胶体207以覆盖第二晶片220。而再通过焊线连接的方式,将小于第二晶片220的第一晶片210连接至非凹槽式基底200的第一表面201。最后再形成第一封装胶体240覆盖第一晶片210,而完成图4所示的非凹槽式封装体。
另外,本发明的非凹槽式封装体的制造方法,亦可包含将软焊料球状接合物250形成于外部接点203上的步骤,其形成方法可以是网板印刷、电镀、植球、或是其他方法。
虽然本发明已通过较佳实施例说明如上,但该较佳实施例并非用以限定本发明。本领域的技术人员,在不脱离本发明的精神和范围内,应有能力对该较佳实施例做出各种更改和补充,因此本发明的保护范围以权利要求书的范围为准。
附图中符号的简单说明如下:
100:基底
101:第一表面
102:第二表面
110:大晶片
112:焊锡凸块
120:小晶片
131、132:焊线
140:封装胶体
200:非凹槽式基底
201:第一表面
202:第二表面
203:外部接点
207:封装胶体
210:第一晶片
212:焊线
220:第二晶片
222:导体凸块
240:封装胶体
250:软焊料球状接合物
260:底胶
Claims (15)
1.一种非凹槽式封装体,该非凹槽式封装体包含:
一非凹槽式基底具有相反的第一表面与第二表面;
第一晶片通过焊线与该非凹槽式基底的该第一表面连接;
一封装胶体覆盖该第一晶片;以及
尺寸大于该第一晶片的第二晶片,电性连接于该非凹槽式基底的该第二表面。
2.根据权利要求1所述的非凹槽式封装体,其特征在于,该第二晶片与该第一晶片的面积比不小于2。
3.根据权利要求1所述的非凹槽式封装体,其特征在于,该第二晶片与该第一晶片的面积比为2至4。
4.根据权利要求1所述的非凹槽式封装体,其特征在于,该非凹槽式基底为阵列式的基底,包含多个封装单元。
5.根据权利要求1所述的非凹槽式封装体,其特征在于,该非凹槽式基底位于该第一晶片与该第二晶片之间,形成三明治结构。
6.根据权利要求1所述的非凹槽式封装体,其特征在于,该第一晶片具有矩形的主动表面、与多个焊线连接垫,该焊线连接垫是沿着该主动表面的四边排列。
7.一种非凹槽式封装体,该非凹槽式封装体包含:
一非凹槽式基底具有相反的第一表面与第二表面,该第一表面上具有一外部接点;
第一晶片通过焊线与该非凹槽式基底的该第一表面连接;
一封装胶体覆盖该第一晶片;
一导体凸块凸出于该非凹槽式基底的第二表面,且与其电性连接;
尺寸大于该第一晶片的第二晶片,具有一主动表面电性连接于该导电凸块;以及
一底胶置于该第二晶片与该非凹槽式基底的第二表面之间,而将该导体凸块封于其中。
8.根据权利要求7所述的非凹槽式封装体,其特征在于,该第二晶片与该第一晶片的面积比不小于2。
9.根据权利要求7所述的非凹槽式封装体,其特征在于,该第二晶片与该第一晶片的面积比为2至4。
10.根据权利要求7所述的非凹槽式封装体,其特征在于,该非凹槽式基底为阵列式的基底,包含多个封装单元。
11.根据权利要求7所述的非凹槽式封装体,其特征在于,该非凹槽式基底位于该第一晶片与该第二晶片之间,形成三明治结构。
12.根据权利要求7所述的非凹槽式封装体,其特征在于,更包含一软焊料球状接合物于该外部接点上。
13.根据权利要求12所述的非凹槽式封装体,其特征在于,该封装胶体的厚度不大于该软焊料球状接合物。
14.根据权利要求7所述的非凹槽式封装体,其特征在于,该第一晶片具有矩形的主动表面、与多个焊线连接垫,该焊线连接垫是沿着该主动表面的四边排列。
15.根据权利要求7所述的非凹槽式封装体,其特征在于,更包含一第二封装胶体覆盖该第二晶片与该底胶。
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US9536798B2 (en) * | 2012-02-22 | 2017-01-03 | Cyntec Co., Ltd. | Package structure and the method to fabricate thereof |
TWI503934B (zh) | 2013-05-09 | 2015-10-11 | Advanced Semiconductor Eng | 半導體元件及其製造方法及半導體封裝結構 |
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US5200362A (en) * | 1989-09-06 | 1993-04-06 | Motorola, Inc. | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
US5994166A (en) * | 1997-03-10 | 1999-11-30 | Micron Technology, Inc. | Method of constructing stacked packages |
SG83742A1 (en) * | 1999-08-17 | 2001-10-16 | Micron Technology Inc | Multi-chip module with extension |
US6506633B1 (en) * | 2002-02-15 | 2003-01-14 | Unimicron Technology Corp. | Method of fabricating a multi-chip module package |
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US20060231960A1 (en) | 2006-10-19 |
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